MC74VHC374 D

MC74VHC374
Octal D-Type Flip-Flop
with 3-State Output
The MC74VHC374 is an advanced high speed CMOS octal
flip−flip with 3−state output fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
This 8−bit D−type flip−flop is controlled by a clock input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
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MARKING DIAGRAMS
20
SOIC−20
DW SUFFIX
CASE 751D
20
1
1
20
Features
•
•
•
•
•
•
•
•
•
•
•
•
VHC374
AWLYYWWG
High Speed: fmax = 185 MHz (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 4 μA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2 V to 5.5 V Operating Range
Low Noise: VOLP = 0.9 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 266 FETs or 66.5 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
TSSOP−20
DT SUFFIX
CASE 948E
20
1
1
20
SOEIAJ−20
M SUFFIX
CASE 967
1
20
1
VHC
374
ALYWG
G
VHC374
AWLYWWG
VHC374 = Specific Device Code
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W
= Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
MC74VHC374DWR2G SOIC−20 1000 Units/Reel
MC74VHC374DTR2G TSSOP−20 2500 Units/T&R
MC74VHC374MELG
SOEIAJ−20 2000 Units/Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 6
1
Publication Order Number:
MC74VHC374/D
MC74VHC374
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CP
OE
3
2
4
5
7
6
8
9
13
12
14
15
17
16
18
19
Q0
OE
1
20
VCC
Q1
Q0
2
19
Q7
Q2
D0
3
18
D7
D1
4
17
D6
Q1
5
16
Q6
Q2
6
15
Q5
D2
7
14
D5
D3
8
13
D4
Q3
9
12
Q4
10
11
CP
Q3
Q4
NONINVERTING
OUTPUTS
Q5
Q6
Q7
11
GND
Figure 2. PIN ASSIGNMENT
1
Figure 1. LOGIC DIAGRAM
FUNCTION TABLE
INPUTS
OE
L
L
L
H
OUTPUT
CP
D
Q
L, H,
X
H
L
X
X
H
L
No Change
Z
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2
MC74VHC374
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MAXIMUM RATINGS*
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to VCC + 0.5
V
IIK
Input Diode Current
− 20
mA
IOK
Output Diode Current
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute−maximum−rated
conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
5.5
V
VCC
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
− 40
+ 85
_C
0
0
100
20
ns/V
TA
Operating Temperature
tr, tf
Input Rise and Fall Time
VCC = 3.3V
VCC = 5.0V
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VCC
V
Test Conditions
VIH
Minimum High−Level
Input Voltage
2.0
3.0 to
5.5
VIL
Maximum Low−Level
Input Voltage
2.0
3.0 to
5.5
VOH
Minimum High−Level
Output Voltage
Vin = VIH or VIL
IOH = − 50μA
Vin = VIH or VIL
IOH = − 4mA
IOH = − 8mA
VOL
Maximum Low−Level
Output Voltage
Vin = VIH or VIL
IOL = 50μA
TA = 25°C
Min
Min
1.9
2.9
4.4
3.0
4.5
2.58
3.94
3.0
4.5
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Max
1.50
VCC x 0.7
0.50
VCC x 0.3
2.0
3.0
4.5
3
Max
1.50
VCC x 0.7
2.0
3.0
4.5
Vin = VIH or VIL
IOL = 4mA
IOL = 8mA
Typ
TA = − 40 to 85°C
2.0
3.0
4.5
Unit
V
0.50
VCC x 0.3
V
V
1.9
2.9
4.4
2.48
3.80
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.36
0.36
0.44
0.44
V
MC74VHC374
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DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VCC
V
Test Conditions
TA = 25°C
Min
Typ
TA = − 40 to 85°C
Max
Min
Max
Unit
Iin
Maximum Input
Leakage Current
Vin = 5.5V or GND
0 to 5.5
± 0.1
± 1.0
μA
IOZ
Maximum
Three−State Leakage
Current
Vin = VIL or VIH
Vout = VCC or GND
5.5
± 0.25
± 2.5
μA
ICC
Maximum Quiescent
Supply Current
Vin = VCC or GND
5.5
4.0
40.0
μA
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
fmax
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
tOSLH,
tOSHL
Parameter
Maximum Clock Frequency
(50% Duty Cycle)
Maximum Propagation Delay,
CP to Q
Output Enable Time,
OE to Q
Output Disable Time,
OE to Q
Output to Output Skew
Test Conditions
Min
Typ
TA = − 40 to 85°C
Max
Min
Max
Unit
ns
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
80
55
130
85
70
50
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
130
85
185
120
110
75
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
8.1
10.6
12.7
16.2
1.0
1.0
15.0
18.5
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
5.4
6.9
8.1
10.1
1.0
1.0
9.5
11.5
VCC = 3.3 ± 0.3V
RL = 1kΩ
CL = 15pF
CL = 50pF
7.1
9.6
11.0
14.5
1.0
1.0
13.0
16.5
VCC = 5.0 ± 0.5V
RL = 1kΩ
CL = 15pF
CL = 50pF
5.1
6.6
7.6
9.6
1.0
1.0
9.0
11.0
VCC = 3.3 ± 0.3V
RL = 1kΩ
CL = 50pF
10.2
14.0
1.0
16.0
VCC = 5.0 ± 0.5V
RL = 1kΩ
CL = 50pF
6.1
8.8
1.0
10.0
VCC = 3.3 ± 0.3V
(Note 1)
CL = 50pF
1.5
1.5
ns
VCC = 5.0 ± 0.5V
(Note 1)
CL = 50pF
1.0
1.0
ns
10
10
pF
Cin
Maximum Input Capacitance
4
Cout
Maximum Three−State Output
Capacitance (Output in
High−Impedance State)
6
ns
ns
ns
pF
Typical @ 25°C, VCC = 5.0V
CPD
32
Power Dissipation Capacitance (Note 2)
pF
1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per flip−flop). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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4
MC74VHC374
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25°C
Symbol
Parameter
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.6
0.9
V
VOLV
Quiet Output Minimum Dynamic VOL
− 0.6
− 0.9
V
VIHD
Minimum High Level Dynamic Input Voltage
3.5
V
VILD
Maximum Low Level Dynamic Input Voltage
1.5
V
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
Parameter
Typ
Test Conditions
TA = − 40
to 85°C
Limit
Limit
Unit
tw
Minimum Pulse Width, CP
VCC = 3.3 ± 0.3 V
VCC = 5.0 ± 0.5 V
5.0
5.0
5.5
5.0
ns
tsu
Minimum Setup Time, D to CP
VCC = 3.3 ± 0.3 V
VCC = 5.0 ± 0.5 V
4.5
3.0
4.5
3.0
ns
th
Minimum Hold Time, D to CP
VCC = 3.3 ± 0.3 V
VCC = 5.0 ± 0.5 V
2.0
2.0
2.0
2.0
ns
Maximum Input Rise and Fall Times
VCC = 3.3 ± 0.3 V
VCC = 5.0 ± 0.5 V
tr, tf
ns
SWITCHING WAVEFORMS
VCC
VCC
CP
OE
50%
50%
GND
GND
tPZL
tPLZ
tW
1/fmax
tPLH
Q
Q
HIGH
IMPEDANCE
50% VCC
VOL +0.3V
tPHL
tPZH
50% VCC
Q
tPHZ
VOH -0.3V
50% VCC
Figure 3.
Figure 4.
VALID
VCC
D
50%
GND
th
tsu
VCC
CP
50%
GND
Figure 5.
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5
HIGH
IMPEDANCE
MC74VHC374
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
CL*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6.
D0
3
Q
OE
D2
7
D
C
CP
Figure 7.
D1
4
D
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kΩ
OUTPUT
Q
D3
8
D
C
Q
D4
13
D
C
Q
D5
14
D
C
Q
D6
17
D
C
Q
D7
18
D
C
Q
D
C
Q
C
11
1
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
Figure 8. EXPANDED LOGIC DIAGRAM
INPUT
Figure 9. INPUT EQUIVALENT CIRCUIT
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6
15
Q5
16
Q6
19
Q7
MC74VHC374
PACKAGE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
A
20
q
X 45 _
E
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
18X
e
A1
SEATING
PLANE
C
T
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7
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74VHC374
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
−U−
PIN 1
IDENT
SECTION N−N
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
N
F
DETAIL E
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
6.40
6.60
0.252
0.260
B
4.30
4.50
0.169
0.177
----C
1.20
0.047
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
−W−
H
0.27
0.37
0.011
0.015
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0_
8_
0_
8_
PLANE
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
http://onsemi.com
8
MC74VHC374
PACKAGE DIMENSIONS
SOEIAJ−20
CASE 967−01
ISSUE A
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.15
0.25
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.81
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.006
0.010
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.032
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MC74VHC374/D