MC14043B D

MC14043B, MC14044B
CMOS MSI
Quad R−S Latches
The MC14043B and MC14044B quad R−S latches are constructed
with MOS P−Channel and N−Channel enhancement mode devices in
a single monolithic structure. Each latch has an independent Q output
and set and reset inputs. The Q outputs are gated through three−state
buffers having a common enable input. The outputs are enabled with
a logical “1” or high on the enable input; a logical “0” or low
disconnects the latch from the Q outputs, resulting in an open circuit at
the Q outputs.
Features
• Double Diode Input Protection
• Three−State Outputs with Common Enable
• Outputs Capable of Driving Two Low−power TTL Loads or One
•
•
•
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SOIC−16
D SUFFIX
CASE 751B
MARKING DIAGRAMS
16
Low−Power Schottky TTL Load Over the Rated Temperature
Range
Supply Voltage Range = 3.0 Vdc to 18 Vdc
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
140xxBG
AWLYWW
1
SOIC−16
16
MC14043B
ALYWG
MAXIMUM RATINGS (Voltages Referenced to VSS)
Value
Unit
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
Symbol
VDD
Vin, Vout
Iin, Iout
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
SOEIAJ−16
F SUFFIX
CASE 966
1
SOEIAJ−16
xx
A
WL, L
YY, Y
WW, W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 10
1
Publication Order Number:
MC14043B/D
MC14043B, MC14044B
PIN ASSIGNMENT
MC14043B
MC14044B
Q3
1
16
VDD
Q3
1
16
VDD
Q0
2
15
R3
NC
2
15
S3
R0
3
14
S3
S0
3
14
R3
S0
4
13
NC
R0
4
13
Q0
E
5
12
S2
E
5
12
R2
S1
6
11
R2
R1
6
11
S2
R1
7
10
Q2
S1
7
10
Q2
VSS
8
9
Q1
VSS
8
9
Q1
NC = NO CONNECTION
MC14043B
S0
R0
S1
R1
S2
R2
S3
4
MC14044B
2
R0
Q0
3
S0
6
9
R1
Q1
7
12
VDD = PIN 16
VSS = PIN 8
NC = PIN 13
10
S1
R2
Q2
11
S2
14
TRUTH TABLE
1
Q3
S R E
Q
X X 0
High
Impedance
15
R3
5
ENABLE
0
0
1
1
0
1
0
1
R3
4
13
Q0
3
6
9
Q1
7
12
VDD = PIN 16
VSS = PIN 8
NC = PIN 2
10
Q2
11
14
TRUTH TABLE
1
Q3
S R E
Q
X X 0
High
Impedance
15
S3
1 No Change
1
0
1
1
1
1
5
ENABLE
X = Don’t Care
0
0
1
1
0
1
0
1
1
0
1
1
1
0
1 No Change
X = Don’t Care
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2
MC14043B, MC14044B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
− 55_C
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
25_C
VDD
Vdc
Min
Max
Min
Typ
(Note 2)
125_C
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
“0” Level
VIL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
–3.0
–0.64
–1.6
–4.2
−
−
−
−
–2.4
–0.51
–1.3
–3.4
–4.2
–0.88
–2.25
–8.8
−
−
−
−
–1.7
–0.36
–0.9
–2.4
−
−
−
−
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
15
−
±0.1
−
±0.00001
±0.1
−
±1.0
mAdc
Input Capacitance
(Vin = 0)
Cin
−
−
−
−
5.0
7.5
−
−
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
−
−
−
1.0
2.0
4.0
−
−
−
0.002
0.004
0.006
1.0
2.0
4.0
−
−
−
30
60
120
mAdc
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs all
buffers switching)
IT
5.0
10
15
Three−State Output Leakage
Current
ITL
15
Vin = 0 or VDD
Input Voltage
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
mAdc
IT = (0.58 mA/kHz) f + IDD
IT = (1.15 mA/kHz) f + IDD
IT = (1.73 mA/kHz) f + IDD
±0.1
−
−
±0.0001
±0.1
mAdc
−
±3.0
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL − 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.004.
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3
MC14043B, MC14044B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Vdc
Min
Typ
(Note 6)
Max
5.0
10
15
−
−
−
100
50
40
200
100
80
5.0
10
15
−
−
−
100
50
40
200
100
80
5.0
10
15
−
−
−
175
75
60
350
175
120
Unit
Output Rise Time
tTLH = (1.35 ns/pF) CL + 32.5 ns
tTLH = (0.60 ns/pF) CL + 20 ns
tTLH = (0.40 ns/pF) CL + 20 ns
tTLH
Output Fall Time
tTHL = (1.35 ns/pF) CL + 32.5 ns
tTHL = (0.60 ns/pF) CL + 20 ns
tTHL = (0.40 ns/pF) CL + 20 ns
tTHL
Propagation Delay Time
tPLH = (0.90 ns/pF) CL + 130 ns
tPLH = (0.36 ns/pF) CL + 57 ns
tPLH = (0.26 ns/pF) CL + 47 ns
tPLH
tPHL = (0.90 ns/pF) CL + 130 ns
tPHL = (0.90 ns/pF) CL + 57 ns
tPHL = (0.26 ns/pF) CL + 47 ns
tPHL
5.0
10
15
−
−
−
175
75
60
350
175
120
ns
Set, Set Pulse Width
tW
5.0
10
15
200
100
70
80
40
30
−
−
−
ns
Reset, Reset Pulse Width
tW
5.0
10
15
200
100
70
80
40
30
−
−
−
ns
tPLZ,
tPHZ,
tPZL,
tPZH
5.0
10
15
−
−
−
150
80
55
300
160
110
ns
Three−State Enable/Disable Delay
ns
ns
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
AC WAVEFORMS
MC14043B
MC14044B
20 ns
50%
10%
20 ns
50%
tPHL
VDD
90%
10%
VSS
20 ns
90% VDD
VDD
10%
10%
50%
20 ns
90%
tTHL
Q
SET
VSS
20 ns
RESET
20 ns
VDD
90%
SET
20 ns
20 ns
50%
RESET
VSS
tTLH
tTHL
tTLH
VOH
90%
50%
10%
Q
50%
VOL
90%
10%
tPLH
tPLH
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4
tPHL
VSS
VOH
VOL
MC14043B, MC14044B
THREE−STATE ENABLE/DISABLE DELAYS
Set, Reset, Enable, and Switch Conditions for 3−State Tests
MC14043B
VDD
MC14044B
S1
S2
Q
S
R
S
R
tPZH
Open
Closed
A
VDD
VSS
VSS
VDD
tPZL
Closed
Open
B
VSS
VDD
VDD
VSS
tPHZ
Open
Closed
A
VDD
VSS
VSS
VDD
tPLZ
Closed
Open
B
VSS
VDD
VDD
VSS
Test
Enable
S1
TO
OUTPUT
UNDER
TEST
1k
CL
50 pF
S2
VSS
VDD
ENABLE
50%
VSS
tPZH
VDD
90%
QA
10%
tPZL
tPHZ
VOL
tPLZ
VOH
QB
10%
VSS
ORDERING INFORMATION
Package
Shipping†
MC14043BDG
SOIC−16
(Pb−Free)
48 Units / Rail
NLV14043BDG*
SOIC−16
(Pb−Free)
48 Units / Rail
MC14043BDR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
NLV14043BDR2G*
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
SOEIAJ−16
(Pb−Free)
2000 Units / Tape & Reel
MC14044BDG
SOIC−16
(Pb−Free)
48 Units / Rail
NLV14044BDG*
SOIC−16
(Pb−Free)
48 Units / Rail
MC14044BDR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
NLV14044BDR2G*
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
Device
MC14043BFELG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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5
MC14043B, MC14044B
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC14043B, MC14044B
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
CASE 966
ISSUE A
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
9
Q1
M_
E HE
1
L
8
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.78
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.031
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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For additional information, please contact your local
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MC14043B/D