NB6L56 D

NB6L56
2.5V / 3.3V Dual 2:1
Differential Clock / Data
Multiplexer with LVPECL
Outputs
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Multi−Level Inputs w/ Internal Termination
The NB6L56 is a high performance Dual 2−to−1 Differential Clock
or Data multiplexer. The differential inputs incorporate internal 50 W
termination resistors that are accessed through the VT pin. This feature
allows the NB6L56 to accept various Differential logic level
standards, such as LVPECL, CML or LVDS. Outputs are 800 mV
LVPECL signals. For interface options see Figures 12 − 15.
The NB6L56 produces minimal Clock or Data jitter operating up to
2.5 GHz or 2.5 Gbps, respectively. As such, the NB6L56 is ideal for
SONET, GigE, Fiber Channel, Backplane and other Clock/Data
distribution applications.
The NB6L56 is offered in a low profile 5 mm x 5 mm 32−pin QFN
package and is a member of the ECLinPS MAX™ family of high
performance Clock / Data products. Application notes, models, and
support documentation are available at www.onsemi.com.
Features
• Maximum Input Data Rate > 2.5 Gbps
• Maximum Input Clock Frequency > 2.5 GHz
• Jitter
•
•
•
•
< 1 ps RMS RJ (Data)
< 10 ps PP DJ (Data)
< 0.7 ps RMS Crosstalk induced jitter (CLOCK)
360 ps Max Propagation Delay
180 ps Max Rise and Fall Times
Operating Range:
VCC = 2.5 ± 5% (2.375 V to 2.625 V)
VCC =3.3 ± 10% (3.0 V to 3.6 V)
Internal 50 W Input Termination Resistors
Industrial Temp. Range (−40°C to 85°C)
QFN−32 Package
These are Pb−Free Devices
•
•
•
•
Clock and Data Distribution
Networking and Communications
High End Computing
Wireless and Wired Infrastructure
•
•
•
•
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
•
•
•
MARKING DIAGRAM*
1
NB6L
56
AWLYYWWG
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
A
B
End Products
May, 2012 − Rev. 0
32
*For additional marking information, refer to
Application Note AND8002/D.
Applications
© Semiconductor Components Industries, LLC, 2012
1
QFN32
MN SUFFIX
CASE 488AM
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
1
Publication Order Number:
NB6L56/D
NB6L56
INA0
50 W
VTA0
50 W
INA0
2:1
Mux A
VREFACA0
QA
QA
INA1
50 W
VTA1
50 W
INA1
VCC
VREFACA1
SELA
INB0
50 W
VTB0
50 W
INB0
VREFACB0
2:1
Mux B
QB
INB1
50 W
VTB1
50 W
INB1
QB
VCC
VREFACB1
SELB
VCC
GND
Figure 2. Pin Configuration (Top View)
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2
INA1
VREFACA1
VTA1
INA1
INA0
VREFACA0
VTA0
INA0
NB6L56
32
31
30
29
28
27
26
25
Exposed Pad (EP)
INB0
1
24 GND
VTB0
2
23 VCC
VREFACB0
3
22 QA
INB0
4
21 QA
NB6L56
18 SELA
INB1
8
17 VCC
9
10
11
12
13
14
15
16
VCC
7
SELB
VREFACB1
NC
19 NC
VCC
6
QB
VTB1
QB
20 VCC
VCC
5
GND
INB1
Figure 3. NB6L56 Pinout: QFN−32 (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Pin Description
1, 4
5, 8
25, 28
29, 32
INB0, INB0
INB1, INB1
INA0, INA0
INA1, INA1
2, 6
26, 30
VTB0, VTB1
VTA0, VTA1
3
7
27
31
VREFACB0
VREFACB1
VREFACA0
VREFACA1
15
18
SELB
SELA
14, 19
NC
−
10, 13,16,17
20, 23
VCC
Power
11, 12
21, 22
QB, QB
QA, QA
LVPECL
Output
Inverted, Non−inverted Differential Outputs Note 1.
9, 24
GND
Ground
Negative Supply Voltage, connected to Ground
−
EP
−
LVPECL, CML, Noninverted, Inverted Differential Input pairs (Note 1). Default state is
LVDS Input
indeterminate if left floating open. Do not connect unused input pairs with
one input connected to VCC and the complementary input to GND. For
differential and single ended interface, see “Interface Applications”.
Internal 100 W Center−tapped Termination Pin for Differential Input pairs
(Figure 4)
−
Output Voltage Reference for Capacitor−Coupled Inputs or Single
Ended Interface (see “Interface Applications”)
LVTTL /
Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH
LVCMOS Input when left open
No Connect
Positive Supply Voltage. All VCC pins must be connected to the positive
power supply for correct DC and AC operation.
The Exposed Pad (EP) on the package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must
be attached to a heat−sinking conduit. The pad is connected to the die
and must only be connected electrically to GND on the PC board.
1. If no signal is applied on any INxn input pair, the device will be susceptible to self−oscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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NB6L56
Table 2. INPUT SELECT FUNCTION TABLE
SELA/SELB
Q
Q
L
INx0
INx0
H
INx1
INx1
Table 3. ATTRIBUTES
Characteristic
ESD Protection
Value
Human Body Model
Machine Model
Input Pullup resistor (RPU)
>2 kV
200 V
75 kW
Moisture Sensitivity (Note 3)
QFN32
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Level 1
UL 94 V−0 @ 0.125 in
1023
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 4)
Symbol
VCC
VINPP
IIN
IOUT
Parameter
Condition 1
Positive Power Supply
Condition 2
GND = 0 V
Rating
Unit
4.0
V
Differential Input Voltage |INx − INx|
1.89
V
Input Current Through RT (50 W Resistor)
±40
mA
±50
±100
mA
Output Current
Continuous
Surge
IVREFAC
VREFAC Sink/Source Current
±1.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(Note 4)
qJC
Thermal Resistance (Junction−to−Case) (Note 4)
yJC
Tsol
0 lfpm
500 lfpm
QFN*32
QFN*32
31
27
°C/W
Standard Board
QFN*32
12
°C/W
Thermal Resistance (Junction−to−Board)
16
°C/W
Wave Solder Pb−Free
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power) with eight filled thermal vias under exposed pad.
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NB6L56
Table 5. DC CHARACTERISTICS VCC = 2.5 ± 5% (2.375 V to 2.625 V); VCC = 3.3 ± 10% (3.0 V to 3.6 V) (Note 5)
Symbol
ICC
Characteristic
Min
Power Supply Current (Inputs and Outputs Open)
Typ
Max
Unit
65
85
mA
LVPECL OUTPUTS
VOH
Output HIGH Voltage
VCC – 1.145
VCC − 0.895
mV
VOL
Output LOW Voltage
VCC – 2.000
VCC − 1.695
mV
VOUT
Output Swing (Single Ended)
Output Swing (Differential)
400
800
800
1600
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Note 6) (Figures 5 and 6)
Vth
Input Threshold Reference Voltage Range
VIH
Single−ended Input HIGH Voltage
VIL
Single−ended Input LOW Voltage
Single−ended Input Voltage (VIH − VIL ) (Note 6)
VISE
1125
VCC − 75
mV
Vth + 75
VCC
mV
GND
Vth − 75
mV
150
3015
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Note 7) (Figures 7 and 8)
VIHD
Differential Input HIGH Voltage
1200
VCC
mV
VILD
Differential Input LOW Voltage
GND
VIHD − 100
mV
VID
Differential Input Voltage (VIHD − VILD)
100
1890
mV
VCMR
Input Common Mode Range (Differential Configuration) (Figure 9)
1150
VCC − 50
mV
IIH
Input HIGH Current (VTnx Open)
−150
150
mA
IIL
Input LOW Current (VTnx Open)
−150
150
mA
LVTTL / LVCMOS INPUTS (SELA/SELB)
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIL
Input LOW Current (VIN = 0.5 V)
IIH
Input HIGH Current (VCC)
2.0
V
0.8
−300
V
mA
75
mA
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor INxn/INxn to VTxn
45
50
55
W
VCC − 1.35
VCC − 1.2
VCC − 1.1
V
REFERENCE VOLTAGE
VREF−AC
Output Reference Voltage
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Outputs evaluated with 50 W resistors to VTT = VCC − 2.0 V for proper operation (See Figure 16).
6. VTH is applied to the complementary input when operating in single−ended mode. VIH, VIL and VTH parameters must be complied with
simultaneously.
7. VIHD, VILD and VCMR parameters must be complied with simultaneously. VCMR max varies 1:1 with VCC.
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NB6L56
Table 6. AC CHARACTERISTICS VCC = 2.5 ± 5% (2.375 V to 2.625 V); VCC = 3.3 ± 10% (3.0 V to 3.6 V) (Note 8)
Symbol
fMAX
fSEL
VOUTPP
tPLH,
tPHL
tPLH Tempco
Characteristic
Min
Maximum Input Clock Frequency
Maximum Operating Data Rate (NRZ)
Voutpp w 400 mV
Voutpp w 400 mV
Typ
25
Output Voltage Amplitude (Differential Interconnect) fin ≤ 2.5 GHz
400
Propagation Delay to Differential Outputs, @ 1 GHz,
INxn/INxn to Qx, Qx
SELx to Qx, Qx
160
100
50
250
260
143
tskew
Input to Input per Bank Within Device
Output Bank to Output Bank Within Device
10
12
tJITTER
DATA JITTER
20
25
Cycle to Cycle (1K WFMS; RMS)
Total Jitter TJ (PP)
1
10
Crosstalk Induced Jitter Input to Input per Output Bank Within Device (Note 9)
35
Input Voltage Swing (Differential Configuration) (Note 10)
100
Output Rise/Fall Times @ 1 GHz (20% − 80%), Qx, Qx
50
100
ps
Dfs/°C
1
10
tJITTER
tr,, tf
360
400
RJ for K28.7 at 2.5 GHz (RMS)
DJ for NRZ PRBS23 / K28.5 at 2.5 Gbps
Integrated Phase Jitter fin = 155.52 MHz and 1GHz 12 kHz * 20 MHz Offset
(RMS)
VINPP
MHz
mVpp
Differential Propagation Delay Temperature Coefficient
tjit(f)
Unit
Ghz
Gbps
2.5
Maximum Toggle Frequency, SELA/SELB
CLOCK JITTER
Max
2.5
ps
ps
fs
0.7
psRMS
1200
mV
180
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Differential 50% duty cycle at VINPPmin clock source. Outputs evaluated with 50 W resistors to VTT = VCC − 2.0 V (See Figure 16). Input
crosspoint to output crosspoint for INxn/INxn to Qx, Qx; 50% input to output crosspoint for SELx to Qx, Qx. See Figures 5, 10 and 11.
9. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
inputs.
10. Input voltage swing is a single−ended measurement operating in differential mode.
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6
NB6L56
VCC
INxn
VIH
Vth
VIL
INxn
50 W
Vth
VTxn
INxn
50 W
INxn
Figure 4. Simplified Input Structure
VCC
VIHmax
Vthmax
Vth
Figure 5. Differential Input Driven Single−Ended
VILmax
IN
VIH
Vth
VIL
IN
IN
VIHmin
Vthmin
VILmin
GND
Figure 6. Vth Diagram
Figure 7. Differential Inputs Driven Differentially
VCC
VIHDmax
VILDmax
VCMRmax
IN
IN
IN
VID = |VIHD(IN) − VILD(IN)|
VCMR
VIHD
VIHDtyp
VILDtyp
IN
VILD
VID = VIHD − VILD
VIHDmin
VCMRmin
VILDmin
GND
Figure 8. Differential Inputs Driven Differentially
Figure 9. VCMR Diagram
IN
VCC / 2
VINPP = VIH(IN) − VIL(IN)
IN
VCC / 2
SEL
tpd
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tpd
Qx
Qx
tPHL
tPLH
Figure 11. SEL to Qx Timing Diagram
Figure 10. AC Reference Measurement
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7
NB6L56
VCC
VCC
VCC
VCC
NB6L56
Zo = 50 W
LVPECL
Driver
50 W
Zo = 50 W
GND
RT3
GND
GND
Zo = 50 W
LVPECL
Driver
50 W
Zo = 50 W
INx
GND
50 W
LVPECL
Driver
50 W
GND
NB6L56
NB6L56
INx
Zo = 50 W
INx
VCC
VCC
50 W
Zo = 50 W
GND
50 W
VT = VCC − 2.0 V
INx
RT3 = 50 W @ 3.3 VCC
20 W @ 2.5 VCC
INx
INx
GND
GND
Figure 12. Typical LVPECL Interface (see AND8020)
VCC
VCC
NB6L56
Zo = 50 W
INx
50 W
LVDS
Driver
VT = OPEN
50 W
Zo = 50 W
INx
GND
GND
Figure 13. Typical LVDS Interface
VCC
VCC
Zo = 50 W
VCC
VCC
NB6L56
INx
Zo = 50 W
50 W
CML
Driver
VT = VCC
50 W
Zo = 50 W
GND
LVPECL
Driver
VT = VREFACxn*
GND
GND
GND
50 W
50 W
Zo = 50 W
INx
NB6L56
INx
INx
GND
GND
Figure 15. Typical LVPECL Capacitor−Coupled
Differential Interface (VT Connected to VREFAC)
Figure 14. Typical Standard 50 W Load CML
Interface
*VREFAC bypassed to ground with a 0.01 mF capacitor.
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NB6L56
NB6L56
Q
Zo = 50 W
D
Receiver
Device
LVPECL
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 16. Typical Termination for LVPECL Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping†
NB6L56MNG
QFN32
(Pb−Free)
74 Units / Rail
NB6L56MNTXG
QFN32
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB6L56
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM−01
ISSUE O
PIN ONE
LOCATION
2X
ÉÉ
ÉÉ
0.15 C
2X
A
B
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
32 X
0.08 C
C
L
32 X
9
D2
SEATING
PLANE
A1
SIDE VIEW
SOLDERING FOOTPRINT*
EXPOSED PAD
16
5.30
K
32 X
17
MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.180 0.250 0.300
5.00 BSC
2.950 3.100 3.250
5.00 BSC
2.950 3.100 3.250
0.500 BSC
0.200
−−−
−−−
0.300 0.400 0.500
3.20
8
32 X
0.63
E2
1
24
32
3.20
25
b
0.10 C A B
32 X
5.30
e
0.05 C
32 X
0.28
BOTTOM VIEW
28 X
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
NB6L56/D