NB7L585 2.5V / 3.3V Differential 2:1 Mux Input to 1:6 LVPECL Clock/Data Fanout Buffer / Translator http://onsemi.com Multi−Level Inputs w/ Internal Termination MARKING DIAGRAM 1 Description The NB7L585 is a differential 1:6 LVPECL Clock/Data distribution chip featuring a 2:1 Clock/Data input multiplexer with an input select pin. The INx/INx inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML, or LVDS logic levels. The NB7L585 produces six identical output copies of Clock or Data operating up to 5 GHz or 8 Gb/s, respectively. As such, NB7L585 is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The NB7L585 is powered with either 2.5 V or 3.3 V supply and is offered in a low profile 5mm x 5mm 32−pin QFN package. Application notes, models, and support documentation are available at www.onsemi.com. The NB7L585 is a member of the GigaComm™ family of high performance clock products. 32 1 QFN32 MN SUFFIX CASE 488AM NB7L 585 AWLYYWWG G A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) + SEL Features • • • • • • • • • • • • • • • Maximum Input Data Rate > 8 Gb/s Data Dependent Jitter < 15 ps Maximum Input Clock Frequency > 5 GHz Random Clock Jitter < 0.8 ps RMS Low Skew 1:6 LVPECL Outputs, 20 ps max 2:1 Multi−Level Mux Inputs 175 ps Typical Propagation Delay 55 ps Typical Rise and Fall Times Differential LVPECL Outputs, 800 mV peak−to−peak, typical Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V Internal 50 W Input Termination Resistors VREFAC Reference Output QFN−32 Package, 5mm x 5mm −40ºC to +85ºC Ambient Operating Temperature These Devices are Pb−Free and are RoHS Compliant Q0 VREFAC0 IN0 VT0 IN0 IN1 VT1 IN1 50 W 50 W Q0 Q1 0 Q1 Q2 Q2 Q3 50 W 50 W 1 Q3 Q4 VREFAC1 VCC GND Q4 Q5 Q5 Figure 1. Simplified Block Diagram ORDERING INFORMATION See detailed ordering and shipping information on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2009 December, 2009 − Rev. 1 1 Publication Order Number: NB7L585/D GND SEL VCC Q0 Q0 Q1 Q1 VCC NB7L585 32 31 30 29 28 27 26 25 Exposed Pad (EP) IN0 1 24 GND VT0 2 23 VCC VREFAC0 3 22 Q2 IN0 4 21 Q2 IN1 5 20 Q3 VT1 6 19 Q3 VREFAC1 7 18 VCC IN1 8 17 GND 10 11 12 13 14 15 16 VCC Q5 Q5 Q4 Q4 VCC GND 9 NC NB7L585 Table 1. INPUT SELECT FUNCTION TABLE SEL* CLK Input Selected 0 IN0 1 IN1 *Defaults HIGH when left open. Figure 2. Pinout: QFN−32 (Top View) Table 2. PIN DESCRIPTION Pin Number Pin Name I/O Pin Description 1,4 5,8 IN0, IN0 IN1, IN1 LVPECL, CML, LVDS Input 2,6 VT0, VT1 31 SEL LVTTL/LVCMOS Input 10 NC − No Connect 11, 16, 18 23, 25, 30 VCC − Positive Supply Voltage. All VCC pins must be connected to the positive power supply for correct DC and AC operation. 29, 28 27, 26 22, 21 20, 19 15, 14 13, 12 Q0, Q0 Q1, Q1 Q2,Q2 Q3, Q3 Q4, Q4 Q5, Q5 LVPECL Output Non−inverted, Inverted, Differential Data Inputs internally biased to VCC/2 Internal 100 W Center−tapped Termination Pin for IN0 / IN0 and IN1 / IN1 Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH when left open Non−inverted, Inverted Differential Outputs Note 1. 9, 17, 24, 32 GND 3 7 VREFAC0 VREFAC1 − Negative Supply Voltage, connected to Ground Output Voltage Reference for Capacitor−Coupled Inputs − EP − The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board. 1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on INn/INn input, then the device will be susceptible to self−oscillation. 2. All VCC and GND pins must be externally connected to a power supply for proper operation. http://onsemi.com 2 NB7L585 Table 3. ATTRIBUTES Characteristics Value ESD Protection Human Body Model Machine Model > 2 kV > 200 V QFN−32 Level 1 RPU − SEL Input Pullup Resistor 75 kW Moisture Sensitivity (Note 3) Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 288 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC Positive Power Supply GND = 0 V +4.0 V VIO Input/Output Voltage GND = 0 V −0.5 to VCC +0.5 V VINPP Differential Input Voltage |IN − IN| 1.89 V IIN Input Current Through RT (50 W Resistor) $40 mA Iout Output Current 50 100 mA IVREFAC VREFAC Sink or Source Current $1.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) (Note 4) qJC Thermal Resistance (Junction−to−Case) (Note 4) Tsol Wave Solder Continuous Surge 0 lfpm 500 lfpm QFN32 QFN32 QFN32 −65 to +150 °C 31 27 °C/W 12 °C/W 265 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB7L585 Table 5. DC CHARACTERISTICS POSITIVE LVPECL OUTPUT VCC = 2.375 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C (Note 5) Characteristic Symbol Min Typ Max Unit 3.0 2.375 3.3 2.5 3.6 2.625 V 185 225 mA POWER SUPPLY VCC Power Supply Voltage VCC = 3.3V VCC = 2.5V ICC Power Supply Current (Inputs and Outputs Open) LVPECL Outputs VOH Output HIGH Voltage (Note 6) VOL Output LOW Voltage (Note 6) VCC = 3.3 V VCC = 2.5 V VCC – 1145 2155 1355 VCC – 800 2500 1700 mV VCC = 3.3 V VCC = 2.5 V VCC – 2000 1300 500 VCC – 1500 1800 1000 mV DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figures 5 & 6) VIH Single−ended Input HIGH Voltage Vth + 100 VCC mV VIL Single−ended Input LOW Voltage GND Vth − 100 mV Vth Input Threshold Reference Voltage Range (Note 8) 1100 VCC −100 mV VISE Single−ended Input Voltage (VIH − VIL) 200 1200 mV VCC – 1000 mV VREFACx (for Capacitor− Coupled Inputs, Only) VREFAC Output Reference Voltage @100 mA for Capacitor− Coupled Inputs, Only VCC – 1500 VCC – 1200 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7 & 8) (Note 9) VIHD Differential Input HIGH Voltage (IN, IN) 1200 VCC mV VILD Differential Input LOW Voltage (IN , IN) GND VIHD − 100 mV VID Differential Input Voltage (IN , IN) (VIHD − VILD) 100 1200 mV VCMR Input Common Mode Range (Differential Configuration, Note 10) (Figure 9) 1050 VCC − 50 mV IIH Input HIGH Current IN/IN (VTIN/VTIN Open) −150 150 mA IIL Input LOW Current IN/IN (VTIN/VTIN Open) −150 150 mA CONTROL INPUT (SEL Pin) VIH Input HIGH Voltage for Control Pin 2.0 VCC mV VIL Input LOW Voltage for Control Pin GND 0.8 mV IIH Input HIGH Current −150 150 mA IIL Input LOW Current −150 150 mA 55 W TERMINATION RESISTORS RTIN Internal Input Termination Resistor (Measured from INx to VTx) 45 50 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. 6. LVPECL outputs (Qn/Qn) loaded with 50 W to VCC – 2 V for proper operation. 7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB7L585 Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C (Note 11) Symbol Min Typ fMAX Maximum Input Clock Frequency; VOUTpp w 400 mV Characteristic 5 7 GHz fDATAMAX Maximum Operating Data Rate (PRBS23) 8 10 Gbps fSEL Maximum Toggle Frequency, SEL 1.0 1.5 GHz VOUTpp Output Voltage Amplitude (@ VINPPmin) (Note 12) (Figures 8 and 10) 550 400 800 650 mV tPLH, tPHL Propagation Delay to Differential Outputs, @ 1 GHz, measured at differential crosspoint 125 75 175 200 tPLH TC Propagation Delay Temperature Coefficient tskew Output − Output skew (within device) (Note 13) Device − Device skew (tpd max – tpdmin) tDC Output Clock Duty Cycle (Reference Duty Cycle = 50%) FN Phase Noise, fin = 1 GHz tŐFN tJITTER fin ≤ 4 GHz fin ≤ 5 GHz IN/IN to Q/Q SEL to Q Max 250 300 50 fin v 5.0 GHz 45 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz 40 MHz 50 Unit ps Dfs/°C 20 100 ps 55 % −135 −137 −149 −150 −150 −151 dBc Integrated Phase Jitter (Figure x) fin = 1 GHz, 12 kHz * 20 MHz Offset (RMS) 36 fs RJ – Output Random Jitter (Note 14) DJ − Residual Output Deterministic Jitter (Note 15) 0.2 5 fin ≤ 5.0 GHz ≤ 8 Gbps Crosstalk Induced Jitter (Adjacent Channel) (Note 17) VINPP Input Voltage Swing (Differential Configuration) (Note 16) 100 tr,, tf Output Rise/Fall Times @ 1 GHz (20% − 80%), Q, Q 25 55 0.8 15 ps rms ps pk−pk 0.7 psRMS 1200 mV 85 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured using a 400 mV pk−pk source, 50% duty cycle clock source. All output loading with external 50 W to VCC – 2 V. Input edge rates 40 ps (20% − 80%). 12. Output voltage swing is a single−ended measurement operating in differential mode. 13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from cross−point of the inputs to the crosspoint of the outputs. 14. Additive RMS jitter with 50% duty cycle clock signal. 15. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23. 16. Input voltage swing is a single−ended measurement operating in differential mode. 17. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the inputs. OUTPUT VOLTAGE AMPLITUDE (mV) 1000 Q AMP (mV) 800 600 400 200 0 0 1 2 3 4 5 6 fin, CLOCK INPUT FREQUENCY (GHz) 7 8 Figure 3. Clock Output Voltage Amplitude (VOUTpp) vs. Input Frequency (fin) at Ambient Temperature (Typical) http://onsemi.com 5 NB7L585 IN VIH Vth INx VIL 50 W IN VTx Vth 50 W INx Figure 5. Differential Input Driven Single−Ended Figure 4. Input Structure VCC VIHmax Vthmax Vth VILmax IN VIH Vth VIL IN IN VIHmin Vthmin VILmin VEE Figure 6. Vth Diagram Figure 7. Differential Inputs Driven Differentially VCC VIHDmax VILDmax VCMRmax IN IN IN VID = |VIHD(IN) − VILD(IN)| VCMR VIHD VIHDtyp VILDtyp IN VILD VID = VIHD − VILD VIHDmin VCMRmin VILDmin VEE Figure 9. VCMR Diagram Figure 8. Differential Inputs Driven Differentially IN VCC / 2 VINPP = VIH(IN) − VIL(IN) IN VCC / 2 SEL tpd Q VOUTPP = VOH(Q) − VOL(Q) Q tpd Qx Qx tPHL tPLH Figure 11. SEL to Qx Timing Diagram Figure 10. AC Reference Measurement http://onsemi.com 6 NB7L585 VCC VCC VCC NB7L585 IN Zo = 50 W LVPECL Driver VCC 50 W VT = VCC − 2.0 V 50 W LVDS Driver 50 W Zo = 50 W VT = OPEN 50 W Zo = 50 W IN CLKx GND GND Figure 12. LVPECL Interface GND Figure 13. LVDS Interface VCC VCC VCC VCC NB7L585 IN Zo = 50 W Zo = 50 W 50 W 50 W VT = VREFAC* 50 W Zo = 50 W IN GND GND Figure 15. Capacitor−Coupled Differential Interface (VT Connected to VREFAC) Figure 14. Standard 50 W Load CML Interface *VREFAC bypassed to ground with a 0.01 mF capacitor. Zo = 50 W D Receiver Device Driver Device Q IN GND GND Q NB7L585 IN 50 W Differential Driver VT = VCC Zo = 50 W IN CLKx GND CML Driver NB7L585 IN Zo = 50 W D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 16. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 7 NB7L585 DEVICE ORDERING INFORMATION Package Shipping† NB7L585MNG QFN−32 (Pb−Free) 74 Units / Rail NB7L585MNR4G QFN−32 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 8 NB7L585 PACKAGE DIMENSIONS PIN ONE LOCATION 2X ÉÉ ÉÉ 0.15 C 2X QFN32 5*5*1 0.5 P CASE 488AM−01 ISSUE O A B D NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 0.15 C (A3) 0.10 C A 32 X 0.08 C C L 32 X 9 D2 SEATING PLANE A1 SIDE VIEW MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 −−− −−− 0.300 0.400 0.500 SOLDERING FOOTPRINT* EXPOSED PAD 16 K 5.30 32 X 17 8 3.20 E2 1 32 X 0.63 24 32 25 32 X b 0.10 C A B 3.20 e 5.30 0.05 C BOTTOM VIEW 32 X 0.28 28 X 0.50 PITCH *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. GigaComm is a trademark of Semiconductor Component Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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