MCR25DG, MCR25MG, MCR25NG Silicon Controlled Rectifiers Reverse Blocking Thyristors Designed primarily for half−wave ac control applications, such as motor controls, heating controls, and power supplies; or wherever half−wave, silicon gate−controlled devices are needed. www.onsemi.com SCRs 25 AMPERES RMS 400 thru 800 VOLTS Features • • • • • • • • Blocking Voltage to 800 Volts On-State Current Rating of 25 Amperes RMS High Surge Current Capability − 300 Amperes Rugged, Economical TO−220AB Package Glass Passivated Junctions for Reliability and Uniformity Minimum and Maximum Values of IGT, VGT, and IH Specified for Ease of Design High Immunity to dv/dt − 100 V/msec Minimum @ 125°C These are Pb−Free Devices* G A K MARKING DIAGRAM AY WW MCR25xG AKA MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Peak Repetitive Off−State Voltage (Note 1) (TJ = −40 to 125°C, Sine Wave, 50 to 60 Hz, Gate Open) MCR25DG MCR25MG MCR25NG VDRM, VRRM On-State RMS Current (180° Conduction Angles; TC = 80°C) IT(RMS) 25 A ITSM 300 A I2t 373 A2sec PGM 20.0 W Peak Non-repetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 125°C) Circuit Fusing Consideration (t = 8.3 ms) Forward Peak Gate Power (Pulse Width ≤ 1.0 ms, TC = 80°C) Forward Average Gate Power (t = 8.3 ms, TC = 80°C) Value Unit V 1 2 TO−220AB CASE 221A−09 STYLE 3 3 400 600 800 PG(AV) 0.5 W Forward Peak Gate Current (Pulse Width ≤ 1.0 ms, TC = 80°C) IGM 2.0 A Operating Junction Temperature Range TJ −40 to +125 °C Storage Temperature Range Tstg −40 to +150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. A Y WW x G AKA = Assembly Location = Year = Work Week = D, M, or N = Pb−Free Package = Diode Polarity PIN ASSIGNMENT 1 Cathode 2 Anode 3 Gate 4 Anode ORDERING INFORMATION Device Package Shipping MCR25DG TO−220AB (Pb−Free) 50 Units / Rail MCR25MG TO−220AB (Pb−Free) 50 Units / Rail MCR25NG TO−220AB (Pb−Free) 50 Units / Rail *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2015 January, 2015 − Rev. 6 1 Publication Order Number: MCR25/D MCR25DG, MCR25MG, MCR25NG THERMAL CHARACTERISTICS Characteristic Thermal Resistance, Symbol Value Unit RqJC RqJA 1.5 62.5 °C/W TL 260 °C Junction−to−Case Junction−to−Ambient Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max − − − − 0.01 2.0 Unit OFF CHARACTERISTICS Peak Repetitive Forward or Reverse Blocking Current (VAK = Rated VDRM or VRRM, Gate Open) IDRM IRRM TJ = 25°C TJ = 125°C mA ON CHARACTERISTICS Peak Forward On-State Voltage (Note 2) (ITM = 50 A) VTM − − 1.8 V Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 W) IGT 4.0 12 30 mA Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 W) VGT 0.5 0.67 1.0 V Holding Current (VD =12 Vdc, Initiating Current = 200 mA, Gate Open) IH 5.0 13 40 mA Latching Current (VD = 12 V, IG = 30 mA) IL − 35 80 mA Critical Rate of Rise of Off−State Voltage (VD = 67% of Rated VDRM, Exponential Waveform, Gate Open, TJ = 125°C) dv/dt 100 250 − V/ms Critical Rate of Rise of On−State Current (IPK = 50 A, Pw = 30 msec, diG/dt = 1 A/msec, Igt = 50 mA) di/dt − − 50 A/ms DYNAMIC CHARACTERISTICS Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Indicates Pulse Test: Pulse Width ≤ 2.0 ms, Duty Cycle ≤ 2%. Voltage Current Characteristic of SCR + Current Symbol Parameter VDRM Peak Repetitive Off State Forward Voltage IDRM Peak Forward Blocking Current VRRM Peak Repetitive Off State Reverse Voltage IRRM Peak Reverse Blocking Current VTM Peak On State Voltage IH Holding Current Anode + VTM on state IRRM at VRRM Reverse Blocking Region (off state) Reverse Avalanche Region Anode − www.onsemi.com 2 IH + Voltage IDRM at VDRM Forward Blocking Region (off state) 40 1.0 35 0.9 VGT, GATE TRIGGER VOLTAGE (V) I GT, GATE TRIGGER CURRENT (mA) MCR25DG, MCR25MG, MCR25NG 30 25 20 15 10 5 0 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (°C) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (°C) Figure 2. Typical Gate Trigger Voltage versus Junction Temperature I T, INSTANTANEOUS ON-STATE CURRENT (A) Figure 1. Typical Gate Trigger Current versus Junction Temperature 1 Typical @ 25°C R(t) TRANSIENT THERMAL R (NORMALIZED) 100 Maximum @ 125°C 10 Maximum @ 25°C 1 0.1 Z +R qJC @ R(t) 0.01 0.5 0.9 1.3 1.7 2.1 2.5 2.9 0.1 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) Figure 3. Typical On−State Characteristics 1 10 100 t, TIME (ms) 1000 1@104 Figure 4. Transient Thermal Response 100 IL , LATCHING CURRENT (mA) 100 I H , HOLDING CURRENT (mA) qJC(t) 0.1 10 10 1 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (°C) 1 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (°C) Figure 5. Typical Holding Current versus Junction Temperature Figure 6. Typical Latching Current versus Junction Temperature www.onsemi.com 3 P(AV), AVERAGE POWER DISSIPATION (WATTS) MCR25DG, MCR25MG, MCR25NG 130 TC , CASE TEMPERATURE ( °C) 120 a a = Conduction Angle 110 100 dc 90 80 a = 30° 0 60° 180° 90° 2 4 6 8 10 12 14 16 18 IT(RMS), RMS ON−STATE CURRENT (AMPS) 20 32 28 180° a 24 16 a = 30° 12 8 4 0 0 2 4 6 8 10 12 14 16 18 IT(AV), AVERAGE ON−STATE CURRENT (AMPS) 20 Figure 8. On State Power Dissipation Figure 7. Typical RMS Current Derating 2500 1200 Gate Cathode Open, (dv/dt does not depend on RGK) Gate-Cathode Open, (dv/dt does not depend on RGK) 2000 STATIC dv/dt (V/us) 1000 800 85°C 600 100°C 110°C 1500 VPK = 275 1000 VPK = 400 400 VPK = 600 TJ = 125°C 500 200 0 VPK = 800 0 200 300 400 500 600 700 800 80 85 90 VPK , Peak Voltage (Volts) Figure 9. Typical Exponential Static dv/dt Versus Peak Voltage 95 100 105 110 TJ, Junction Temperature (°C ) 1 CYCLE 280 260 240 220 200 TJ=125° C f=60 Hz 180 160 1 2 3 115 120 Figure 10. Typical Exponential Static dv/dt Versus Junction Temperature 300 I TSM, SURGE CURRENT (AMPS) STATIC dv/dt (V/us) 90° 60° a = Conduction Angle 20 dc 4 5 6 7 NUMBER OF CYCLES 8 9 Figure 11. Maximum Non−Repetitive Surge Current www.onsemi.com 4 10 125 MCR25DG, MCR25MG, MCR25NG PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AH −T− B SEATING PLANE C F T S 4 DIM A B C D F G H J K L N Q R S T U V Z A Q 1 2 3 U H K Z L R V J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. G D INCHES MIN MAX 0.570 0.620 0.380 0.415 0.160 0.190 0.025 0.038 0.142 0.161 0.095 0.105 0.110 0.161 0.014 0.024 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ----0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.53 4.07 4.83 0.64 0.96 3.61 4.09 2.42 2.66 2.80 4.10 0.36 0.61 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ----2.04 N STYLE 3: PIN 1. 2. 3. 4. CATHODE ANODE GATE ANODE ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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