NLSX5012 2-Bit 100 Mb/s Configurable Dual-Supply Level Translator The NLSX5012 is a 2-bit configurable dual-supply autosensing bidirectional level translator that does not require a direction control pin. The I/O VCC- and I/O VL-ports are designed to track two different power supply rails, VCC and VL respectively. Both the VCC and the VL supply rails are configurable from 0.9 V to 4.5 V. This allows a logic signal on the VL side to be translated to either a higher or a lower logic signal voltage on the VCC side, and vice-versa. The NLSX5012 offers the feature that the values of the VCC and VL supplies are independent. Design flexibility is maximized because VL can be set to a value either greater than or less than the VCC supply. In contrast, the majority of competitive auto sense translators have a restriction that the value of the VL supply must be equal to less than (VCC - 0.4) V. The NLSX5012 has high output current capability, which allows the translator to drive high capacitive loads such as most high frequency EMI filters. Another feature of the NLSX5012 is that each I/O_VLn and I/O_VCCn channel can function as either an input or an output. An Output Enable (EN) input is available to reduce the power consumption. The EN pin can be used to disable both I/O ports by putting them in 3-state which significantly reduces the supply current from both VCC and VL. The EN signal is referenced to the VL supply. http://onsemi.com MARKING DIAGRAMS UDFN8 MU SUFFIX CASE 517AJ 8 1 VA = Specific Device Code M = Date Code G = Pb−Free Package 8 SO−8 D SUFFIX CASE 751 8 1 A L Y W G • • • • • • • • 8 Device Important Information • ESD Protection for All Pins: Package Shipping† NLSX5012MUTAG UDFN8 3000/Tape & Reel (Pb−Free) NLSX5012DR2G SO−8 2500/Tape & Reel (Pb−Free) NLSX5012DMR2G Micro8 4000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. HBM (Human Body Model) > 8000 V April, 2011 − Rev. 2 = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION • Mobile Phones, PDAs, Other Portable Devices © Semiconductor Components Industries, LLC, 2011 5012 AYWG G 1 A Y W G Typical Applications ♦ 1 Micro8 DM SUFFIX CASE 846A 1 − VL may be greater than, equal to, or less than VCC High 100 pF Capacitive Drive Capability High−Speed with 140 Mb/s Guaranteed Date Rate for VCC, VL > 1.8 V Low Bit−to−Bit Skew Overvoltage Tolerant Enable and I/O Pins Non−preferential Power−Up Sequencing Power−Off Protection Small packaging: UDFN8, SO−8, Micro8 These are Pb−Free Devices SX5012 ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Features • Wide VCC, VL Operating Range: 0.9 V to 4.5 V • VL and VCC are independent AE M G 1 Publication Order Number: NLSX5012/D NLSX5012 P One−Shot VL +1.8V R1 +3.6V VL +1.8 V System I/O1 I/On GND OE NLSX5012 I/O VL1 VCC N One−Shot VCC +3.6 V System I/O VCC1 I/O1 I/O VLn I/O VCCn EN GND I/On I/O VL I/O VCC P One−Shot R2 GND N One−Shot Figure 1. Typical Application Circuit 2.5 V VL mC NLSX5012 VCC Figure 2. Simplified Functional Diagram (1 I/O Line) 3.0 V 2.5 V Peripheral mC 1.8 V VL NLSX5012 VCC Peripheral TX I/O VL1 I/O VCC1 RX TX I/O VL1 I/O VCC1 RX RX I/O VL2 I/O VCC2 TX RX I/O VL2 I/O VCC2 TX ANO EN GND ANO Figure 3. Application Example for VL < VCC EN GND Figure 4. Application Example for VL > VCC http://onsemi.com 2 NLSX5012 VL EN VCC GND I/O VL1 I/O VCC1 I/O VL2 I/O VCC2 Figure 5. Logic Diagram VL 1 8 VCC I/O VL1 2 7 I/O VCC1 I/O VL2 GND 3 6 4 5 I/O VCC2 VL 1 8 VCC I/O VL1 2 7 I/O VCC1 I/O VL2 3 6 GND 4 EN 5 I/O VCC2 EN VL 1 8 VCC I/O VL1 2 7 I/O VCC1 I/O VL2 3 6 I/O VCC2 GND 4 5 EN Micro8 (Top View) SOIC−8 (Top View) UDFN8 (Top View) Figure 6. Pin Assignments PIN ASSIGNMENT Pins FUNCTION TABLE Description EN Operating Mode VCC VCC Input Voltage L Hi−Z VL VL Input Voltage H I/O Buses Connected GND Ground EN Output Enable I/O VCCn I/O Port, Referenced to VCC I/O VLn I/O Port, Referenced to VL http://onsemi.com 3 NLSX5012 MAXIMUM RATINGS Symbol Parameter Value Condition Unit VCC High−side DC Supply Voltage −0.5 to +5.5 V VL Low−side DC Supply Voltage −0.5 to +5.5 V I/O VCC VCC−Referenced DC Input/Output Voltage −0.5 to +5.5 V I/O VL VL−Referenced DC Input/Output Voltage −0.5 to +5.5 V VI Enable Control Pin DC Input Voltage −0.5 to +5.5 V IIK DC Input Diode Current −50 VI < GND mA IOK DC Output Diode Current −50 VO < GND mA ICC DC Supply Current Through VCC $100 mA IL DC Supply Current Through VL $100 mA IGND DC Ground Current Through Ground Pin $100 mA TSTG Storage Temperature −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC High−side Positive DC Supply Voltage 0.9 4.5 V VL Low−side Positive DC Supply Voltage 0.9 4.5 V GND 4.5 V GND GND 4.5 4.5 V −55 +125 °C 0 10 ns VI Enable Control Pin Voltage VIO Bus Input/Output Voltage TA Operating Temperature Range Dt/DV I/O VCC I/O VL Input Transition Rise or Rate VI, VIO from 30% to 70% of VCC; VCC = 3.3 V $ 0.3 V http://onsemi.com 4 NLSX5012 DC ELECTRICAL CHARACTERISTICS −405C to +855C Min Max Unit VL (V) (Note 3) I/O VCC Input HIGH Voltage 0.9 – 4.5 0.9 – 4.5 2/3 * VCC − − 2/3 * VCC − V VILC I/O VCC Input LOW Voltage 0.9 – 4.5 0.9 – 4.5 − − 1/3 * VCC − 1/3 * VCC V VIHL I/O VL Input HIGH Voltage 0.9 – 4.5 0.9 – 4.5 2/3 * VL − − 2/3 * VL − V VILL I/O VL Input LOW Voltage 0.9 – 4.5 0.9 – 4.5 − − 1/3 * VL − 1/3 * VL V VIH Control Pin Input HIGH Voltage TA = +25°C 0.9 – 4.5 0.9 – 4.5 2/3 * VL − − 2/3 * VL − V VIL Control Pin Input LOW Voltage TA = +25°C 0.9 – 4.5 0.9 – 4.5 − − 1/3 * VL − 1/3 * VL V VOHC I/O VCC Output HIGH Voltage I/O VCC source current = 20 mA 0.9 – 4.5 0.9 – 4.5 0.9 * VCC − − 0.9 * VCC − V VOLC I/O VCC Output LOW Voltage I/O VCC sink current = 20 mA 0.9 – 4.5 0.9 – 4.5 − − 0.2 − 0.2 V VOHL I/O VL Output HIGH Voltage I/O VL source current = 20 mA 0.9 – 4.5 0.9 – 4.5 0.9 * VL − − 0.9 * VL − V VOLL I/O VL Output LOW Voltage I/O VL sink current = 20 mA 0.9 – 4.5 0.9 – 4.5 − − 0.2 − 0.2 V IQVCC VCC Supply Current EN = VL, IO = 0 A, (I/O VCC = 0 V or VCC, I/O VL = float) or (I/O VCC = float, I/O VL = 0 V or VL) 0.9 – 4.5 0.9 – 4.5 − − 1 − 2.5 mA 0.9 – 4.5 0.9 – 4.5 − − 1 − 2.5 mA TA = +25°C, EN = 0 V (I/O VCC = 0 V or VCC, I/O VL = float) or (I/O VCC = float, I/O VL = 0 V or VL) 0.9 – 4.5 0.9 – 4.5 − − 0.5 − 1.5 mA 0.9 – 4.5 0.9 – 4.5 − − 0.5 − 1.5 mA TA = +25°C, EN = 0V 0.9 – 4.5 0.9 – 4.5 − − ±1 − ±1.5 mA Parameter VIHC IQVL ITS−VCC VL Supply Current VCC Tristate Output Mode Supply Current ITS−VL VL Tristate Output Mode Supply Current IOZ I/O Tristate Output Mode Leakage Current II Control Pin Input Current IOFF 1. 2. 3. 4. Max VCC (V) (Note 2) Symbol Power Off Leakage Current Test Conditions (Note 1) −555C to +1255C Typ (Note 4) Min TA = +25°C 0.9 – 4.5 0.9 – 4.5 − − ±1 − ±1 mA I/O VCC = 0 to 4.5V, 0 0 − − 1 − 1.5 mA I/O VL = 0 to 4.5 V 0.9 – 4.5 0 − − 1 − 1.5 0 0.9 – 4.5 − − 1 − 1.5 Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. http://onsemi.com 5 NLSX5012 TIMING CHARACTERISTICS −555C to +1255C Symbol Parameter Test Conditions (Note 5) VCC (V) (Note 6) VL (V) (Note 7) Min Typ (Note 8) Max Unit 0.9 – 4.5 0.9 – 4.5 − − 8.5 nS 1.8 – 4.5 1.8 – 4.5 − − 3.5 0.9 – 4.5 0.9 – 4.5 − − 8.5 1.8 – 4.5 1.8 – 4.5 − − 3.5 0.9 – 4.5 0.9 – 4.5 − − 8.5 1.8 – 4.5 1.8 – 4.5 − − 3.5 0.9 – 4.5 0.9 – 4.5 − − 8.5 1.8 – 4.5 1.8 – 4.5 − − 3.5 tR−VCC I/O VCC Rise Time CIOVCC = 15 pF tF−VCC I/O VCC Fall Time CIOVCC = 15 pF tR−VL tF−VL ZOVCC ZOVL I/O VL Rise Time I/O VL Fall Time CIOVL = 15 pF CIOVL = 15 pF nS nS nS I/O VCC One−Shot Output Impedance (Note 9) 0.9 1.8 4.5 0.9 – 4.5 − − − 37 20 6.0 − − − W I/O VL One−Shot Output Impedance (Note 9) 0.9 1.8 4.5 0.9 – 4.5 − − − 37 20 6.0 − − − W CIOVCC = 15 pF 0.9 – 4.5 0.9 – 4.5 − − 35 nS 1.8 – 4.5 1.8 – 4.5 − − 10 0.9 – 4.5 0.9 – 4.5 − − 35 1.8 – 4.5 1.8 – 4.5 − − 10 1.0 – 4.5 1.0 – 4.5 − − 37 1.8 – 4.5 1.8 – 4.5 − − 11 1.2 – 4.5 1.2 – 4.5 − − 40 1.8 – 4.5 1.8 – 4.5 − − 13 0.9 – 4.5 0.9 – 4.5 − − 35 1.8 – 4.5 1.8 – 4.5 − − 10 0.9 – 4.5 0.9 – 4.5 − − 35 1.8 – 4.5 1.8 – 4.5 − − 10 1.0 – 4.5 1.0 – 4.5 − − 37 1.8 – 4.5 1.8 – 4.5 − − 11 1.2 – 4.5 1.2 – 4.5 − − 40 1.8 – 4.5 1.8 – 4.5 − − 13 tPD_VL−VCC Propagation Delay (Driving I/O VCC) CIOVCC = 30 pF CIOVCC = 50 pF CIOVCC = 100 pF tPD_VCC−VL Propagation Delay (Driving I/O VL) CIOVL = 15 pF CIOVL = 30 pF CIOVL = 50 pF CIOVL = 100 pF nS tSK Channel−to−Channel Skew CIOVCC = 15 pF, CIOVL = 15 pF (Note 9) 0.9 – 4.5 0.9 – 4.5 − − 0.15 nS IIN_PEAK Input Driver Maximum Peak Current EN = VL; I/O_VCC = 1 MHz Square Wave, Amplitude = VCC, or I/O_VL = 1 MHz Square Wave, Amplitude = VL (Note 9) 0.9 – 4.5 0.9 – 4.5 − − 5.0 mA 5. 6. 7. 8. Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. 9. Guaranteed by design. http://onsemi.com 6 NLSX5012 TIMING CHARACTERISTICS (continued) −555C to +1255C Symbol tEN−VCC tEN−VL I/O_VCC Output Enable Time I/O_VL Output Enable Time tDIS−VCC I/O_VCC Output Disable Time tDIS−VL MDR Test Conditions (Note 10) VCC (V) (Note 11) VL (V) (Note 12) Min Typ (Note 13) Max Unit tPZH CIOVCC = 15 pF, I/O_VL = VL 0.9 – 4.5 0.9 – 4.5 − − 160 nS tPZL CIOVCC = 15 pF, I/O_VL = 0 V 0.9 – 4.5 0.9 – 4.5 − − 130 tPZH CIOVL = 15 pF, I/O_VCC = VCC 0.9 – 4.5 0.9 – 4.5 − − 160 tPZL CIOVL = 15 pF, I/O_VCC = 0 V 0.9 – 4.5 0.9 – 4.5 − − 130 tPHZ CIOVCC = 15 pF, I/O_VL = VL 0.9 – 4.5 0.9 – 4.5 − − 210 tPLZ CIOVCC = 15 pF, I/O_VL = 0 V 0.9 – 4.5 0.9 – 4.5 − − 175 tPHZ CIOVL = 15 pF, I/O_VCC = VCC 0.9 – 4.5 0.9 – 4.5 − − 210 tPLZ CIOVL = 15 pF, I/O_VCC = 0 V 0.9 – 4.5 0.9 – 4.5 − − 175 CIO = 15 pF 0.9 – 4.5 0.9 – 4.5 50 − − 1.8 – 4.5 1.8 – 4.5 140 − − 0.9 – 4.5 0.9 – 4.5 40 − − 1.8 – 4.5 1.8 – 4.5 120 − − 1.0 – 4.5 1.0 – 4.5 30 − − 1.8 – 4.5 1.8 – 4.5 100 − − 1.2 – 4.5 1.2 – 4.5 20 − − 1.8 – 4.5 1.8 – 4.5 60 − − Parameter I/O_VL Output Disable Time Maximum Data Rate CIO = 30 pF CIO = 50 pF CIO = 100 pF nS nS nS mbps 10. Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified. 11. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. 12. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. 13. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. http://onsemi.com 7 NLSX5012 DYNAMIC POWER CONSUMPTION (TA = +25°C) Symbol Parameter CPD_VL VL = Input port, VCC = Output Port VCC = Input port, VL = Output Port CPD_VCC VL = Input port, VCC = Output Port VCC = Input port, VL = Output Port Test Conditions CLoad = 0, f = 1 MHz, EN = VL (outputs enabled) CLoad = 0, f = 1 MHz, EN = VL (outputs enabled) CLoad = 0, f = 1 MHz, EN = VL (outputs enabled) CLoad = 0, f = 1 MHz, EN = VL (outputs enabled) VCC (V) (Note 14) VL (V) (Note 15) Typ (Note 16) Unit 0.9 4.5 39 pF 1.5 1.8 20 1.8 1.5 17 1.8 1.8 14 1.8 2.8 13 2.5 2.5 14 2.8 1.8 13 4.5 0.9 19 0.9 4.5 37 1.5 1.8 30 1.8 1.5 29 1.8 1.8 29 1.8 2.8 29 2.5 2.5 30 2.8 1.8 29 4.5 0.9 19 0.9 4.5 29 1.5 1.8 29 1.8 1.5 29 1.8 1.8 29 1.8 2.8 29 2.5 2.5 30 2.8 1.8 29 4.5 0.9 35 0.9 4.5 21 1.5 1.8 18 1.8 1.5 18 1.8 1.8 14 1.8 2.8 13 2.5 2.5 14 2.8 1.8 13 4.5 0.9 30 pF pF pF 14. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. 15. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. 16. Typical values are at TA = +25°C. 17. CPD VL and CPD VCC are defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated for the VL and VCC power supplies, respectively. ICC = ICC (dynamic) + ICC (static) ≈ ICC(operating) ≈ CPD x VCC x fIN x NSW where ICC = ICC_VCC + ICC VL and NSW = total number of outputs switching. http://onsemi.com 8 NLSX5012 STATIC POWER CONSUMPTION (TA = +25°C) Symbol Parameter CPD_VL VL = Input port, VCC = Output Port VCC = Input port, VL = Output Port CPD_VCC VL = Input port, VCC = Output Port VCC = Input port, VL = Output Port Test Conditions CLoad = 0, f = 1 MHz, EN = GND (outputs disabled) CLoad = 0, f = 1 MHz, EN = GND (outputs disabled) CLoad = 0, f = 1 MHz, EN = GND (outputs disabled) CLoad = 0, f = 1 MHz, EN = GND (outputs disabled) VCC (V) (Note 18) VL (V) (Note 19) Typ (Note 20) Unit 0.9 4.5 0.01 pF 1.5 1.8 0.01 1.8 1.5 0.01 1.8 1.8 0.01 1.8 2.8 0.01 2.5 2.5 0.01 2.8 1.8 0.01 4.5 0.9 0.01 0.9 4.5 0.01 1.5 1.8 0.01 1.8 1.5 0.01 1.8 1.8 0.01 1.8 2.8 0.01 2.5 2.5 0.01 2.8 1.8 0.01 4.5 0.9 0.01 0.9 4.5 0.01 1.5 1.8 0.01 1.8 1.5 0.01 1.8 1.8 0.01 1.8 2.8 0.01 2.5 2.5 0.01 2.8 1.8 0.01 4.5 0.9 0.01 0.9 4.5 0.01 1.5 1.8 0.01 1.8 1.5 0.01 1.8 1.8 0.01 1.8 2.8 0.01 2.5 2.5 0.01 2.8 1.8 0.01 4.5 0.9 0.01 18. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. 19. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. 20. Typical values are at TA = +25°C http://onsemi.com 9 pF pF pF NLSX5012 NLSX5012 VL VCC NLSX5012 VL EN I/O VL Source VCC EN I/O VL I/O VCC I/O VCC CIOVL CIOVCC Source tRISE/FALL v 3 ns I/O VL 90% 50% 10% I/O VCC tRISE/FALL v 3 ns 90% 50% 10% tPD_VL−VCC I/O VCC tPD_VCC−VL I/O VL tPD_VL−VCC 90% 50% 10% tPD_VCC−VL 90% 50% 10% tF−VCC tR−VCC tF−VL Figure 7. Driving I/O VL Test Circuit and Timing tR−VL Figure 8. Driving I/O VCC Test Circuit and Timing VCC PULSE GENERATOR 2xVCC OPEN R1 DUT RT CL Test RL Switch tPZH, tPHZ Open tPZL, tPLZ 2 x VCC CL = 15 pF or equivalent (Includes jig and probe capacitance) RL = R1 = 50 kW or equivalent RT = ZOUT of pulse generator (typically 50 W) Figure 9. Test Circuit for Enable/Disable Time Measurement tR tF Input tPLH Output 90% 50% 10% tR EN VCC 90% 50% 10% tPHL GND VL 50% tPZL Output 50% tPZH tF Output 50% GND tPLZ tPHZ HIGH IMPEDANCE 10% VOL 90% VOH Figure 10. Timing Definitions for Propagation Delays and Enable/Disable Measurement http://onsemi.com 10 HIGH IMPEDANCE NLSX5012 IMPORTANT APPLICATIONS INFORMATION Level Translator Architecture VL pins to a high impedance state. Normal translation operation occurs when the EN pin is equal to a logic high signal. The EN pin is referenced to the VL supply and has Over−Voltage Tolerant (OVT) protection. The NLSX5012 auto−sense translator provides bi−directional logic voltage level shifting to transfer data in multiple supply voltage systems. These level translators have two supply voltages, VL and VCC, which set the logic levels on the input and output sides of the translator. When used to transfer data from the I/O VL to the I/O VCC ports, input signals referenced to the VL supply are translated to output signals with a logic level matched to VCC. In a similar manner, the I/O VCC to I/O VL translation shifts input signals with a logic level compatible to VCC to an output signal matched to VL. The NLSX5012 translator consists of bi−directional channels that independently determine the direction of the data flow without requiring a directional pin. One−shot circuits are used to detect the rising or falling input signals. In addition, the one−shots decrease the rise and fall times of the output signal for high−to−low and low−to−high transitions. Uni−Directional versus Bi−Directional Translation The NLSX5012 translator can function as a non−inverting uni−directional translator. One advantage of using the translator as a uni−directional device is that each I/O pin can be configured as either an input or output. The configurable input or output feature is especially useful in applications such as SPI that use multiple uni−directional I/O lines to send data to and from a device. The flexible I/O port of the auto sense translator simplifies the trace connections on the PCB. Power Supply Guidelines The values of the VL and VCC supplies can be set to anywhere between 0.9 and 4.5 V. Design flexibility is maximized because VL may be either greater than or less than the VCC supply. In contrast, the majority of the competitive auto sense translators has a restriction that the value of the VL supply must be equal to less than (VCC − 0.4) V. The sequencing of the power supplies will not damage the device during power−up operation. In addition, the I/O VCC and I/O VL pins are in the high impedance state if either supply voltage is equal to 0 V. For optimal performance, 0.01 to 0.1 mF decoupling capacitors should be used on the VL and VCC power supply pins. Ceramic capacitors are a good design choice to filter and bypass any noise signals on the voltage lines to the ground plane of the PCB. The noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the PCB connection traces. The NLSX5012 translators have a power down feature that provides design flexibility. The output ports are disabled when either power supply is off (VL or VCC = 0 V). This feature causes all of the I/O pins to be in the power saving high impedance state. Input Driver Requirements Auto−sense translators such as the NLSX5012 have a wide bandwidth, but a relatively small DC output current rating. The high bandwidth of the bi−directional I/O circuit is used to quickly transform from an input to an output driver and vice versa. The I/O ports have a modest DC current output specification so that the output driver can be over driven when data is sent in the opposite direction. For proper operation, the input driver to the auto−sense translator should be capable of driving 2 mA of peak output current. The bi−directional configuration of the translator results in both input stages being active for a very short time period. Although the peak current from the input signal circuit is relatively large, the average current is small and consistent with a standard CMOS input stage. Enable Input (EN) The NLSX5012 translator has an Enable pin (EN) that provides tri−state operation at the I/O pins. Driving the Enable pin to a low logic level minimizes the power consumption of the device and drives the I/O VCC and I/O http://onsemi.com 11 NLSX5012 PACKAGE DIMENSIONS UDFN8 1.8 x 1.2, 0.4P CASE 517AJ−01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. 4. MOLD FLASH ALLOWED ON TERMINALS ALONG EDGE OF PACKAGE. FLASH MAY NOT EXCEED 0.03 ONTO BOTTOM SURFACE OF TERMINALS. 5. DETAIL A SHOWS OPTIONAL CONSTRUCTION FOR TERMINALS. A B D 0.10 C PIN ONE REFERENCE ÏÏ 0.10 C L1 E DETAIL A NOTE 5 TOP VIEW (A3) 0.05 C DIM A A1 A3 b b2 D E e L L1 L2 A 0.05 C SIDE VIEW e/2 (b2) A1 e 1 4 8 5 C SEATING PLANE DETAIL A 8X L (L2) BOTTOM VIEW MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.15 0.25 0.30 REF 1.80 BSC 1.20 BSC 0.40 BSC 0.45 0.55 0.00 0.03 0.40 REF MOUNTING FOOTPRINT SOLDERMASK DEFINED 8X b 0.10 M C A B 0.05 M C 8X 0.66 7X 0.22 NOTE 3 1.50 1 0.32 0.40 PITCH DIMENSIONS: MILLIMETERS http://onsemi.com 12 NLSX5012 PACKAGE DIMENSIONS SO−8 CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 13 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 _ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 NLSX5012 PACKAGE DIMENSIONS Micro8t CASE 846A−02 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A-01 OBSOLETE, NEW STANDARD 846A-02. MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX A −− −− 1.10 −− −− 0.043 A1 0.05 0.08 0.15 0.002 0.003 0.006 b 0.25 0.33 0.40 0.010 0.013 0.016 c 0.13 0.18 0.23 0.005 0.007 0.009 D 2.90 3.00 3.10 0.114 0.118 0.122 E 2.90 3.00 3.10 0.114 0.118 0.122 e 0.65 BSC 0.026 BSC L 0.40 0.55 0.70 0.016 0.021 0.028 HE 4.75 4.90 5.05 0.187 0.193 0.199 D HE PIN 1 ID E e b 8 PL 0.08 (0.003) T B M S A S SEATING −T− PLANE 0.038 (0.0015) A A1 L c SOLDERING FOOTPRINT* 8X 1.04 0.041 0.38 0.015 3.20 0.126 6X 8X 4.24 0.167 0.65 0.0256 5.28 0.208 SCALE 8:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 14 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative NLSX5012/D