NLSX4373 2-Bit 20 Mb/s Dual-Supply Level Translator The NLSX4373 is a 2−bit configurable dual−supply bidirectional auto sensing translator that does not require a directional control pin. The VCC I/O and VL I/O ports are designed to track two different power supply rails, VCC and VL respectively. The VCC supply rail is configurable from 1.5 V to 5.5 V while VL supply rail is configurable to 1.5 V to 5.5 V. This allows voltage logic signals on the VL side to be translated into lower, higher or equal value voltage logic signals on the VCC side, and vice−versa. The NLSX4373 translator has open−drain outputs with integrated 10 kW pullup resistors on the I/O lines. The integrated pullup resistors are used to pullup the I/O lines to either VL or VCC. The NLSX4373 is an excellent match for open−drain applications such as the I2C communication bus. http://onsemi.com MARKING DIAGRAMS UDFN8 MU SUFFIX CASE 517AJ 8 1 VF = Specific Device Code M = Date Code G = Pb−Free Package 8 Features • VL can be Less than, Greater than or Equal to VCC • Wide VCC Operating Range: 1.5 V to 5.5 V • • • • • • • VFM G SO−8 D SUFFIX CASE 751 8 Wide VL Operating Range: 1.5 V to 5.5 V High−Speed with 20 Mb/s Guaranteed Date Rate Low Bit−to−Bit Skew Enable Input and I/O Lines have Overvoltage Tolerant (OVT) to 5.5 V Nonpreferential Powerup Sequencing Integrated 10 kW Pullup Resistors Small packaging: UDFN8, SO−8, Micro8 This is a Pb−Free Device Typical Applications 1 A L Y W G Important Information 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package 8 Micro8 DM SUFFIX CASE 846A 1 4373 AYW G G 1 A Y W G • I2C, SMBus, PMBus • Low Voltage ASIC Level Translation • Mobile Phones, PDAs, Cameras SX4373 ALYW G G = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION • ESD Protection for All Pins Device − Human Body Model (HBM) > 7000 V Package Shipping† NLSX4373MUTAG UDFN8 3000/Tape & Reel (Pb−Free) NLSX4373DR2G SO−8 2500/Tape & Reel (Pb−Free) NLSX4373DMR2G Micro8 4000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2009 December, 2009 − Rev. 3 1 Publication Order Number: NLSX4373/D NLSX4373 LOGIC DIAGRAM VL EN VCC GND I/O VL1 I/O VCC1 I/O VL2 I/O VCC2 PIN ASSIGNMENTS VL 1 8 VCC I/O VL1 2 7 I/O VCC1 I/O VL2 3 6 I/O VCC2 GND 4 5 EN VL 1 8 VCC I/O VL1 2 7 I/O VCC1 I/O VL2 3 6 GND 4 UDFN8 (Top View) 5 EN 1 8 VCC I/O VL1 2 7 I/O VCC1 I/O VL2 3 6 I/O VCC2 GND 4 5 EN Micro8 (Top View) SOIC−8 (Top View) PIN ASSIGNMENT Pins I/O VCC2 VL FUNCTION TABLE Description EN Operating Mode VCC VCC Input Voltage L Hi−Z VL VL Input Voltage H I/O Buses Connected GND Ground EN Output Enable I/O VCCn VCC I/O Port, Referenced to VCC I/O VLn VL I/O Port, Referenced to VL http://onsemi.com 2 NLSX4373 MAXIMUM RATINGS Symbol Parameter Value Condition Unit VCC High−side DC Supply Voltage −0.3 to +7.0 V VL High−side DC Supply Voltage −0.3 to +7.0 V I/O VCC VCC−Referenced DC Input/Output Voltage −0.3 to (VCC + 0.3) V I/O VL VL−Referenced DC Input/Output Voltage −0.3 to (VL + 0.3) V VEN Enable Control Pin DC Input Voltage −0.3 to +7.0 V II/O_SC Short−Circuit Duration (I/O VL and I/O VCC to GND) TSTG Storage Temperature 40 Continuous mA −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC High−side Positive DC Supply Voltage 1.5 5.5 V VL High−side Positive DC Supply Voltage 1.5 5.5 V VEN Enable Control Pin Voltage GND 5.5 V VIO Enable Control Pin Voltage GND 5.5 V TA Operating Temperature Range −40 +85 °C VL VCC PU1 One−Shot Block One−Shot Block PU2 Gate Bias RPullup 10 kW I/O VL RPullup 10 kW I/O VCC N Figure 1. Block Diagram (1 I/O Line) http://onsemi.com 3 NLSX4373 DC ELECTRICAL CHARACTERISTICS (VCC = 1.5 V to 5.5 V and VL = 1.5 V to 5.5 V, unless otherwise specified) −405C to +855C Symbol Parameter Test Conditions Min Typ (Notes 1, 2) Max Unit VCC − 0.4 − − V VIHC I/O VCC Input HIGH Voltage VILC I/O VCC Input LOW Voltage − − 0.15 V VIHL I/O VL Input HIGH Voltage VL − 0.2 − − V VILL I/O VL Input LOW Voltage − − 0.15 V VIH Control Pin Input HIGH Voltage VL − 0.2 − − V VIL Control Pin Input LOW Voltage − − 0.15 V VOHC I/O VCC Output HIGH Voltage I/O VCC Source Current = 20 mA 2/3 * VCC − − V VOLC I/O VCC Output LOW Voltage I/O VCC Sink Current = 20 mA − − 1/3 * VCC V VOHL I/O VL Output HIGH Voltage I/O VL Source Current = 20 mA 2/3 * VL − − V VOLL I/O VL Output LOW Voltage I/O VL Sink Current = 20 mA − − 1/3 * VL V IQVCC VCC Supply Current I/O VCC and I/O VL Unconnected, VEN = VL − 0.5 2.0 mA VL Supply Current I/O VCC and I/O VL Unconnected, VEN = VL − 0.3 1.5 mA VCC Tristate Output Mode Supply Current I/O VCC and I/O VL Unconnected, VEN = GND − 0.1 1.0 mA VL Tristate Output Mode Supply Current I/O VCC and I/O VL Unconnected, VEN = GND − 0.1 1.0 mA IQVL ITS−VCC ITS−VL IOZ I/O Tristate Output Mode Leakage Current TA = +25°C − 0.1 1.0 mA RPU Pullup Resistor I/O VL and VCC TA = +25°C − 10 − kW 1. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. 2. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. http://onsemi.com 4 NLSX4373 TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS (I/O test circuit of Figures 2 and 3, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW) −405C to +855C (Notes 3 and 4) Symbol Parameter Test Conditions Min Typ Max Unit VL = 1.5 V, VCC = 5.5 V tRVCC I/O VCC Risetime 15 ns tFVCC I/O VCC Falltime 20 ns tRVL I/O VL Risetime 30 ns tFVL I/O VL Falltime 10 ns tPDVL−VCC Propagation Delay (Driving I/O VL) 20 ns tPDVCC−VL Propagation Delay (Driving I/O VCC) 20 ns Part−to−Part Skew 5 nS tPPSKEW Maximum Data Rate 20 Mb/s VL = 1.8 V, VCC = 2.8 V tRVCC I/O VCC Risetime 15 ns tFVCC I/O VCC Falltime 15 ns tRVL I/O VL Risetime 25 ns tFVL I/O VL Falltime 10 ns tPDVL−VCC Propagation Delay (Driving I/O VL) 15 ns tPDVCC−VL Propagation Delay (Driving I/O VCC) 15 ns Part−to−Part Skew 5 nS tPPSKEW Maximum Data Rate 20 Mb/s VL = 2.5 V, VCC = 3.6 V tRVCC I/O VCC Risetime 15 ns tFVCC I/O VCC Falltime 10 ns tRVL I/O VL Risetime 15 ns tFVL I/O VL Falltime 10 ns tPDVL−VCC Propagation Delay (Driving I/O VL) 15 ns tPDVCC−VL Propagation Delay (Driving I/O VCC) 15 ns Part−to−Part Skew 5 nS tPPSKEW Maximum Data Rate 20 Mb/s VL = 2.8 V, VCC = 1.8 V tRVCC I/O VCC Risetime 25 ns tFVCC I/O VCC Falltime 10 ns tRVL I/O VL Risetime 20 ns tFVL I/O VL Falltime 15 ns tPDVL−VCC Propagation Delay (Driving I/O VL) 15 ns tPDVCC−VL Propagation Delay (Driving I/O VCC) 15 ns Part−to−Part Skew 5 nS tPPSKEW Maximum Data Rate 20 3. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25°C. 4. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. http://onsemi.com 5 Mb/s NLSX4373 TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS (I/O test circuit of Figures 2 and 3, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW) −405C to +855C (Notes 3 and 4) Symbol Parameter Test Conditions Min Typ Max Unit VL = 3.6 V, VCC = 2.5 V tRVCC I/O VCC Risetime 15 ns tFVCC I/O VCC Falltime 10 ns tRVL I/O VL Risetime 15 ns tFVL I/O VL Falltime 15 ns tPDVL−VCC Propagation Delay (Driving I/O VL) 15 ns tPDVCC−VL Propagation Delay (Driving I/O VCC) 15 ns Part−to−Part Skew 5 nS tPPSKEW Maximum Data Rate 20 Mb/s VL = 5.5 V, VCC = 1.5 V tRVCC I/O VCC Risetime 30 ns tFVCC I/O VCC Falltime 10 ns tRVL I/O VL Risetime 15 ns tFVL I/O VL Falltime 20 ns tPDVL−VCC Propagation Delay (Driving I/O VL) 20 ns tPDVCC−VL Propagation Delay (Driving I/O VCC) 20 ns Part−to−Part Skew 5 nS tPPSKEW Maximum Data Rate 20 Mb/s 3. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25°C. 4. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. TIMING CHARACTERISTICS − OPEN DRAIN DRIVING CONFIGURATIONS (I/O test circuit of Figures 4 and 5, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW) −405C to +855C (Notes 5 and 6) Symbol Parameter Test Conditions Min Typ Max Unit +1.5 v VL v VCC v +5.5 V tRVCC I/O VCC Risetime 400 ns tFVCC I/O VCC Falltime 50 ns tRVL I/O VL Risetime 400 ns tFVL I/O VL Falltime 60 ns ns tPDVL−VCC Propagation Delay (Driving I/O VL) 1000 tPDVCC−VL Propagation Delay (Driving I/O VCC) 1000 ns 50 nS tPPSKEW MDR Part−to−Part Skew Maximum Data Rate 2 5. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25°C. 6. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. http://onsemi.com 6 Mb/s NLSX4373 TEST SETUPS NLSX4373 VL VCC NLSX4373 VL EN Source EN I/O VL I/O VCC I/O VL I/O VCC CLOAD CLOAD RLOAD NLSX4373 Figure 3. Rail−to−Rail Driving I/O VCC I/O VCC I/O VL CLOAD I/O VCC VCC CLOAD RLOAD Figure 4. Open−Drain Driving I/O VL Figure 5. Open−Drain Driving I/O VCC tRISE/FALL v 3 ns tPD_VL−VCC I/O VCC VCC EN RLOAD I/O VL NLSX4373 VL VCC EN 90% 50% 10% Source RLOAD Figure 2. Rail−to−Rail Driving I/O VL VL VCC I/O VCC tRISE/FALL v 3 ns 90% 50% 10% tPD_VCC−VL I/O VL tPD_VL−VCC 90% 50% 10% tPD_VCC−VL 90% 50% 10% tF−VCC tR−VCC tF−VL Figure 6. Definition of Timing Specification Parameters http://onsemi.com 7 tR−VL NLSX4373 VCC PULSE GENERATOR 2xVCC OPEN R1 DUT RT CL Test RL Switch tPZH, tPHZ Open tPZL, tPLZ 2 x VCC CL = 15 pF or equivalent (Includes jig and probe capacitance) RL = R1 = 50 kW or equivalent RT = ZOUT of pulse generator (typically 50 W) Figure 7. Test Circuit for Enable/Disable Time Measurement tR tF Input tPLH Output 90% 50% 10% tR EN VCC 90% 50% 10% tPHL GND VL 50% tPZL Output 50% tPZH tF Output 50% GND tPLZ tPHZ HIGH IMPEDANCE 10% VOL 90% VOH Figure 8. Timing Definitions for Propagation Delays and Enable/Disable Measurement http://onsemi.com 8 HIGH IMPEDANCE NLSX4373 APPLICATIONS INFORMATION Level Translator Architecture parameters listed in the data sheet assume that the output impedance of the drivers connected to the translator is less than 50 kW. The NLSX4373 auto sense translator provides bi−directional voltage level shifting to transfer data in multiple supply voltage systems. This device has two supply voltages, VL and VCC, which set the logic levels on the input and output sides of the translator. When used to transfer data from the VL to the VCC ports, input signals referenced to the VL supply are translated to output signals with a logic level matched to VCC. In a similar manner, the VCC to VL translation shifts input signals with a logic level compatible to VCC to an output signal matched to VL. The NLSX4373 consists of two bi−directional channels that independently determine the direction of the data flow without requiring a directional pin. The one−shot circuits are used to detect the rising or falling input signals. In addition, the one shots decrease the rise and fall time of the output signal for high−to−low and low−to−high transitions. Each input/output channel has an internal 10 kW pull. The magnitude of the pullup resistors can be reduced by connecting external resistors in parallel to the internal 10 kW resistors. Enable Input (EN) The NLSX4373 has an Enable pin (EN) that provides tri−state operation at the I/O pins. Driving the Enable pin to a low logic level minimizes the power consumption of the device and drives the I/O VCC and I/O VL pins to a high impedance state. Normal translation operation occurs when the EN pin is equal to a logic high signal. The EN pin is referenced to the VL supply and has Overvoltage Tolerant (OVT) protection. Power Supply Guidelines During normal operation, supply voltage VL can be greater than, less than or equal to VCC. The sequencing of the power supplies will not damage the device during the power up operation. For optimal performance, 0.01 mF to 0.1 mF decoupling capacitors should be used on the VL and VCC power supply pins. Ceramic capacitors are a good design choice to filter and bypass any noise signals on the voltage lines to the ground plane of the PCB. The noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the PCB connection traces. Input Driver Requirements The rise (tR) and fall (tF) timing parameters of the open drain outputs depend on the magnitude of the pull−up resistors. In addition, the propagation times (tPD), skew (tPSKEW) and maximum data rate depend on the impedance of the device that is connected to the translator. The timing http://onsemi.com 9 NLSX4373 PACKAGE DIMENSIONS UDFN8 1.8 x 1.2, 0.4P CASE 517AJ−01 ISSUE O PIN ONE REFERENCE ÏÏ ÏÏ 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. 4. MOLD FLASH ALLOWED ON TERMINALS ALONG EDGE OF PACKAGE. FLASH MAY NOT EXCEED 0.03 ONTO BOTTOM SURFACE OF TERMINALS. 5. DETAIL A SHOWS OPTIONAL CONSTRUCTION FOR TERMINALS. A B D 0.10 C L1 E DETAIL A NOTE 5 TOP VIEW (A3) 0.05 C DIM A A1 A3 b b2 D E e L L1 L2 A 0.05 C SIDE VIEW e/2 (b2) A1 e 1 4 8 5 C SEATING PLANE DETAIL A 8X L (L2) BOTTOM VIEW MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.15 0.25 0.30 REF 1.80 BSC 1.20 BSC 0.40 BSC 0.45 0.55 0.00 0.03 0.40 REF MOUNTING FOOTPRINT SOLDERMASK DEFINED 8X b 0.10 M C A B 0.05 M C 8X 0.66 7X 0.22 NOTE 3 1.50 1 0.32 0.40 PITCH DIMENSIONS: MILLIMETERS http://onsemi.com 10 NLSX4373 PACKAGE DIMENSIONS SO−8 CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 11 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 _ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 NLSX4373 PACKAGE DIMENSIONS Micro8t CASE 846A−02 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A-01 OBSOLETE, NEW STANDARD 846A-02. MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX A −− −− 1.10 −− −− 0.043 A1 0.05 0.08 0.15 0.002 0.003 0.006 b 0.25 0.33 0.40 0.010 0.013 0.016 c 0.13 0.18 0.23 0.005 0.007 0.009 D 2.90 3.00 3.10 0.114 0.118 0.122 E 2.90 3.00 3.10 0.114 0.118 0.122 e 0.65 BSC 0.026 BSC L 0.40 0.55 0.70 0.016 0.021 0.028 HE 4.75 4.90 5.05 0.187 0.193 0.199 D HE PIN 1 ID E e b 8 PL 0.08 (0.003) T B M S A S SEATING −T− PLANE 0.038 (0.0015) A A1 L c SOLDERING FOOTPRINT* 8X 1.04 0.041 0.38 0.015 3.20 0.126 6X 8X 4.24 0.167 0.65 0.0256 5.28 0.208 SCALE 8:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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