HCTS161AMS Radiation Hardened Synchronous Counter September 1995 Features Pinouts • 3 Micron Radiation Hardened CMOS SOS 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW • Total Dose 200K RAD (Si) • Minimum LET for SEU Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/BitDay (Typ) • Dose Rate Survivability: >1 x 1012 RAD (Si)/s • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V MR 1 16 VCC CP 2 15 TC P0 3 14 Q0 P1 4 13 Q1 P2 5 12 Q2 P3 6 11 Q3 PE 7 10 TE GND 8 9 SPE • Input Logic Levels -VIL = 0.8V Max -VIH = VCC/2V Min • Input Current Levels Ii ≤ 5µA at VOL, VOH 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C TOP VIEW Description The Intersil HCTS161AMS high-reliability high-speed presettable four-bit binary synchronous counter features asynchronous reset and look-ahead carry logic. The HCTS161AMS has an active-low master reset to zero, MR. A low level at the synchronous parallel enable, SPE, disables counting and allows data at the preset inputs (P0 - P3) to load the counter. The data is latched to the outputs on the positive edge of the clock input, CP. The HCTS161AMS has two count enable pins, PE and TE. TE also controls the terminal count output, TC. The terminal count output indicates a maximum count for one clock pulse and is used to enable the next cascaded stage to count. MR 1 16 VCC CP 2 15 TC P0 3 14 Q0 P1 4 13 Q1 P2 5 12 Q2 P3 6 11 Q3 PE 7 10 TE GND 8 9 SPE The HCTS161AMS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS161AMS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE HCTS161ADMSR -55oC to +125oC Intersil Class S Equivalent 16 Lead SBDIP HCTS161AKMSR -55oC to +125oC Intersil Class S Equivalent 16 Lead Ceramic Flatpack HCTS161AD/Sample +25oC Sample 16 Lead SBDIP HCTS161AK/Sample +25oC Sample 16 Lead Ceramic Flatpack HCTS161AHMSR +25oC Die Die CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 1 Spec Number File Number 518888 2144.2 Specifications HCTS161AMS Absolute Maximum Ratings Reliability Information Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.. Operating Conditions Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . .100ns Max Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Output Current (Sink) Output Current (Source) Output Voltage Low Output Voltage High Input Leakage Current Noise Immunity Functional Test GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 40 µA 2, 3 +125oC, -55oC - 750 µA 1 +25oC 4.8 - mA 2, 3 +125oC, -55oC 4.0 - mA 1 +25oC -4.8 - mA 2, 3 +125oC, -55oC -4.0 - mA VCC = 4.5V, VIH = 2.25V, IOL = 50µA, VIL = 0.8V 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V VCC = 5.5V, VIH = 2.75V, IOL = 50µA, VIL = 0.8V 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V VCC = 4.5V, VIH = 2.25V, IOH = -50µA, VIL = 0.8V 1, 2, 3 +25oC, +125oC, -55oC VCC -0.1 - V VCC = 5.5V, VIH = 2.75V, IOH = -50µA, VIL = 0.8V 1, 2, 3 +25oC, +125oC, -55oC VCC -0.1 - V VCC = 5.5V, VIN = VCC or GND 1 +25oC - ±0.5 µA 2, 3 +125oC, -55oC - ±5.0 µA 7, 8A, 8B +25oC, +125oC, -55oC - - V (NOTE 1) CONDITIONS SYMBOL ICC IOL IOH VOL VOH IIN FN VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V , (Note 2) VCC = 4.5V, VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0V, (Note 2) VCC = 4.5V, VIH = 2.25V, VIL = 0.8V, (Note 3) LIMITS NOTES: 1. All voltages reference to device GND. 2. Force/measure functions may be interchanged. 3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”. Spec Number 2 518888 Specifications HCTS161AMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay CP to Qn SYMBOL TPLH1 TPHL1 Propagation Delay CP to TC TPLH2 TPHL2 Propagation Delay TE to TC (NOTES 1, 2) CONDITIONS TPLH3 TPHL3 Propagation Delay MR to Q TPHL4 Propagation Delay MR to TC TPHL5 GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 9 +25oC 2 27 ns 10, 11 +125oC, -55oC 2 29 ns 9 +25oC 2 27 ns 10, 11 +125oC, -55oC 2 29 ns 9 +25oC 2 28 ns 10, 11 +125oC, -55oC 2 31 ns 9 +25oC 2 29 ns 10, 11 +125oC, -55oC 2 33 ns 9 +25oC 2 20 ns 10, 11 +125oC, -55oC 2 21 ns 9 +25oC 2 25 10, 11 +125oC, -55oC 2 29 9 +25oC 2 38 ns 10, 11 +125oC, -55oC 2 45 ns 9 +25oC 2 44 ns 10, 11 +125oC, -55oC 2 51 ns VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V LIMITS NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Capacitance Power Dissipation Input Capacitance Pulse Width Time CP Pulse Width Time MR Setup Time Pn to CP Setup Time PE to CP or TE Setup Time SPE to CP Hold Time Pn to CP SYMBOL CPD CIN TW TW TSU TSU TSU TSU (NOTE 1) CONDITIONS VCC = 5.0V, VIH = 5.0, VIL = 0.0V, f = 1MHz VCC = 5.0V, VIH = 5.0, VIL = 0.0V, f = 1MHz VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, LIMITS TEMPERATURE MIN MAX UNITS +25oC - 231 pF - 285 pF - 10 pF - 10 pF 16 - ns 24 - ns 20 - ns 30 - ns 10 - ns 15 - ns 13 - ns 20 - ns 12 - ns +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC 18 - ns +25oC 5 - ns +125oC, -55oC 5 - ns Spec Number 3 518888 Specifications HCTS161AMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL Hold Time TE or PE to CP TSU Hold Time SPE to CP TSU Recovery Time TREC Maximum Frequency FMAX (NOTE 1) CONDITIONS VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, LIMITS TEMPERATURE MIN MAX UNITS +25oC 3 - ns 3 - ns C 3 - ns -55oC 3 - ns 15 - ns +125 C, -55 C 22 - ns +25oC 0 30 MHz 0 20 MHz +125oC, -55oC +25o +125oC, o +25 C o +125o o o C, -55 C NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current (NOTES 1, 2) CONDITIONS SYMBOL ICC 200K RAD LIMITS TEMPERATURE MIN MAX UNITS VCC = 5.5V, VIN = VCC or GND +25oC - 0.75 mA 4.0 - mA Output Current (Sink) IOL VCC = 4.5V, VIH = 4.5, VIL = 0V, VOUT = 0.4V +25oC Output Current (Source) IOH VCC = 4.5V, VIH = 4.5, VIL = 0V, VOUT = VCC -0.4V +25oC -4.0 - mA Output Voltage Low VOL VCC = 4.5V, VIH = 2.25V, VIL = 0.8V , IOL = 50µA +25oC - 0.1 V VCC = 5.5V, VIH = 2.75V, VIL = 0.8V , IOL = 50µA +25oC - 0.1 V VCC = 4.5V, VIH = 2.25V, +25oC VCC -0.1 - V +25oC VCC -0.1 - V Output Voltage High VOH VIL = 0.8V, IOH = -50µA VCC = 5.5V, VIH = 2.75V, VIL = 0.8V, IOH = -50µA Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND +25oC - ±5 µA Noise Immunity Functional Test FN VCC = 4.5V, VIH = 2.25V, VIL = 0.8V , (Note 2) +25oC - - V VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC 2 29 ns Propagation Delay CP to Qn TPHL1 TPLH1 VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC 2 29 ns Propagation Delay CP to TC TPHL2 VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC 2 33 ns TPLH2 VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC 2 31 ns VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC 2 29 ns VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC 2 21 ns 2 45 ns 2 51 ns Propagation Delay TE to TC TPHL3 TPLH3 Propagation Delay MR to Q TPHL4 VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC Propagation Delay MR to TC TPHL5 VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC NOTES: 1. All voltages referenced to device GND. 2. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”. Spec Number 4 518888 Specifications HCTS161AMS TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) GROUP B SUBGROUP DELTA LIMIT ICC 5 12µA IOL/IOH 5 -15% of 0 Hour PARAMETER TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD GROUP A SUBGROUPS Initial Test (Preburn-In) 100%/5004 1, 7, 9 ICC, IOL/H Interim Test I (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H Interim Test II (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H PDA 100%/5004 1, 7, 9, Deltas Interim Test III (Postburn-In) 100%/5004 1, 7, 9 PDA 100%/5004 1, 7, 9, Deltas Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample/5005 1, 7, 9 Sample/5005 1, 7, 9 Group A (Note 1) Group B Group D READ AND RECORD ICC, IOL/H Subgroups 1, 2, 3, 9, 10, 11 NOTE: 1. Alternate group A testing in accordance with method 5005 of MIL-STD-883 may be exercised. TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUPS Group E Subgroup 2 READ AND RECORD METHOD PRE RAD POST RAD PRE RAD POST RAD 5005 1, 7, 9 Table 4 1, 9 Table 4 (Note 1) NOTE: 1. Except FN test which will be performed 100% Go/No-Go. Spec Number 5 518888 HCTS161AMS TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OSCILLATOR OPEN GROUND 1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V 50kHz 25kHz 16 - - 1 - 7, 9, 10, 16 - - 1, 3, 5, 7, 9, 10, 16 2 - STATIC BURN-IN I TEST CONNECTIONS (Note 1) 11 - 15 1 - 10 - STATIC BURN-IN II TEST CONNECTIONS (Note 1) 11 - 15 8 - DYNAMIC BURN-IN TEST CONNECTIONS (Note 2) - 4, 6, 8 11 - 15 NOTES: 1. Each pin except VCC and GND will have a resistor of 10kΩ ± 5% for static burn-in 2. Each pin except VCC and GND will have a resistor of 1kΩ ± 5% for dynamic burn-in TABLE 9. IRRADIATION TEST CONNECTIONS OPEN GROUND VCC = 5V ± 0.5V 11 - 15 8 1 - 7, 9, 10, 16 NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Spec Number 6 518888 HCTS161AMS Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) 100% Interim Electrical Test 1 (T1) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Nondestructive Bond Pull, Method 2023 100% Interim Electrical Test 2 (T2) Sample - Wire Bond Pull Monitor, Method 2011 100% Delta Calculation (T0-T2) Sample - Die Shear Monitor, Method 2019 or 2027 100% PDA 1, Method 5004 (Notes 1and 2) 100% Internal Visual Inspection, Method 2010, Condition A 100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or Equivalent, Method 1015 100% Delta Calculation (T0-T1) 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Interim Electrical Test 3 (T3) 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% PIND, Method 2020, Condition A 100% Final Electrical Test 100% External Visual 100% Fine/Gross Leak, Method 1014 100% Serialization 100% Radiographic, Method 2012 (Note 3) 100% Initial Electrical Test (T0) 100% External Visual, Method 2009 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125oC min., Method 1015 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5) NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents: • Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). • Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. • GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. • X-Ray report and film. Includes penetrometer measurements. • Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). • Lot Serial Number Sheet (Good units serial number and lot number). • Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Spec Number 7 518888 HCTS161AMS Propagation Delay Timing Diagram Propagation Delay Load Circuit DUT TEST POINT VIH INPUT VS CL VSS RL TPLH TPHL VOH CL = 50pF VS OUTPUT RL = 500Ω VOL AC VOLTAGE LEVELS PARAMETER HCTS UNITS VCC 4.50 V VIH 3.00 V VS 1.30 V VIL 0 V GND 0 V AC Load Circuit Pulse Width, Setup, Hold Timing Diagram Positive Edge Trigger DUT INPUT VIH TW TEST POINT CL RL VS VIL TH CL = 50pF RL = 500Ω TSU TW INPUT CP VIH VS VIL TH = HOLD TIME TSU = SETUP TIME TW = PULSE WIDTH VOLTAGE LEVELS PARAMETER HCTS UNITS VCC 4.50 V VIH 3.00 V VS 1.30 V VIL 0 V GND 0 V Spec Number 8 518888 HCTS161AMS Die Characteristics DIE DIMENSIONS: 86 x 104mils 2.19 x 2.65mm METALLIZATION: Type: AlSi Metal Thickness: 11kÅ ± 1kÅ GLASSIVATION: Type: SiO2 Thickness: 13kÅ ± 2.6kÅ WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 100µm x 100µm 4 x 4 mils Metallization Mask Layout HCTS161AMS CP (2) MR (1) VCC (16) (15) TC P0 (3) (14) Q0 P1 (4) (13) Q1 P2 (5) (12) Q2 P3 (6) (11) Q3 PE (7) (8) GND (9) SPE (10) TE NOTE: The die diagram is a generic plot form a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCTS161A is TA14446A. Spec Number 9 518888