74LVC244A D

74LVC244A
Low-Voltage CMOS Octal
Buffer
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
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The 74LVC244A is a high performance, non−inverting octal buffer
operating from a 1.2 to 3.6 V supply. High impedance TTL compatible
inputs significantly reduce current loading to input drivers while TTL
compatible outputs offer improved switching noise performance. A VI
specification of 5.5 V allows 74LVC244A inputs to be safely driven
from 5 V devices. The 74LVC244A is suitable for memory address
driving and all TTL level bus oriented transceiver applications.
Current drive capability is 24 mA at the outputs. The Output Enable
(OE) input, when HIGH, disables the output by placing them in
a HIGH Z condition.
TSSOP−20
DT SUFFIX
CASE 948E
•
•
Designed for 1.2 V to 3.6 V VCC Operation
5 V Tolerant − Interface Capability With 5 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
24 mA Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10 mA)
Substantially Reduces System Power Requirements
ESD Performance:
♦ Human Body Model >2000 V
♦ Machine Model >200 V
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
QFN20
MN SUFFIX
CASE 485CB
MARKING DIAGRAMS
Features
•
•
•
•
•
•
QFN20
MN SUFFIX
CASE 485AA
20
LVC
244A
ALYW G
G
1
1
1
LVC
244A
ALYWG
G
244A
ALYWG
G
QFN20 − 485AA
QFN20 − 485CB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 1
1
Publication Order Number:
74LVC244A/D
74LVC244A
VCC
2OE
1O0
2D0
1O1
2D1
1O2
2D2
1O3
2D3
20
19
18
17
16
15
14
13
12
11
1OE
1D0
1D1
1
2
3
4
5
6
7
8
9
10
1OE
1D0
2O0
1D1
2O1
1D2
2O2
1D3
2O3
GND
1D2
1D3
19
2
18
4
16
6
14
8
12
1O0
1O1
1O2
1O3
12
11
20
QFN
PIN #1
2OE
10
2D0
2
19
17
3
15
5
13
7
11
9
2O0
9
Figure 1. Pinout: 20−Lead (Top View)
2D1
PIN NAMES
2D2
PINS
FUNCTION
nOE
Output Enable Inputs
1Dn, 2Dn
Data Inputs
1On, 2On
3−State Outputs
2D3
INPUTS
OUTPUTS
1Dn
2Dn
1On, 2On
L
L
L
L
H
H
H
X
Z
2O1
2O2
2O3
Figure 2. Logic Diagram
TRUTH TABLE
1OE
2OE
1
H = High Voltage Level
L = Low Voltage Level
Z = High Impedance State
X = High or Low Voltage Level and Transitions are Acceptable
For ICC reasons, DO NOT FLOAT Inputs
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2
74LVC244A
MAXIMUM RATINGS
Symbol
VCC
Parameter
Condition
Value
Unit
−0.5 to +6.5
V
−0.5 ≤ VI ≤ +6.5
V
Output in 3−State
−0.5 ≤ VO ≤ +6.5
V
Output in HIGH or LOW State
(Note 1)
−0.5 ≤ VO ≤ VCC + 0.5
V
DC Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
IIK
DC Input Diode Current
VI < GND
−50
mA
IOK
DC Output Diode Current
VO < GND
−50
mA
VO > VCC
+50
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature, 1 mm from Case for
10 Seconds
TL = 260
°C
TJ
Junction Temperature Under Bias
TJ = 135
°C
qJA
Thermal Resistance (Note 2)
110.7
°C/W
MSL
Moisture Sensitivity
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
Supply Voltage
Operating
Functional
Typ
Max
V
1.65
1.2
3.6
3.6
VI
Input Voltage
0
5.5
VO
Output Voltage
HIGH or LOW State
3−State
0
0
VCC
5.5
IOH
IOL
Units
V
V
HIGH Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
−24
−12
mA
LOW Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
24
12
mA
TA
Operating Free−Air Temperature
−40
+125
Dt/DV
Input Transition Rise or Fall Rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 3.6 V
0
0
20
10
°C
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
74LVC244A
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
Symbol
VIH
VIL
VOH
VOL
II
−405C to +1255C
Parameter
Conditions
Min
Typ
(Note 3)
HIGH−level input
voltage
VCC = 1.2 V
1.08
−
−
1.08
−
−
VCC = 1.65 V to 1.95 V
0.65 x
VCC
−
−
0.65 x
VCC
−
−
VCC = 2.3 V to 2.7 V
1.7
−
−
1.7
−
−
VCC = 2.7 V to 3.6 V
2.0
−
−
2.0
−
−
LOW−level input
voltage
HIGH−level output
voltage
LOW−level output
voltage
Input leakage current
Max
Min
Typ
(Note 3)
Max
Unit
V
VCC = 1.2 V
−
−
0.12
−
−
0.12
VCC = 1.65 V to 1.95 V
−
−
0.35 x
VCC
−
−
0.35 x
VCC
VCC = 2.3 V to 2.7 V
−
−
0.7
−
−
0.7
VCC = 2.7 V to 3.6 V
−
−
0.8
−
−
0.8
V
V
VI = VIH or VIL
IO = −100 mA;
VCC = 1.65 V to 3.6 V
VCC −
0.2
−
−
VCC −
0.3
−
−
IO = −4 mA; VCC = 1.65 V
1.2
−
−
1.05
−
−
IO = −8 mA; VCC = 2.3 V
1.8
−
−
1.65
−
−
IO = −12 mA; VCC = 2.7 V
2.2
−
−
2.05
−
−
IO = −18 mA; VCC = 3.0 V
2.4
−
−
2.25
−
−
IO = −24 mA; VCC = 3.0 V
2.2
−
−
2.0
−
−
IO = 100 mA;
VCC = 1.65 V to 3.6 V
−
−
0.2
−
−
0.3
IO = 4 mA; VCC = 1.65 V
−
−
0.45
−
−
0.65
V
VI = VIH or VIL
IO = 8 mA; VCC = 2.3 V
−
−
0.6
−
−
0.8
IO = 12 mA; VCC = 2.7 V
−
−
0.4
−
−
0.6
IO = 24 mA; VCC = 3.0 V
−
−
0.55
−
−
0.8
VI = 5.5V or GND VCC = 3.6 V
−
±0.1
±5
−
±0.1
±20
mA
IOZ
OFF−state output
current
VI = VIH or VIL;
VO = 5.5 V or GND; VCC = 3.6 V
−
±0.1
±5
−
±0.1
±20
mA
IOFF
Power−off leakage
current
VI or VO = 5.5 V; VCC = 0.0 V
−
±0.1
±10
−
±0.1
±20
mA
ICC
Supply current
VI = VCC or GND; IO = 0 A;
VCC = 3.6 V
−
0.1
10
−
0.1
40
mA
Additional supply
current
per input pin;
VI = VCC − 0.6 V; IO = 0 A;
VCC = 2.7 V to 3.6 V
−
5
500
−
5
5000
mA
DICC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. All typical values are measured at TA = 25°C and VCC = 3.3 V, unless stated otherwise.
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74LVC244A
AC ELECTRICAL CHARACTERISTICS (tR = tF = 2.5 ns)
−405C to +855C
Symbol
tpd
ten
tdis
tsk(0)
Parameter
Propagation Delay (Note 5)
nDn to nOn
Enable Time (Note 6)
nOE to nOn
Disable Time (Note 7)
nOE to nOn
−405C to +1255C
Conditions
Min
Typ1
Max
Min
Typ1
Max
Unit
VCC = 1.2 V
−
17.0
−
−
−
−
ns
VCC = 1.65 V to 1.95 V
1.5
6.4
13.7
1.5
−
15.8
VCC = 2.3 V to 2.7 V
1.0
3.4
7.1
1.0
−
8.2
VCC = 2.7 V
1.5
3.4
6.9
1.5
−
9.0
VCC = 3.0 V to 3.6 V
1.5
2.9
5.9
1.5
−
7.5
VCC = 1.2 V
−
24.0
−
−
−
−
VCC = 1.65 V to 1.95 V
1.5
7.0
17.3
1.5
−
20.0
VCC = 2.3 V to 2.7 V
1.5
3.9
9.5
1.5
−
11.0
VCC = 2.7 V
1.5
4.1
8.6
1.5
−
11.0
VCC = 3.0 V to 3.6 V
1.0
3.2
7.6
1.0
−
9.5
VCC = 1.2 V
−
9.0
−
−
−
−
VCC = 1.65 V to 1.95 V
2.2
4.5
9.8
2.2
−
11.3
VCC = 2.3 V to 2.7 V
0.5
3.6
5.5
0.5
−
6.4
VCC = 2.7 V
1.5
3.3
6.8
1.5
−
8.5
VCC = 3.0 V to 3.6 V
1.5
3.1
5.8
1.5
−
7.5
−
−
1
−
−
1.5
Output Skew Time (Note 8)
ns
ns
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Typical values are measured at TA = 25°C and VCC = 3.3 V, unless stated otherwise.
5. tpd is the same as tPLH and tPHL.
6. ten is the same as tPZL and tPZH.
7. tdis is the same as tPLZ and tPHZ.
8. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
VOLP
Dynamic LOW Peak Voltage (Note 9)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
0.8
0.6
V
VOLV
Dynamic LOW Valley Voltage (Note 9)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
−0.8
−0.6
V
9. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
CIN
COUT
CPD
Condition
Typical
Unit
Input Capacitance
Parameter
VCC = 3.3 V, VI = 0 V or VCC
4
pF
Output Capacitance
VCC = 3.3 V, VI = 0 V or VCC
5
pF
Power Dissipation Capacitance
(Note 10)
pF
Per input; VI = GND or VCC
VCC = 1.65 V to 1.95 V
6.4
VCC = 2.3 V to 2.7 V
9.6
VCC = 3.0 V to 3.6 V
12.5
10. CPD is used to determine the dynamic power dissipation (PD in mW).
PD = CPD x VCC2 x fi x N + S (CL x VCC2 x fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF VCC = supply voltage in Volts
N = number of outputs switching
S(CL x VCC2 x fo) = sum of the outputs.
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5
74LVC244A
VCC
Vmi
1Dn, 2Dn
Vmi
0V
tPLH
tPHL
VOH
Vmo
1On, 2On
Vmo
VOL
WAVEFORM 1 − PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VCC
Vmi
1OE, 2OE
Vmi
0V
tPZH
tPHZ
VCC
VOH - 0.3 V
Vmo
1On, 2On
≈0V
tPZL
tPLZ
≈ 3.0 V
Vmo
1On, 2On
VOL + 0.3 V
GND
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 3. AC Waveforms
VCC
Symbol
3.3 V ± 0.3 V
2.7 V
Vmi
1.5 V
1.5 V
VCC/2
Vmo
1.5 V
1.5 V
VCC/2
VCC < 2.7 V
VHZ
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.15 V
VLZ
VOH − 0.3 V
VOH − 0.3 V
VOH − 015 V
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6
74LVC244A
VCC
VI
VO
PULSE
GENERATOR
R1
DUT
RT
CL
VEXT
OPEN
GND
RL
CL includes jig and probe capacitance
RT = ZOUT of pulse generator (typically 50 W)
R1 = RL
Supply Voltage
Input
Load
VEXT
VCC (V)
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
1.2
VCC
≤ 2 ns
30 pF
1 kW
Open
2 x VCC
GND
1.65 − 1.95
VCC
≤ 2 ns
30 pF
1 kW
Open
2 x VCC
GND
2.3 − 2.7
VCC
≤ 2 ns
30 pF
500 W
Open
2 x VCC
GND
2.7
2.7 V
≤ 2.5 ns
50 pF
500 W
Open
2 x VCC
GND
3 − 3.6
2.7 V
≤ 2.5 ns
50 pF
500 W
Open
2 x VCC
GND
Figure 4. Test Circuit
ORDERING INFORMATION
Package
Shipping†
TSSOP−20
(Pb−Free)
2500 / Tape & Reel
74LVC244AMN2TWG
(In Development)
QFN20, 2.5x3.5
(Pb−Free)
3000 / Tape & Reel
74LVC244AMNTWG
(In Development)
QFN20, 2.5x4.5
(Pb−Free)
3000 / Tape & Reel
Device
74LVC244ADTR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
74LVC244A
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
L
SECTION N−N
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
N
F
DETAIL E
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
6.40
6.60 0.252
0.260
B
4.30
4.50 0.169
0.177
C
--1.20
--0.047
D
0.05
0.15 0.002
0.006
F
0.50
0.75 0.020
0.030
G
0.65 BSC
0.026 BSC
−W−
H
0.27
0.37
0.011
0.015
J
0.09
0.20 0.004
0.008
J1
0.09
0.16 0.004
0.006
K
0.19
0.30 0.007
0.012
K1
0.19
0.25 0.007
0.010
L
6.40 BSC
0.252 BSC
M
0_
8_
0_
8_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
74LVC244A
PACKAGE DIMENSIONS
QFN20, 2.5x4.5 MM
CASE 485AA
ISSUE B
D
A
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
PIN ONE REFERENCE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
E
2X
0.15 C
2X
0.15 C
TOP VIEW
0.10 C
A
20X
0.08 C
(A3)
A1
SIDE VIEW
C
SEATING
PLANE
D2
e
11
20X
L
9
12
e
E2
20X
b
0.10 C A B
0.05 C
NOTE 3
19
2
1
20
20X
K
BOTTOM VIEW
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9
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.50 BSC
0.85
1.15
4.50 BSC
2.85
3.15
0.50 BSC
0.20
--0.35
0.45
74LVC244A
PACKAGE DIMENSIONS
QFN20, 2.5x3.5, 0.4P
CASE 485CB
ISSUE O
PIN ONE
REFERENCE
L
B
ÉÉÉ
ÉÉÉ
ÉÉÉ
2X
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
ÇÇÇ
ÉÉÉ
ÉÉÉ
EXPOSED Cu
0.15 C
L
L1
0.15 C
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
TOP VIEW
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTIONS
A
DETAIL B
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.15
0.25
2.50 BSC
0.90
1.10
3.50 BSC
2.00
2.20
0.40 BSC
0.35
0.45
--0.15
(A3)
0.10 C
A1
0.08 C
NOTE 4
C
SIDE VIEW
SEATING
PLANE
SOLDERING FOOTPRINT*
3.80
0.10 C A B
2.24
D2
20X
PACKAGE
OUTLINE
L
9
12
0.10 C A B
DETAIL A
20X
2.80 1.14
E2
1
20X
2
19
1
0.63
b
0.10 C A B
0.05 C
0.40
PITCH
NOTE 3
20X
0.25
DIMENSIONS: MILLIMETERS
e
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
e/2
BOTTOM VIEW
ON Semiconductor and the
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