MC74HC240A Octal 3-State Inverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS http://onsemi.com The MC74HC240A is identical in pinout to the LS240. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This octal noninverting buffer/line driver/line receiver is designed to be used with 3−state memory address drivers, clock drivers, and other sub−oriented systems. The device has inverting outputs and two active−low output enables. The HC240A is similar in function to the HC244A. SOIC−20 DW SUFFIX CASE 751D PIN ASSIGNMENT Features • • • • • • • • • Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7 A Chip Complexity: 120 FETs or 30 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free and are RoHS Compliant ENABLE A 1 20 VCC A1 2 19 ENABLE B YB4 3 18 YA1 A2 4 17 B4 YB3 5 16 YA2 A3 6 15 B3 YB2 7 14 YA3 A4 8 13 B2 YB1 9 12 YA4 GND 10 11 B1 MARKING DIAGRAMS 20 20 LOGIC DIAGRAM A1 TSSOP−20 DT SUFFIX CASE 948E HC 240A ALYWG G HC240A AWLYYWWG 2 18 4 16 6 14 8 12 11 9 13 7 YA1 1 A2 A3 A4 DATA NPUTS B1 YA2 YA3 YA4 YB1 INVERTING OUTPUTS 1 SOIC−20 TSSOP−20 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) FUNCTION TABLE B2 B3 B4 15 5 17 3 Inputs YB2 YB3 YB4 Outputs Enable A, Enable B A, B YA, YB L L H L H X H L Z Z = high impedance OUTPUT ENABLES ENABLE A ENABLE B 1 19 © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 13 ORDERING INFORMATION PIN 20 = VCC PIN 10 = GND See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. 1 Publication Order Number: MC74HC240A/D MC74HC240A MAXIMUM RATINGS Symbol Parameter Value Unit –0.5 to +7.0 V DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds (SOIC or TSSOP Package) SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/_C from 65_ to 125_C TSSOP Package: −6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min Max Unit 2.0 6.0 V 0 VCC V –55 +125 _C 0 0 0 1000 500 400 ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. http://onsemi.com 2 MC74HC240A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC V –55 to 25_C v 85_C v 125_C Unit Vout = VCC – 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V Maximum Low−Level Input Voltage Vout = 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V Minimum High−Level Output Voltage Vin = VIH |Iout| v 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 Symbol Parameter Test Conditions VIH Minimum High−Level Input Voltage VIL VOH Vin = VIH VOL |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA Vin = VIL |Iout| v 20 mA Maximum Low−Level Output Voltage |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA Vin = VIL V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA IOZ Maximum Three−State Leakage Current Output in High−Impedance State Vin = VIL or VIH Vout = VCC or GND 6.0 ± 0.5 ± 5.0 ± 10 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 4.0 40 160 mA AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V –55 to 25_C v 85_C v 125_C Unit tPLH, tPHL Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3) 2.0 3.0 4.5 6.0 80 40 16 14 100 50 20 17 120 60 24 20 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) 2.0 3.0 4.5 6.0 110 60 22 19 140 70 28 24 165 80 33 28 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) 2.0 3.0 4.5 6.0 110 60 22 19 140 70 28 24 165 80 33 28 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 3) 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 32 18 15 ns Cin Maximum Input Capacitance − 10 10 10 pF Cout Maximum Three−State Output Capacitance (Output in High−Impedance State) − 15 15 15 pF Typical @ 25°C, VCC = 5.0 V CPD 32 Power Dissipation Capacitance (Per Transceiver Channel)* * Used to determine the no−load dynamic power consumption: P D = CPD VCC http://onsemi.com 3 2f + ICC VCC . pF MC74HC240A SWITCHING WAVEFORMS VCC tr DATA INPUT A OR B ENABLE tf GND VCC 90% 50% 10% tPZL tPLZ HIGH IMPEDANCE GND tPHL tPLH OUTPUT Y 90% 50% 10% OUTPUT YA OR YB 50% 50% tPZH OUTPUT Y tTHL tPHZ 10% VOL 90% VOH 50% HIGH IMPEDANCE tTLH Figure 1. Figure 2. TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance 1 kW CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit PIN DESCRIPTIONS INPUTS function as inverters. When a high level is applied, the outputs assume the high−impedance state. A1, A2, A3, A4, B1, B2, B3, B4 (Pins 2, 4, 6, 8, 11, 13, 15, 17) OUTPUTS Data input pins. Data on these pins appear in inverted form on the corresponding Y outputs, when the outputs are enabled. YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4 (Pins 18, 16, 14, 12, 9, 7, 5, 3) Device outputs. Depending upon the state of the output−enable pins, these outputs are either inverting outputs or high−impedance outputs. CONTROLS Enable A, Enable B (Pins 1, 19) Output enables (active−low). When a low level is applied to these pins, the outputs are enabled and the devices http://onsemi.com 4 MC74HC240A LOGIC DETAIL TO THREE OTHER A OR B INVERTERS ONE OF 8 INVERTERS VCC DATA INPUT A OR B YA OR YB ENABLE A OR ENABLE B ORDERING INFORMATION Package Shipping† MC74HC240ADWG SOIC−20 WIDE (Pb−Free) 38 Units / Rail NVL74HC240ADWG* SOIC−20 WIDE (Pb−Free) 38 Units / Rail MC74HC240ADWR2G SOIC−20 WIDE (Pb−Free) 1000 Tape & Reel NVL74HC240ADWR2G* SOIC−20 WIDE (Pb−Free) 1000 Tape & Reel TSSOP−20 (Pb−Free) 2500 Tape & Reel Device MC74HC240ADTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable http://onsemi.com 5 MC74HC240A PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B −U− L PIN 1 IDENT SECTION N−N 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S N A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 1.20 --0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 0.047 --0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HC240A PACKAGE DIMENSIONS SOIC−20 DW SUFFIX CASE 751D−05 ISSUE G 20 11 X 45 _ h H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q A B M D 1 10 20X B B 0.25 M T A S B S L A 18X e A1 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ SEATING PLANE C T ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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