ISL55002, ISL55004 ® Data Sheet July 15, 2005 High Supply Voltage 220MHz Unity-Gain Stable Operational Amplifiers The ISL55002 and ISL55004 are high speed, low power, low cost monolithic operational amplifiers. The ISL55002 and ISL55004 are unity-gain stable and feature a 300V/µs slew rate and 220MHz bandwidth while requiring only 9mA of supply current. The power supply operating range of the ISL55002 and ISL55004 is from ±15V down to ±2.5V. For single-supply operation, the ISL55002 and ISL55004 operate from 30V down to 5V. The ISL55002 and ISL55004 also feature an extremely wide output voltage swing of -12.75V/+13.4V with VS = ±15V and RL = 1kΩ. At a gain of +1, the ISL55002 and ISL55004 have a -3dB bandwidth of 220MHz with a phase margin of 50°. Because of its conventional voltage-feedback topology, the ISL55002 and ISL55004 allow the use of reactive or non-linear elements in its feedback network. This versatility combined with low cost and 140mA of output-current drive makes the ISL55002 and ISL55004 an ideal choice for price-sensitive applications requiring low power and high speed. The ISL55002 is available in an 8-pin SO package and the ISL55004 in a 14-pin SO (0.150”) package. All are specified for operation over the full -40°C to +85°C temperature range. FN7497.1 Features • 220MHz -3dB bandwidth • Unity-gain stable • Low supply current: 9mA @ VS = ±15V • Wide supply range: ±2.5V to ±15V dual-supply and 5V to 30V single-supply • High slew rate: 300V/µs • Fast settling: 75ns to 0.1% for a 10V step • Wide output voltage swing: -12.75V/+13.6V with VS = ±15V, RL = 1kΩ • Low cost, enhanced replacement for the AD847 and LM6361 • Pb-free plus anneal available (RoHS compliant) Applications • Video amplifiers • Single-supply amplifiers • Active filters/integrators • High speed sample-and-hold • High speed signal processing • ADC/DAC buffers • Pulse/RF amplifiers • Pin diode receivers • Log amplifiers • Photo multiplier amplifiers • Difference amplifiers Pinouts ISL55004 [14-PIN SO (0.150”)] TOP VIEW ISL55002 (8-PIN SO) TOP VIEW OUT 1 IN1- 2 IN1+ 3 8 VS+ - + + - VS- 4 OUT1 1 7 OUT2 IN1- 2 6 IN2- IN1+ 3 12 IN4+ 5 IN2+ VS+ 4 11 VS- IN2+ 5 10 IN3+ IN2- 6 OUT2 7 1 14 OUT4 - + - + + - + - 13 IN4- 9 IN38 OUT3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL55002, ISL55004 Ordering Information PACKAGE TAPE & REEL PKG. DWG. # ISL55002IB 8-Pin SO - M8.15 ISL55002IB-T7 8-Pin SO 7” M8.15 ISL55002IB-T13 8-Pin SO 13” M8.15 ISL55002IBZ (See Note) 8-Pin SO (Pb-Free) - M8.15 ISL55002IBZ-T7 (See Note) 8-Pin SO (Pb-Free) 7” M8.15 ISL55002IBZ-T13 (See Note) 8-Pin SO (Pb-Free) 13” M8.15 ISL55004IB 14-Pin SO (0.150”) - M14.15 ISL55004IB-T7 14-Pin SO (0.150”) 7” M14.15 ISL55004IB-T13 14-Pin SO (0.150”) 13” M14.15 ISL55004IBZ (See Note) 14-Pin SO (0.150”) (Pb-Free) - M14.15 ISL55004IBZ-T7 (See Note) 14-Pin SO (0.150”) (Pb-Free) 7” M14.15 ISL55004IBZ-T13 (See Note) 14-Pin SO (0.150”) (Pb-Free) 13” M14.15 PART NUMBER NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7497.1 July 15, 2005 ISL55002, ISL55004 Absolute Maximum Ratings (TA = 25°C) Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Operating Temperature Range (TA). . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . +150°C Storage Temperature (TST) . . . . . . . . . . . . . . . . . . .-65°C to +150°C Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . ±16.5V or 33V Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±VS Differential Input Voltage (dVIN). . . . . . . . . . . . . . . . . . . . . . . . .±10V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER VS = ±15V, RL = 1kΩ, TA = 25°C, unless otherwise specified. DESCRIPTION CONDITION MIN TYP MAX UNIT 1.2 5 mV VOS Input Offset Voltage TCVOS Average Offset Voltage Drift IB Input Bias Current VS = ±15V 0.6 3.5 µA IOS Input Offset Current VS = ±15V 0.2 2 µA TCIOS Average Offset Current Drift (Note 1) AVOL Open-loop Gain VS = ±15V, VOUT = ±10V, RL = 1kΩ PSRR Power Supply Rejection Ratio CMRR VS = ±15V µV/°C TBD nA/°C 12000 21000 V/V VS = ±5V to ±15V 75 100 dB Common-mode Rejection Ratio VCM = ±10V, VOUT = 0V 75 90 dB CMIR Common-mode Input Range VS = ±15V 13 V VOUT Output Voltage Swing VO+, RL = 1kΩ 13.3 13.4 V/V VO-, RL = 1kΩ -12.6 -12.75 V/V VO+, RL = 150Ω 9.6 10.7 V/V VO-, RL = 150Ω -6.5 -8.2 V/V 80 140 mA ISC Output Short Circuit Current TA = 25°C IS Supply Current (per amplifier) VS = ±15V, no load RIN Input Resistance CIN Input Capacitance ROUT PSOR 9 2.0 9.5 mA 3.2 MΩ AV = +1 @10MHz 1 pF Output Resistance AV = +1 50 mΩ Power Supply Operating Range Dual supply Single supply ±2.25 ±15 V 4.5 30 V MAX UNIT NOTE: 1. Measured from TMIN to TMAX. AC Electrical Specifications PARAMETER BW VS = ±15V, AV = +1, RL = 1kΩ unless otherwise specified. DESCRIPTION -3dB Bandwidth (VOUT = 0.4VPP) CONDITION MIN TYP VS = ±15V, AV = +1 220 MHz VS = ±15V, AV = -1 55 MHz VS = ±15V, AV = +2 53 MHz VS = ±15V, AV = +5 17 MHz GBWP Gain Bandwidth Product VS = ±15V 70 MHz PM Phase Margin RL = 1kΩ, CL = 5pF 55 ° 3 FN7497.1 July 15, 2005 ISL55002, ISL55004 AC Electrical Specifications PARAMETER VS = ±15V, AV = +1, RL = 1kΩ unless otherwise specified. (Continued) DESCRIPTION CONDITION MIN TYP MAX UNIT 260 300 V/µs SR Slew Rate (Note 1) FPBW Full-power Bandwidth (Note 2) VS = ±15V 9.5 MHz tS Settling to +0.1% (AV = +1) VS = ±15V, 10V step 75 ns dG Differential Gain (Note 3) NTSC/PAL 0.01 % dP Differential Phase NTSC/PAL 0.05 ° eN Input Noise Voltage 10kHz 12 nV/√Hz iN Input Noise Current 10kHz 1.5 pA/√Hz NOTES: 1. Slew rate is measured on rising edge. 2. For VS = ±15V, VOUT = 10VPP, for VS = ±5V, VOUT = 5VPP. Full-power bandwidth is based on slew rate measurement using FPBW = SR / (2π * VPEAK). 3. Video performance measured at VS = ±15V, AV = +2 with two times normal video level across RL = 150Ω. This corresponds to standard video levels across a back-terminated 75Ω load. For other values or RL, see curves. Typical Performance Curves FIGURE 1. OPEN-LOOP GAIN vs FREQUENCY FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS NONINVERTING GAIN SETTINGS 4 FIGURE 2. OPEN-LOOP PHASE vs FREQUENCY FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS INVERTING GAIN SETTINGS FN7497.1 July 15, 2005 ISL55002, ISL55004 Typical Performance Curves FIGURE 5. PHASE vs FREQUENCY FOR VARIOUS NONINVERTING GAIN SETTINGS FIGURE 6. PHASE vs FREQUENCY FOR VARIOUS INVERTING GAIN SETTINGS SLEW RATE (V/µs) 350 AV=+2 RF=500Ω 300 RL=500Ω CL=5pF 250 POSITIVE SLEW RATE NEGATIVE SLEW RATE 200 150 100 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGES (±V) FIGURE 7. GAIN BANDWIDTH PRODUCT vs SUPPLY FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +1) 5 FIGURE 8. SLEW RATE vs SUPPLY FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +2) FN7497.1 July 15, 2005 ISL55002, ISL55004 Typical Performance Curves FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +1) FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +2) FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS RFEEDBACK (AV = +1) FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS RFEEDBACK (AV = +2) NORMALIZED GAIN (dB) 5 AV=+1 RF=0Ω 3 RL=500Ω CL=5pF VS=±5V VS=±2.5V 1 VS=±15V -1 VS=±10V -3 -5 100K 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS INVERTING INPUT CAPACITANCE (CIN) 6 FIGURE 16. GAIN vs FREQUENCY FOR VARIOUS SUPPLY SETTINGS FN7497.1 July 15, 2005 ISL55002, ISL55004 Typical Performance Curves FIGURE 17. COMMON-MODE REJECTION RATIO (CMRR) FIGURE 18. POWER SUPPLY REJECTION RATIO (PSRR) HARMONIC DISTORTION (dBc) -20 VS=±15V -30 AV=+1 RF=0Ω -40 RL=500Ω CL=5pF -50 VOUT=2VP-P THD -60 2ND HD -70 3RD HD -80 -90 -100 500K 1M 10M 40M FREQUENCY (Hz) FIGURE 19. HARMONIC DISTORTION vs FREQUENCY (AV = +1) FIGURE 20. HARMONIC DISTORTION vs OUTPUT VOLTAGE (AV = +2) FIGURE 21. OUTPUT SWING vs FREQUENCY FOR VARIOUS GAIN SETTINGS FIGURE 22. OUTPUT SWING vs SUPPLY VOLTAGE FOR VARIOUS GAIN SETTINGS 7 FN7497.1 July 15, 2005 ISL55002, ISL55004 Typical Performance Curves 20% to 80% 80% to 20% 20% to 80% 80% to 20% FIGURE 23. LARGE SIGNAL RISE AND FALL TIMES FIGURE 24. SMALL SIGNAL RISE AND FALL TIMES POWER DISSIPATION (W) 1.2 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD SO14 θJA=120°C/W 1 1.042W 0.8 781mW 0.6 SO8 θJA=160°C/W 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 25. SUPPLY CURRENT vs SUPPLY VOLTAGE 1.8 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.6 POWER DISSIPATION (W) FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 1.420W 1.4 SO14 θJA=88°C/W 1.2 1 1.136W 0.8 SO8 θJA=110°C/W 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 8 FN7497.1 July 15, 2005 ISL55002, ISL55004 Product Description The ISL55002 and ISL55004 are wide bandwidth, low power, and low offset voltage feedback operational amplifiers. These devices are internally compensated for closed loop gain of +1 or greater. Connected in voltage follower mode and driving a 500Ω load, the -3dB bandwidth is around a 220MHz. Driving a 150Ω load and a gain of 2, the bandwidth is about 90MHz while maintaining a 300V/µs slew rate. The ISL55002 and ISL55004 are designed to operate with supply voltage from +15V to -15V. That means for single supply application, the supply voltage is from 0V to 30V. For split supplies application, the supply voltage is from ±15V. The amplifier has an input common-mode voltage range from 1.5V above the negative supply (VS- pin) to 1.5V below the positive supply (VS+ pin). If the input signal is outside the above specified range, it will cause the output signal to be distorted. The outputs of the ISL55002 and ISL55004 can swing from -12.75V to +13.4V for VS = ±15V. As the load resistance becomes lower, the output swing is lower. Choice Of Feedback Resistor And Gain Bandwidth Product For applications that require a gain of +1, no feedback resistor is required. Just short the output pin to the inverting input pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, RF can't be very big for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. For gain of +1, RF = 0 is optimum. For the gains other than +1, optimum response is obtained with RF with proper selection of RF and RG (see Figures15 and 16 for selection.) Video Performance For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150Ω, because of the change in output current with DC level. The dG and dP of this device is about 0.01% and 0.05°, while driving 150Ω at a gain of 2. Driving high impedance loads would give a similar or better dG and dP performance. Driving Capacitive Loads and Cables The ISL55002 and ISL55004 can drive 47pF loads in parallel with 500Ω with less than 3dB of peaking at gain of +1 and as much as 100pF at a gain of +2 with under 3db of peaking. If less peaking is desired in applications, a small series resistor 9 (usually between 5Ω to 50Ω) can be placed in series with the output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. Output Drive Capability The ISL55002 and ISL55004 do not have internal short circuit protection circuitry. They have a typical short circuit current of 140mA. If the output is shorted indefinitely, the power dissipation could easily overheat the die or the current could eventually compromise metal integrity. Maximum reliability is maintained if the output current never exceeds ±60mA. This limit is set by the design of the internal metal interconnect. Note that in transient applications, the part is robust. Short circuit protection can be provided externally with a back match resistor in series with the output placed close as possible to the output pin. In video applications this would be a 75Ω resistor and will provide adequate short circuit protection to the device. Care should still be taken not to stress the device with a short at the output. Power Dissipation With the high output drive capability of the ISL55002 and ISL55004, it is possible to exceed the 150°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX – T AMAX PD MAX = -------------------------------------------Θ JA Where: • TJMAX = Maximum junction temperature • TAMAX = Maximum ambient temperature • θJA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: FN7497.1 July 15, 2005 ISL55002, ISL55004 Sullen Key High Pass Filter For sourcing: n V OUTi ∑ ( VS – VOUTi ) × ---------------R Li PD MAX = V S × I SMAX + i=1 For sinking: Again this useful filter benefits from the characteristics of the ISL55002 and ISL55004. The transfer function is very similar to the low pass so only the results are presented (See Figure 29). n ∑ ( VOUTi – VS ) × ILOADi PD MAX = V S × I SMAX + i=1 Where: • VS = Supply voltage • ISMAX = Maximum quiescent supply current • VOUT = Maximum output voltage of the application • RLOAD = Load resistance tied to ground • ILOAD = Load current • N = number of amplifiers (max = 2) By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat. Power Supply Bypassing Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. Printed Circuit Board Layout For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. Application Circuits Sullen Key Low Pass Filter A common and easy to implement filter taking advantage of the wide bandwidth, low offset and low power demands of the ISL55002 and ISL55004. A derivation of the transfer function is provided for convenience (See Figure 28). 10 FN7497.1 July 15, 2005 ISL55002, ISL55004 K = 1+ V2 5V 1 V1 R2C2s + 1 Vo V1 − Vi Vo − Vi K 1 + − V1 + =0 1 R1 R2 C1s K H(s) = R1C1R2C2s 2 + ((1 − K )R1C1 + R1C2 + R21C2)s + 1 1 H( jw ) = 2 1 − w R1C1R2C2 + jw ((1 − K )R1C1 + R1C2 + R2C2) Vo = K C5 1nF C1 1nF R1 V1 R2 1kΩ 1kΩ C2 1nF + V+ - V- VOUT R7 1kΩ RB Holp = K 1kΩ RA 1kΩ RB RA C5 wo = 1nF Q= V3 5V 1 R1C1R2C2 1 R1C1 R1C2 R2C2 (1 − K ) + + R2C2 R2C1 R1C1 Holp = K Equations simplify if we let all components be equal R=C 1 wo = RC 1 Q= 3 −K FIGURE 28. SULLEN KEY LOW PASS FILTER V2 5V Holp = K C5 1nF C1 V1 1kΩ R2 1kΩ C2 1nF 1 (1 − K ) + V+ - V- R1C1 R1C2 R2C2 + + R2C2 R2C1 R1C1 VOUT R7 1kΩ RB RA 1kΩ R1C1R2C2 Q= 1nF R1 1 wo = Holp = 1kΩ C5 1nF V3 5V wo = K 4 −K 2 RC Equations simplify if we let all components be equal R=C 2 Q= 4 −K FIGURE 29. SULLEN KEY HIGH PASS FILTER 11 FN7497.1 July 15, 2005 ISL55002, ISL55004 Differential Output Instrumentation Amplifier e o3 = – ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 ) The addition of a third amplifier to the conventional three amplifier instrumentation amplifier introduces the benefits of differential signal realization, specifically the advantage of using common-mode rejection to remove coupled noise and ground potential errors inherent in remote transmission. This configuration also provides enhanced bandwidth, wider output swing and faster slew rate than conventional three amplifier solutions with only the cost of an additional amplifier and few resistors. e1 A1 + - R3 A3 + RG R3 R3 R3 R3 A4 R2 A2 e2 + e o = – 2 ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 ) 2f C1, 2 BW = ----------------A Di + R3 A Di = – 2 ( 1 + 2R 2 ⁄ R G ) Strain Gauge The strain gauge is an ideal application to take advantage of the moderate bandwidth and high accuracy of the ISL55002 and ISL55004. The operation of the circuit is very straightforward. As the strain variable component resistor in the balanced bridge is subjected to increasing strain, its resistance changes, resulting in an imbalance in the bridge. A voltage variation from the referenced high accuracy source is generated and translated to the difference amplifier through the buffer stage. This voltage difference as a function of the strain is converted into an output voltage. R3 R2 e o4 = ( 1 + 2R 2 ⁄ R G ) ( e 1 – e 2 ) eo3 + REF eo eo4 R3 +V 2 5V C6 VARIABLE SUBJECT TO STRAIN V5 + 0V - R15 1kΩ 1kΩ R16 1kΩ 1nF R17 1kΩ R18 1kΩ 1kΩ + V+ - V- VOUT RL (V1+V2+V3+V4) 1kΩ RF 1kΩ C12 1nF + V4 - 5V 12 FN7497.1 July 15, 2005 ISL55002, ISL55004 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA 0.25(0.010) M H INCHES B M E SYMBOL -B- 1 2 3 L SEATING PLANE -A- h x 45o A D e µα A1 B 0.25(0.010) M C 0.10(0.004) C A M 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MAX NOTES 0.0532 0.0688 1.35 1.75 - 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o α NOTES: MIN A N B S MILLIMETERS MAX A1 e -C- MIN 8 0o 8 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 13 FN7497.1 July 15, 2005 ISL55002, ISL55004 Small Outline Plastic Packages (SOIC) M14.15 (JEDEC MS-012-AB ISSUE C) N 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA 0.25(0.010) M H INCHES B M E -B1 2 3 L SEATING PLANE -A- h x 45o A D µα e A1 B C 0.10(0.004) 0.25(0.010) M C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3367 0.3444 8.55 8.75 3 E 0.1497 0.1574 3.80 4.00 4 e -C- B S MILLIMETERS 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α 14 0o 14 8o 0o 7 8o NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN7497.1 July 15, 2005