NLAST9431 D

NLAST9431
Low Voltage Single Supply
Dual DPDT Analog Switch
The NLAST9431 is an advanced CMOS dual−independent DPDT
(double pole−double throw) analog switch, fabricated with silicon
gate CMOS technology. It achieves high−speed propagation delays
and low ON resistances while maintaining CMOS low−power
dissipation. This DPDT controls analog and digital voltages that may
vary across the full power−supply range (from VCC to GND).
The device has been designed so the ON resistance (RON) is much
lower and more linear over input voltage than RON of typical CMOS
analog switches.
The channel−select input structure provides protection when
voltages between 0 V and 5.5 V are applied, regardless of the supply
voltage. This input structure helps prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup,
hot insertion, etc.
The NLAST9431 can also be used as a quad 2−to−1 multiplexer−
demultiplexer analog switch with two Select pins that each controls
two multiplexer−demultiplexers.
•
•
•
•
•
•
•
•
•
•
Select Pins Compatible with TTL Levels
http://onsemi.com
MARKING
DIAGRAMS
ÎÎ
ÎÎ
16
1
WQFN16
CASE 488AP
BB
M
G
BB M
G
= Specific Device Code
= Date Code & Assembly Location
= Pb−Free Device
Channel Select Input Overvoltage Tolerant to 5.5 V
ORDERING INFORMATION
Fast Switching and Propagation Speeds
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Break−Before−Make Circuitry
Low Power Dissipation: ICC = 2 A (Max) at TA = 25°C
Diode Protection Provided on Channel Select Input
Improved Linearity and Lower ON Resistance over Input Voltage
Latch−up Performance Exceeds 300 mA
Chip Complexity: 158 FETs
Pb−Free Packages are Available
© Semiconductor Components Industries, LLC, 2008
July, 2008 − Rev. 2
1
Publication Order Number:
NLAST9431/D
NLAST9431
QFN−16 PACKAGE
COM A
NO A0
VCC
NC D1
1
2
3
NC B1
GND
NO C0
COM C
4
COM A
2
16
VCC
COM B
SELECT CD
COM C
14
3
COM D
13
NO D0
5
12
SELECT CD
COM B
6
11
NC C1
NC B1
7
10
COM C
GND
8
9
NO C0
ELECT AB
4
NO B0
NC A1
2
NO B0
2/3
3
NC B1
X1
0
NO C0
1
NC C1
2
NO D0
3
NC D1
0/1
COM D
U
NC A1
1
0/1
NC D1
U
15
NO A0
U
1
0
U
NO A0
U
COM A
U
TSSOP−16 PACKAGE
X1
U
5
6
7
8
SELECT AB
U
NC C1
NC to COM
NO to COM
U
SCD
L
H
U
NO D0
ON Channel
U
See TSSOP−16
Switch Configuration
COM D
Select AB or CD
U
13
9
COM B
14
10
NO B0
15
11
SAB
16
12
NC A1
FUNCTION TABLE
2/3
Figure 2. IEC Logic Symbol
Figure 1. Logic Diagram
http://onsemi.com
2
NLAST9431
MAXIMUM RATINGS
Symbol
Parameter
VCC
Positive DC Supply Voltage
VIS
Analog Input Voltage (VNO or VCOM)
VIN
Digital Select Input Voltage
IIK
DC Current, Into or Out of Any Pin
PD
Power Dissipation in Still Air
TSTG
Storage Temperature Range
TL
Value
Unit
*0.5 to )7.0
V
*0.5 ≤ VIS ≤ VCC )0.5
V
*0.5 ≤ VI ≤ )7.0
V
$50
mA
800
450
mW
*65 to )150
°C
Lead Temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction Temperature Under Bias
+150
°C
MSL
Moisture Sensitivity
FR
Flammability Rating
ILATCH−UP
Latch−Up Performance
JA
Thermal Resistance
QFN−16
TSSOP−16
Level 1
Oxygen Index: 30% − 35%
UL−94−VO (0.125 in)
Above VCC and Below GND at 125°C (Note 1)
QFN−16
TSSOP−16
$300
mA
80
164
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
5.5
V
VCC
DC Supply Voltage
VIN
Digital Select Input Voltage
GND
5.5
V
VIS
Analog Input Voltage (NC, NO, COM)
GND
VCC
V
TA
Operating Temperature Range
*55
)125
°C
tr, tf
Input Rise or Fall Time, SELECT
0
0
100
20
ns/V
VCC = 3.3 V $ 0.3 V
VCC = 5.0 V $ 0.5 V
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80°C
117.8
TJ = 90°C
1,032,200
TJ = 100°C
80
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 110°C
Time, Years
TJ = 120°C
Time, Hours
TJ = 130°C
Junction
Temperature °C
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
1
1
10
100
1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
http://onsemi.com
3
NLAST9431
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Condition
VCC
*555C to 255C
t855C
t1255C
Unit
VIH
Minimum High−Level Input
Voltage, Select Inputs
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
VIL
Maximum Low−Level Input
Voltage, Select Inputs
3.0
4.5
5.5
0.5
0.8
0.8
0.5
0.8
0.8
0.5
0.8
0.8
V
IIN
Maximum Input Leakage
Current
VIN = 5.5 V or GND
5.5
$0.2
$2.0
$2.0
A
IOFF
Power Off Leakage Current,
Select Inputs
VIN = 5.5 V or GND
0
$10
$10
$10
A
ICC
Maximum Quiescent Supply
Current
Select and VIS = VCC or GND
5.5
4.0
4.0
8.0
A
DC ELECTRICAL CHARACTERISTICS − Analog Section
Guaranteed Limit
Symbol
Parameter
Condition
VCC
*555C to 255C
t855C
t1255C
Unit
RON
Maximum “ON” Resistance
(Figures 17 − 23)
VIN = VIL or VIH
VIS = GND to VCC
IINI v 10.0 mA
2.5
3.0
4.5
5.5
85
45
30
25
95
50
35
30
105
55
40
35
RFLAT
(ON)
ON Resistance Flatness
(Figures 17 − 23)
VIN = VIL or VIH
IINI v10.0 mA
VIS = 1 V, 2 V, 3.5 V
4.5
4
4
5
INC(OFF)
INO(OFF)
NO or NC Off Leakage
Current (Figure 9)
VIN = VIL or VIH
VNO or VNC = 1.0 VCOM 4.5 V
5.5
1
10
100
nA
ICOM(ON)
COM ON Leakage Current
(Figure 9)
VIN = VIL or VIH
VNO 1.0 V or 4.5 V with VNC floating or
VNO 1.0 V or 4.5 V with VNO floating
VCOM = 1.0 V or 4.5 V
5.5
1
10
100
nA
http://onsemi.com
4
NLAST9431
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Guaranteed Maximum Limit
Symbol
Parameter
VCC
VIS
*555C to 255C
t855C
t1255C
Test Conditions
(V)
(V)
Min
Typ*
Max
Min
Max
Min
Max
Unit
tON
Turn−On Time
(Figures 12 and 13)
RL = 300 CL = 35 pF
(Figures 5 and 6)
2.5
3.0
4.5
5.5
2.0
2.0
3.0
3.0
5
5
2
2
23
16
11
9
35
24
16
14
5
5
2
2
38
27
19
17
5
5
2
2
41
30
22
20
ns
tOFF
Turn−Off Time
(Figures 12 and 13)
RL = 300 CL = 35 pF
(Figures 5 and 6)
2.5
3.0
4.5
5.5
2.0
2.0
3.0
3.0
1
1
1
1
7
5
4
3
12
10
6
5
1
1
1
1
15
13
9
8
1
1
1
1
18
16
12
11
ns
tBBM
Minimum Break−Before−Make
Time
VIS = 3.0 V (Figure 4)
RL = 300 CL = 35 pF
2.5
3.0
4.5
5.5
2.0
2.0
3.0
3.0
1
1
1
1
12
11
6
5
1
1
1
1
1
1
1
1
ns
*Typical Characteristics are at 25°C.
Typical @ 25, VCC = 5.0 V
CIN
CNO or CNC
CCOM
C(ON)
Maximum Input Capacitance, Select Input
Analog I/O (Switch Off)
Common I/O (Switch Off)
Feedthrough (Switch On)
8
10
10
20
pF
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol
Parameter
Condition
VCC
Typical
V
255C
Unit
BW
Maximum On−Channel *3 dB Bandwidth or
Minimum Frequency Response
(Figure 11)
VIN = 0 dBm
VIN centered between VCC and GND
(Figure 7)
3.0
4.5
5.5
145
170
175
MHz
VONL
Maximum Feedthrough On Loss
VIN = 0 dBm @ 100 kHz to 50 MHz
VIN centered between VCC and GND
(Figure 7)
3.0
4.5
5.5
−3
−3
−3
dB
VISO
Off−Channel Isolation
(Figure 10)
f = 100 kHz; VIS = 1 V RMS
VIN centered between VCC and GND
(Figure 7)
3.0
4.5
5.5
−93
−93
−93
dB
Q
Charge Injection Select Input to Common I/O
(Figure 15)
VIN = VCC to GND, FIS = 20 kHz
tr = tf = 3 ns
RIS = 0 , CL = 1000 pF
Q = CL * VOUT (Figure 8)
3.0
5.5
1.5
3.0
pC
THD
Total Harmonic Distortion
THD ) Noise
(Figure 14)
FIS = 20 Hz to 100 kHz, RL = Rgen = 600 ,
CL = 50 pF
VIS = 5.0 VPP sine wave
5.5
0.1
Channel to Channel Crosstalk
f = 100 kHz; VIS = 1 V RMS
VIN centered between VCC and GND
(Figure 7)
5.5
3.0
−90
−90
VCT
http://onsemi.com
5
%
dB
NLAST9431
VCC
DUT
VCC
Input
Output
GND
VOUT
0.1 F
300 tBMM
35 pF
90%
90% of VOH
Output
Switch Select Pin
GND
Figure 4. tBBM (Time Break−Before−Make)
VCC
DUT
VCC
0.1 F
Input
Output
50%
VOUT
Open
50%
0V
300 VOH
35 pF
90%
90%
Output
VOL
Input
tON
tOFF
Figure 5. tON/tOFF
VCC
VCC
Input
DUT
Output
50%
VOUT
Open
50%
0V
300 VOH
35 pF
Output
10%
VOL
Input
tOFF
Figure 6. tON/tOFF
http://onsemi.com
6
10%
tON
NLAST9431
50 DUT
Reference
Transmitted
Input
Output
50 Generator
50 Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is
the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction.
ǒVVOUT
Ǔ for VIN at 100 kHz
IN
VOUT
Ǔ for VIN at 100 kHz to 50 MHz
VONL = On Channel Loss = 20 Log ǒ
VIN
VISO = Off Channel Isolation = 20 Log
Bandwidth (BW) = the frequency 3 dB below VONL
VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50 Figure 7. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
DUT
VCC
VIN
Output
Open
GND
CL
Output
Off
On
VIN
Figure 8. Charge Injection: (Q)
100
LEAKAGE (nA)
10
1
0.1
ICOM(ON)
ICOM(OFF)
0.01
0.001
−55
VCC = 5.0 V
INO(OFF)
−20
25
70
85
TEMPERATURE (°C)
Figure 9. Switch Leakage vs. Temperature
http://onsemi.com
7
125
Off
VOUT
NLAST9431
+15
0
1.0
2.0
−20
+10
Bandwidth
(ON−RESPONSE)
+5
3.0
−40
4.0
(dB)
(dB)
Off Isolation
−60
VCC = 5.0 V
TA = 25°C
−80
−100
0.01
0.1
−10
6.0
−15
7.0
−20
8.0
9.0
10.0
0.01
100 200
1
10
FREQUENCY (MHz)
25
20
20
TIME (ns)
TIME (ns)
25
15
tON (ns)
tOFF (ns)
0
2.5
3
3.5
4
−30
0.1
1
−35
100 300
10
Figure 11. Typical Bandwidth and Phase Shift
30
5
−25
VCC = 5.0 V
TA = 25°C
FREQUENCY (MHz)
30
10
−5
5.0
Figure 10. Off−Channel Isolation
4.5
VCC = 4.5 V
15
10
tON
5
tOFF
0
−55
5
−40
25
85
125
VCC (VOLTS)
Temperature (°C)
Figure 12. tON and tOFF vs. VCC at 255C
Figure 13. tON and tOFF vs. Temp
1
3.0
VINpp = 3.0 V
VCC = 3.6 V
2.5
2.0
Q (pC)
THD + NOISE (%)
0
PHASE SHIFT
PHASE (°)
0
0.1
VINpp = 5.0 V
VCC = 5.5 V
VCC = 5 V
1.5
1.0
0.5
VCC = 3 V
0
0.01
1
10
−0.5
0
100
1
2
3
4
FREQUENCY (kHz)
VCOM (V)
Figure 14. Total Harmonic Distortion
Plus Noise vs. Frequency
Figure 15. Charge Injection vs. COM Voltage
http://onsemi.com
8
5
NLAST9431
100
100
VCC = 2.0 V
10
80
RON ()
1
ICC (nA)
0.1
0.01
60
VCC = 2.5 V
40
VCC = 3.0 V
0.001
VCC = 3.0 V
VCC = 4.0 V
20
0.0001
VCC = 5.0 V
0.00001
−40
−20
0
20
60
VCC = 5.5 V
80
100
0
0.0
120
80
70
70
60
60
RON ()
90
50
40
125°C
30
10
85°C
0.5
40
25°C
20
−55°C
1.0
1.5
2.0
0
0.0
2.5
−55°C
85°C
125°C
0.5
1.0
1.5
VIS (VDC)
2.0
2.5
3.0
VIS (VDC)
Figure 18. RON vs Temp, VCC = 2.0 V
Figure 19. RON vs. Temp, VCC = 2.5 V
30
50
45
25
40
35
20
30
RON ()
RON ()
6.0
50
30
25°C
20
25
20
125°C
15
15
10
85°C
10
0
0.0
5.0
Figure 17. RON vs. VCC, Temp = 255C
80
5
4.0
Figure 16. ICC vs. Temp, VCC = 3 V and 5 V
90
RON ()
3.0
VIS (VDC)
100
0
0.0
2.0
Temperature (°C)
100
10
1.0
−55°C
0.5
5
25°C
1.0
1.5
2.0
2.5
3.0
3.5
0
0.0
25°C
85°C
125°C
−55°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VIS (VDC)
VIS (VDC)
Figure 21. RON vs. Temp, VCC = 4.5 V
Figure 20. RON vs. Temp, VCC = 3.0 V
http://onsemi.com
9
4.5
NLAST9431
25
25
125°C
20
20
RON ()
RON ()
125°C
15
25°C
10
−55°C
85°C
5
0
0.0
15
25°C
10
85°C
−55°C
5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
5.0
VIS (VDC)
VIS (VDC)
Figure 22. RON vs. Temp, VCC = 5.0 V
Figure 23. RON vs. Temp, VCC = 5.5 V
DEVICE ORDERING INFORMATION
Device Nomenclature
Device Order
Number
NLAST9431MTR2G
Circuit
Indicator
Technology
Device
Function
Package
Suffix
Tape and Reel
Suffix
NL
AST
9431
MT
R2G
Package Type
Shipping†
WQFN−16
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
10
NLAST9431
PACKAGE DIMENSIONS
WQFN16, 1.8x2.6, 0.4P
CASE 488AP−01
ISSUE B
D
ÏÏ
ÏÏ
ÏÏ
ÏÏ
PIN 1 REFERENCE
2X
2X
L
A
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
ÏÏÏ
ÎÎ
ÏÏ
ÏÏÏ ÎÎ
EXPOSED Cu
0.15 C
B
DIM
A
A1
A3
b
D
E
e
L
L1
L2
ALTERNATE
CONSTRUCTIONS
SEATING
PLANE
A1
A3
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.050
0.20 REF
0.15
0.25
1.80 BSC
2.60 BSC
0.40 BSC
0.30
0.50
0.00
0.15
0.40
0.60
MOUNTING FOOTPRINT*
C
0.562
0.0221
8
15 X L
4
A3
A1
0.08 C
DETAIL A
MOLD CMPD
DETAIL B
A
DETAIL B
5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
5. EXPOSED PADS CONNECTED TO DIE FLAG.
USED AS TEST CONTACTS.
L1
0.15 C
0.10 C
L
0.400
0.0157
9
0.225
0.0089
1
e
1
2.900
0.1142
12
16
L2
16 X
b
0.463
0.0182
0.10 C A B
0.05 C
1.200
0.0472
NOTE 3
2.100
0.0827
SCALE 20:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
11
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loca
Sales Representative
NLAST9431/D