NCP349 D

NCP349
Positive Overvoltage
Protection Controller with
Internal Low RON NMOS FET
The NCP349 is able to disconnect the systems from its output pin
when wrong input operating conditions are detected. The system is
positive overvoltage protected up to +28 V.
This device uses an internal NMOS and therefore, no external
device is necessary, reducing the system cost and the PCB area of the
application board.
The NCP349 is able to instantaneously disconnect the output from
the input, due to integrated Low RON Power NMOS (65 mW), if the
input voltage exceeds the overvoltage threshold (OVLO) or falls
below the undervoltage threshold (UVLO).
At powerup (EN pin = low level), the Vout turns on ton time after
the Vin exceeds the undervoltage threshold.
The NCP349 provides a negative going flag (FLAG) output, which
alerts the system that a fault has occurred.
In addition, the device has ESD−protected input (15 kV Air) when
bypassed with a 1.0 mF or larger capacitor.
Features
•
•
•
•
•
•
•
•
•
•
•
•
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6
1
DFN6
MN SUFFIX
CASE 506BM
MARKING DIAGRAM
1
XX MG
G
XX = Specific Device Code
M = Date Code
G
= Pb−Free Package
Overvoltage Protection up to 28 V
On−Chip Low RDS(on) NMOS Transistor: 65 mW
Internal Charge Pump
Overvoltage Lockout (OVLO)
Undervoltage Lockout (UVLO)
Soft−Start
Alert FLAG Output
Shutdown EN Input
Compliance to IEC61000−4−2 (Level 4)
8.0 kV (Contact)
15 kV (Air)
ESD Ratings: Machine Model = B
Human Body Model = 2
DFN6 1.6x2 mm Package
This is a Pb−Free Device
PIN CONNECTIONS
IN
1
GND
2
FLAG
3
PAD1
IN
6
EN
5
OUT
4
OUT
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 11 of this data sheet.
Applications
•
•
•
•
•
Cell Phones
Camera Phones
Digital Still Cameras
Personal Digital Applications
MP3 Players
Q
© Semiconductor Components Industries, LLC, 2012
September, 2012 − Rev. 3
1
Publication Order Number:
NCP349/D
NCP349
Wall Adapter − AC/DC − USB
1 mF
NCP349
7
IN
OUT 5
1
4
IN
OUT
6
FLAG
EN
CC/CV
Charger or
System
VBat
3
BATTERY
10 k
ENABLE/
GND
Microprocessor
2
mP
0
0
Figure 1. Typical Application Circuit
7
4
INPUT
OUTPUT
5
Gate
Driver
1
VREF
Charge
Pump
EN Block
UVLO
OVLO
Control
Logic and
Timer
3
EN
FLAG
6
2
GND
Figure 2. Functional Block Diagram
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NCP349
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Function
1, 7
IN
INPUT
Description
Input Voltage Pins. These pins are connected to the Wall Adapoter (AC−DC, Vbus ..). A 1 mF low
ESR ceramic capacitor, or larger, must be connected between these pins and GND, as close as
possible to the DUT. The two IN pins must be connected together to power supply. (See PCB
recommendation for the pin7).
2
GND
POWER
Ground
3
FLAG
OUTPUT
Fault Indication Pin. This pin allows an external system to detect a fault on the IN pins. The FLAG pin
goes low when input voltage exceeds OVLO threshold or drops below UVLO threshold. Since the
FLAG pin is open drain functionality, an external pull−up resistor to VCC must be added. (Minimum
10 kW).
4, 5
OUT
OUTPUT
Output Voltage Pins. These pins follow IN pins when “no fault” is detected. The two OUT pins must
be hardwired together.
6
EN
INPUT
Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to
GND to a pull down or to a I/O pin. This pin does not have an impact on the fault detection.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Vminin
−0.3
V
Vmin
−0.3
V
Vmaxin
30
V
Maximum Voltage (All others to GND)
Vmax
7.0
V
Maximum Current (UVLO<VIN<OVLO)
Imax
2.0
A
Maximum Peak Current (t ≤ 1 ms, TA = 85°C)
Imaxpeak
4.0
A
Thermal Resistance, Junction−to−Air (Note 1)
RqJA
180
°C/W
Operating Ambient Temperature Range
TA
−40 to +85
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Minimum Voltage (IN to GND)
Minimum Voltage (All others to GND)
Maximum Voltage (IN to GND)
Junction Operating Temperature
TJ
150
°C
ESD Withstand Voltage (IEC 61000−4−2) (input only) when bypassed with 1.0 mF capacitor
Human Body Model (HBM), Model = 2 (Note 2)
Machine Model (MM) Model = B (Note 3)
Vesd
15 Air, 8.0 Contact
2000
200
kV
V
V
Moisture Sensitivity
MSL
Level 1
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The RqJA is highly dependent on the PCB heat sink area (connected to pin 7).
2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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NCP349
ELECTRICAL CHARACTERISTICS (Min/Max limits values (−40°C < TA < +85°C) and Vin = +5.0 V. Typical values are TA = +25°C,
unless otherwise noted.)
Symbol
Conditions
Min
Typ
Max
Unit
Vin
−
1.2
−
28
V
UVLO
Vin falls below UVLO threshold
from 5 V to 2.7 V
2.8
3.0
2.95
3.25
3.1
3.5
UVLOhyst
Vin rises above UVLO + UVLOhyst
30
60
90
OVLO
Vin rises above OVLO threshold
5.53
5.70
6.0
6.67
6.8
5.68
6.02
6.4
6.85
7.2
5.83
6.40
6.8
7.05
7.6
OVLOhyst
Vin falls below OVLO + OVLOhyst
30
50
50
60
100
70
90
150
100
Vin versus Vout Resistance
RDS(on)
Vin = 5.0 V, EN = GND,
Load connected to Vout
−
65
110
mW
Supply Quiescent Current
Idd
No load. EN = 5.0 V
−
70
150
mA
No load. EN = Gnd
−
140
250
mA
Characteristic
Input Voltage Range
Undervoltage Lockout Threshold (Note 4)
NCP349MN, NCP349MNAE, NCP349MNAM
NCP349MNBG, NCP349MNBK
Undervoltage Lockout Hysteresis
Overvoltage Lockout Threshold (Note 4)
NCP349MNAE
NCP349MNBG
NCP349MNBK
NCP349MN
NCP349MNAM
Overvoltage Lockout Hysteresis
NCP349MN, NCP349MNAE, NCP349MNBG
NCP349MNBK
NCP349MNAM
V
mV
V
mV
UVLO Supply Current
Idduvlo
VIN = 2.7 V
−
60
−
mA
FLAG Output Low Voltage
Volflag
1.2 V < VIN < UVLO
Sink 50 mA on/FLAG pin
−
20
400
mV
VIN > OVLO
Sink 1.0 mA on FLAG pin
−
−
400
mV
FLAGleak
FLAG level = 5.0 V
−
1.0
−
nA
EN Voltage High
Vih
−
1.2
−
−
V
EN Voltage Low
Vol
−
−
−
0.4
V
ENleak
EN = 5.0 V or GND
−
1.0
−
nA
ton
From Vin > UVLO to Vout = 0.3 V
(See Figures 3 & 7)
1.0
6.0
30
1.8
10
55
2.7
14
70
tstart
From Vout = 0.3 V to FLAG = 1.2 V
(See Figures 3 & 9)
0.4
6.0
30
1.2
10
55
2.1
14
70
toff
From Vin > OVLO to Vout < = 0.3 V
(See Figures 4 & 8)
Vin increasing from 5.0 V to 8.0 V
at 3.0 V/ms
Rload connected on Vout
−
1.5
5.0
ms
Alert Delay
tstop
From Vin > OVLO to FLAG < =
0.4 V (See Figures 4 & 10)
Vin increasing from 5.0 V to 8.0 V
at 3.0 V/ms
Rload connected on Vout
−
1.0
−
ms
Disable Time
tdis
From EN > = 1.2 V to
Vout < 0.3 V
Rload = 5.0 W
(See Figures 5 & 12)
−
1.0
5.0
ms
FLAG Leakage Current
EN Leakage Current
TIMINGS
Startup Delay
NCP349MN
NCP349MNAE
NCP349MNBG, NCP349MNBK, NCP349MNAM
FLAG Going Up Delay
NCP349MN
NCP349MNAE
NCP349MNBG, NCP349MNBK, NCP349MNAM
Output Turn Off Time
ms
ms
NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature.
4. Additional UVLO and OVLO thresholds ranging from UVLO and from OVLO can be manufactured. Contact your ON Semiconductor
representative for availability.
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NCP349
TIMING DIAGRAMS
<OVLO
UVLO
Vin
Vin
ton
Vout
Vin − (RDS(on)
0.3 V
OVLO
toff
Vout
I)
Vin − (RDS(on)
I)
0.3 V
tstart
FLAG
tstop
1.2 V
FLAG
0.4 V
Figure 3. Startup
Figure 4. Shutdown on Overvoltage Detection
1.2 V
EN
1.2 V
EN
Vout
Vin − (RDS(on)
Vin
OVLO
tdis
I)
UVLO
FLAG
0.3 V
ton + tstart
FLAG
Figure 5. Disable on EN = 1
Figure 6. FLAG Response with EN = 1
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NCP349
TYPICAL OPERATING CHARACTERISTICS
50 ms ton and tstart version
Figure 7. Startup
Vin = Ch1, Vout = Ch3
Figure 8. Output Turn Off Time
Vin = Ch1, Vout = Ch2
Figure 9. FLAG Going Up Delay
Vout = Ch3, FLAG = Ch2
Figure 10. Alert Delay
Vout = Ch1, FLAG = Ch3
Figure 11. Initial Overvoltage Delay
Vin = Ch1, Vout = Ch2, FLAG = Ch3
Figure 12. Disable Time
EN = Ch1, Vout = Ch2, FLAG = Ch3
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NCP349
TYPICAL OPERATING CHARACTERISTICS
Figure 13. Inrush Current with Cout = 100 mF,
I charge = 1 A, Output Wall Adaptor Inductance 1 mH
Figure 14. Output Short Circuit
Figure 15. Output Short Circuit (Zoom Fig. 14)
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NCP349
CONDITIONS
IN
OUT
VIN > OVLO
0 < VIN < UVLO
And/Or
VOLTAGE DETECTION
/EN = 1
Figure 16. Simplified Diagram
CONDITIONS
IN
OUT
/EN = 0
&
UVLO < VIN < OVLO
VOLTAGE DETECTION
Figure 17. Simplified Diagram
Operation
overtaking undervoltage UVLO (Figure 3). The NCP349
provides a FLAG output, which alerts the system that a fault
has occurred. A tstart additional delay, regarding available
output (Figure 3) is added between output signal rising up
and to FLAG signal rising up. FLAG pin is an open drain
output.
The NCP349 provides overvoltage protection for
positive voltage, up to 28 V. A low RDS(on) NMOSFET
protects the systems (i.e.: charger) connected on the Vout
pin, against positive overvoltage. At powerup, with EN pin
= low, the output is rising up ton soft−start after the input
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NCP349
Vout = 0
FLAG = Low
Reset Timer
Vin < UVLO or
Vin > OVLO
Vout = 0
FLAG = Low
Timer Count
OVLO > Vin > UVLO
Timer Check
T < ton
T = ton
Reset Timer
Vin < UVLO or
Vin > OVLO
Check Vin
FLAG = Low
Timer Count
UVLO < Vin < OVLO
EN = 1
EN = 0
Check EN
Vout = Open
Vin < UVLO or
Vin > OVLO
Vout = Vin
T < ton
Timer Check
T = ton
Check EN
UVLO < Vin < OVLO
EN = 1
Vout = Open
FLAG = High
Check Vin
UVLO < Vin < OVLO
EN = 0
Vout = Vin
FLAG = High
Check Vin
Vin < UVLO or
Vin > OVLO
Figure 18. State Machine
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NCP349
Undervoltage Lockout (UVLO)
ESD Tests
To ensure proper operation under any conditions, the
device has a built−in undervoltage lockout (UVLO) circuit.
During Vin positive going slope, the output remains
disconnected from input until Vin voltage is below UVLO,
plus hysteresis, nominal. The FLAG output is tied to low as
long as Vin does not reach UVLO threshold. This circuit has
a built−in hysteresis to provide noise immunity to transient
condition. Additional UVLO thresholds ranging from
UVLO
can
be
manufactured.
Contact
your
ON Semiconductor representative for availability.
The NCP349 input pin fully supports the IEC61000−4−2.
1.0 mF (minimum) must be connected between Vin and
GND, close to the device.
That means, in Air condition, Vin has a ±15 kV ESD
protected input. In Contact condition, Vin has ±8.0 kV ESD
protected input.
Please refer to Figure 19 to see the IEC 61000−4−2
electrostatic discharge waveform.
Overvoltage Lockout (OVLO)
To protect connected systems on Vout pin from
overvoltage, the device has a built−in overvoltage lockout
(OVLO) circuit. During overvoltage condition, the output
remains disabled as long as the input voltage exceeds
typical OVLO. Additional OVLO thresholds ranging from
OVLO can be manufactured. Contact your ON
Semiconductor representative for availability.
FLAG output is tied to low until Vin is higher than OVLO.
This circuit has a built−in hysteresis to provide noise
immunity to transient conditions.
FLAG Output
The NCP349 provides a FLAG output, which alerts
external systems that a fault has occurred.
This pin is tied to low as soon the OVLO threshold is
exceeded or when the Vin level is below the UVLO
threshold. When Vin level recovers normal condition,
FLAG is held high, keeping in mind that an additional tstart
delay has been added between available output and FLAG
= high. The pin is an open drain output, thus a pull up
resistor (typically 1 MW, minimum 10 kW) must be added
to Vbat. Minimum Vbat supply must be 2.5 V. The FLAG
level will always reflects Vin status, even if the device is
turned off (EN = 1).
Figure 19. Electrostatic Discharge Waveform
PCB Recommendations
The NCP349 integrates a 2 A rated NMOSFET, and the
PCB rules must be respected to properly evacuate the heat
out of the silicon. The pin 7 (exposed pad) is internally
connected to the internal NMOS Drain (Input). This
exposed pad must be used to increase heat transfer and must
be connected to Pin 1. Of course, in any case, this pad
shall be not connected to any other potential.
Theta JA curve with PCB cu thk 1.0 oz
Theta JA curve with PCB cu thk 2.0 oz
Power curve with PCB cu thk 2.0 oz
Power curve with PCB cu thk 1.0 oz
EN Input
Internal NMOS FET
The NCP349 includes an internal Low RDS(on) NMOS
FET to protect the systems, connected on OUT pin, from
positive overvoltage. Regarding electrical characteristics,
the RDS(on), during normal operation, will create low losses
on Vout pin.
As example: Rload = 8.0 W, Vin = 5.0 V
Typical RDS(on) = 65 mW, Iout = 618 mA
Vout = 8 x 0.618 = 4.95 V
200
1.75
180
1.5
160
1.25
140
1
120
0.75
100
0.5
80
60
0
NMOS losses = RDS(on) x Iout2 = 0.065 x 0.6182 = 25 mW
100
200
300
400
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500
600
Copper heat spreader area (mm^2)
Figure 20.
10
Max Power (W)
Theta JA (C/W)
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin,
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
0.25
700
NCP349
ORDERING INFORMATION
Device
Marking
NCP349MNTBG
AC
NCP349MNAETBG
AE
NCP349MNBGTBG
AG
NCP349MNBKTBG
AK
NCP349MNAMTBG
AM
Package
Shipping†
DFN6
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
SELECTION GUIDE
The NCP349 can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows:
NCP349MNxxTxG
ab c
Code
Contents
a
UVLO Typical Threshold
a: − = 2.95 V
a: A = 2.95 V
a: B = 3.25 V
b
OVLO Typical Threshold
b: E = 5.68 V
b: G = 6.02 V
b: K = 6.40 V
b: − = 6.85 V
b: M = 7.2 V
c
Tape & Reel Type
c: B = 3000
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NCP349
PACKAGE DIMENSIONS
DFN6, 1.6x2, 0.5P
CASE 506BM−01
ISSUE O
A
B
D
2X
0.10 C
2X
DETAIL A
OPTIONAL
CONSTRUCTIONS
E
TOP VIEW
ÇÇÇ
ÉÉÉ
ÇÇÇ
DETAIL B
A
(A3)
A1
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MOLD CMPD
EXPOSED Cu
0.10 C
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.20 mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L1
ÉÉ
ÉÉ
ÉÉ
PIN ONE
REFERENCE
L
A3
DETAIL B
OPTIONAL
CONSTRUCTION
0.05 C
NOTE 4
C
SIDE VIEW A1
1
MOUNTING FOOTPRINT
1.30
D2
DETAIL A
SEATING
PLANE
6X
3
L
E2
6
K
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.40
1.60 BSC
1.10
1.30
2.00 BSC
0.95
1.15
0.50 BSC
0.20
−−−
0.15
0.35
−−−
0.10
5
e
BOTTOM VIEW
6X
6X
0.43
1.15 2.30
b
0.10 C A B
0.05 C
1
NOTE 3
6X
0.36
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf . SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loca
Sales Representative
NCP349/D