NCP391 D

NCP391
Positive Overvoltage
Protection Controller with
Internal Low RON NMOS FET
The NCP391 is able to disconnect the systems from its output pin
when wrong input operating conditions are detected. The system is
positive overvoltage protected up to +28 V.
This device uses an internal NMOS and therefore, no external
device is necessary, reducing the system cost and the PCB area of the
application board.
The NCP391 is able to instantaneously disconnect the output from
the input, due to integrated Low RON Power NMOS, if the input
voltage exceeds the overvoltage threshold (OVLO) or falls below the
undervoltage threshold (UVLO).
At powerup (EN pin = low level), the Vout turns on ton time after
the Vin exceeds the undervoltage threshold.
The NCP391 provides a negative going flag (FLAG) output, which
alerts the system that a fault has occurred.
In addition, the device has ESD−protected input (15 kV Air) when
bypassed with a 1.0 mF or larger capacitor.
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MARKING
DIAGRAM
WLCSP6
FCAL SUFFIX
CASE 499BP
391LG
AYWW
WLCSP6
FCCAD SUFFIX
CASE 567JW
391DG
AYWW
XXXX
A
Y
WW
G
Features
•
•
•
•
•
•
•
•
•
•
•
•
Overvoltage Protection up to 28 V
On−Chip Low RDS(on) NMOS Transistor
Internal Charge Pump
Overvoltage Lockout (OVLO)
Undervoltage Lockout (UVLO)
Soft−Start
Alert FLAG Output
Shutdown EN Input
Compliance to IEC61000−4−2 (Level 4)
8.0 kV (Contact)
15 kV (Air)
ESD Ratings: Machine Model = B
Human Body Model = 2
WLCSP6 1.31x1.04 mm Package
This is a Pb−Free Device
PIN CONNECTIONS
IN
1
EN
6
IN
2
GND
5
OUT
3
FLAG
4
or
(Top View)
Applications
•
•
•
•
•
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
IN
A1
EN
B1
IN
A2
GND
B2
OUT
A3
FLAG
B3
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 12 of this data sheet.
Cell Phones
Camera Phones
Digital Still Cameras
Personal Digital Applications
MP3 Players
QFN−16
© Semiconductor Components Industries, LLC, 2014
May, 2014 − Rev. 2
1
Publication Order Number:
NCP391/D
NCP391
Wall Adapter − AC/DC − USB
1 mF
NCP391
IN
OUT 3
2
4
IN
FLAG
6
5
EN
GND
CC/CV
Charger or
System
1
VCC
10 k
B+
BATTERY
mP
ENABLE/
Microprocessor
0
0
Figure 1. Typical Application Circuit
1
3
INPUT
Gate
Driver
2
VREF
Charge
Pump
EN Block
UVLO
OVLO
TSD
Control
Logic and
Timer
4
EN
FLAG
6
5
GND
Figure 2. Functional Block Diagram
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2
NCP391
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Function
Description
1, 2 or
A1, A2
IN
INPUT
Input Voltage Pins. These pins are connected to the Wall Adapoter (AC−DC, Vbus ..). A 1 mF low
ESR ceramic capacitor, or larger, must be connected between these pins and GND, as close as
possible to the DUT. The two IN pins must be connected together to power supply. (See PCB recommendation for the pin7).
3 or A3
OUT
OUTPUT
Output Voltage Pins. This pin follows IN pins when “no fault” is detected.
4 or B3
FLAG
OUTPUT
Fault Indication Pin. This pin allows an external system to detect a fault on the IN pins. The FLAG pin
goes low when input voltage exceeds OVLO threshold or drops below UVLO threshold or when TSD
is exceeded. Since the FLAG pin is open drain functionality, an external pull−up resistor to VCC must
be added. (Minimum 10 kW).
5 or B2
GND
POWER
Ground
6 or B1
EN
INPUT
Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to
GND to a pull down or to a I/O pin. This pin does not have an impact on the fault detection.
MAXIMUM RATINGS
Rating
Minimum Voltage (IN to GND)
Minimum Voltage (All others to GND)
Symbol
Value
Unit
Vminin
−0.3
V
Vmin
−0.3
V
Vmaxin
30
V
Maximum Voltage (All others to GND)
Vmax
7.0
V
Maximum Current (UVLO<VIN<OVLO)
Imax
2.0
A
Maximum Peak Current (t ≤ 1 ms, TA = 85°C)
Imaxpeak
4.0
A
Thermal Resistance, Junction−to−Air (Note 1)
RqJA
130
°C/W
Maximum Voltage (IN to GND)
Operating Ambient Temperature Range
TA
−40 to +85
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Junction Operating Temperature
TJ
150
°C
ESD Withstand Voltage (IEC 61000−4−2) (input only) when bypassed with 1.0 mF capacitor
Human Body Model (HBM), Model = 2 (Note 2)
Machine Model (MM) Model = B (Note 3)
Vesd
15 Air, 8.0 Contact
2000
200
kV
V
V
Moisture Sensitivity
MSL
Level 1
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The RqJA is highly dependent on the PCB heat sink area (connected to pin 7).
2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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3
NCP391
ELECTRICAL CHARACTERISTICS − NCP391FCALT2G (Min/Max limits values (−40°C < TA < +85°C) and Vin = +5.0 V. Typical
values are TA = +25°C, unless otherwise noted.)
Characteristic
Input Voltage Range
Undervoltage Lockout Threshold (Note 4)
NCP391FCAL
Undervoltage Lockout Hysteresis
Overvoltage Lockout Threshold (Note 4)
NCP391FCAL
Overvoltage Lockout Hysteresis
Symbol
Conditions
Min
Typ
Max
Unit
Vin
−
1.2
−
28
V
UVLO
Vin falls below UVLO threshold
from 5 V to 2.7 V
2.8
2.95
3.1
UVLOhyst
Vin rises above UVLO + UVLOhyst
30
60
90
OVLO
Vin rises above OVLO threshold
7.16
7.4
7.65
50
100
150
OVLOhyst
V
V
Vin falls below OVLO + OVLOhyst
NCP391FCAL
mV
mV
Vin versus Vout Resistance
RDS(on)
Vin = 5.0 V, EN = GND,
Load connected to Vout
−
120
200
mW
Supply Quiescent Current
Idd
No load. EN = 5.0 V
−
70
150
mA
No load. EN = Gnd
−
90
170
mA
Idduvlo
VIN = 2.7 V
−
60
−
mA
Ivdss
VIN = 28 V
−
10
500
nA
Volflag
1.2 V < VIN < UVLO
Sink 50 mA on/FLAG pin
−
20
400
mV
VIN > OVLO
Sink 1.0 mA on FLAG pin
−
−
400
mV
UVLO Supply Current
MOSFET Leakage
FLAG Output Low Voltage
FLAG Leakage Current
FLAGleak
FLAG level = 5.0 V
−
1.0
−
nA
EN Voltage High
Vih
−
1.2
−
−
V
EN Voltage Low
Vol
−
−
−
0.4
V
ENleak
EN = 5.0 V or GND
−
1.0
−
nA
tSD
−
−
150
−
°C
tSDhyst
−
−
15
−
°C
ton
From Vin > UVLO to Vout = 0.3 V
(See Figures 3 & 7)
6.0
10
14
ms
FLAG Going Up Delay
tstart
From Vout = 0.3 V to FLAG = 1.2 V
(See Figures 3 & 9)
6.0
10
14
ms
Output Turn Off Time
toff
From Vin > OVLO to Vout < = 0.3 V
(See Figures 4 & 8)
Vin increasing from 5.0 V to 8.0 V
at 3.0 V/ms
Rload connected on Vout
−
1.5
5.0
ms
tstop
From Vin > OVLO to FLAG < =
0.4 V (See Figures 4 & 10)
Vin increasing from 5.0 V to 8.0 V
at 3.0 V/ms
Rload connected on Vout
−
1.0
−
ms
tdis
From EN > = 1.2 V to
Vout < 0.3 V
Rload = 5.0 W
(See Figures 5 & 12)
−
1.0
5.0
ms
EN Leakage Current
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
TIMINGS
Startup Delay
Alert Delay
Disable Time
NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature.
4. Additional UVLO and OVLO thresholds ranging from UVLO and from OVLO can be manufactured. Contact your ON Semiconductor
representative for availability.
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4
NCP391
ELECTRICAL CHARACTERISTICS − NCP391FCCADT2G (Min/Max limits values (−40°C < TA < +85°C) and Vin = +4.2 V. Typical
values are TA = +25°C, unless otherwise noted.)
Characteristic
Input Voltage Range
Undervoltage Lockout Threshold (Note 5)
Undervoltage Lockout Hysteresis
Overvoltage Lockout Threshold (Note 5)
Overvoltage Lockout Hysteresis
Symbol
Conditions
Min
Typ
Max
Unit
Vin
−
1.2
−
28
V
UVLO
Vin falls below UVLO threshold
from 4.2 V to 2.7 V
2.8
2.95
3.1
UVLOhyst
Vin rises above UVLO + UVLOhyst
30
60
90
OVLO
Vin rises above OVLO threshold
4.8
4.95
5.1
50
100
150
OVLOhyst
V
mV
V
Vin falls below OVLO + OVLOhyst
mV
Vin versus Vout Resistance
RDS(on)
Vin = 4.2 V, EN = GND,
Load connected to Vout
−
120
200
mW
Supply Quiescent Current
Idd
No load. EN = 4.2 V
−
70
150
mA
No load. EN = Gnd
−
90
170
mA
Idduvlo
VIN = 2.7 V
−
60
−
mA
Ivdss
VIN = 28 V
−
10
500
nA
Volflag
1.2 V < VIN < UVLO
Sink 50 mA on/FLAG pin
−
20
400
mV
VIN > OVLO
Sink 1.0 mA on FLAG pin
−
−
400
mV
UVLO Supply Current
MOSFET Leakage
FLAG Output Low Voltage
FLAG Leakage Current
FLAGleak
FLAG level = 4.2 V
−
1.0
−
nA
EN Voltage High
Vih
−
1.2
−
4.95
V
EN Voltage Low
Vol
−
−
−
0.4
V
ENleak
EN = 4.2 V or GND
−
1.0
−
nA
tSD
−
−
150
−
°C
tSDhyst
−
−
15
−
°C
ton
From Vin > UVLO to Vout = 0.3 V
(See Figures 3 & 7)
6.0
10
14
ms
FLAG Going Up Delay
tstart
From Vout = 0.3 V to FLAG = 1.2 V
(See Figures 3 & 9)
6.0
10
14
ms
Output Turn Off Time
toff
From Vin > OVLO to Vout < = 0.3 V
(See Figures 4 & 8)
Vin increasing from 4.2 V to 8.0 V
at 3.0 V/ms
Rload connected on Vout
−
1.5
5.0
ms
tstop
From Vin > OVLO to FLAG < =
0.4 V (See Figures 4 & 10)
Vin increasing from 4.2 V to 8.0 V
at 3.0 V/ms
Rload connected on Vout
−
1.0
−
ms
tdis
From EN > = 1.2 V to
Vout < 0.3 V
Rload = 5.0 W
(See Figures 5 & 12)
−
1.0
5.0
ms
EN Leakage Current
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
TIMINGS
Startup Delay
Alert Delay
Disable Time
NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature.
5. Additional UVLO and OVLO thresholds ranging from UVLO and from OVLO can be manufactured. Contact your ON Semiconductor
representative for availability.
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5
NCP391
TIMING DIAGRAMS
<OVLO
OVLO
UVLO
Vin
Vin
ton
Vout
Vin − (RDS(on)
0.3 V
toff
Vout
I)
Vin − (RDS(on)
I)
0.3 V
tstart
FLAG
tstop
1.2 V
FLAG
0.4 V
Figure 3. Startup
Figure 4. Shutdown on Overvoltage Detection
1.2 V
EN
1.2 V
EN
Vout
Vin − (RDS(on)
Vin
OVLO
tdis
UVLO
I)
FLAG
0.3 V
ton + tstart
FLAG
Figure 5. Disable on EN = 1
Figure 6. FLAG Response with EN = 1
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NCP391
TYPICAL OPERATING CHARACTERISTICS
50 ms ton and tstart version
Figure 7. Startup
Vin = Ch1, Vout = Ch3
Figure 8. Output Turn Off Time
Vin = Ch1, Vout = Ch2
Figure 9. FLAG Going Up Delay
Vout = Ch3, FLAG = Ch2
Figure 10. Alert Delay
Vout = Ch1, FLAG = Ch3
Figure 11. Initial Overvoltage Delay
Vin = Ch1, Vout = Ch2, FLAG = Ch3
Figure 12. Disable Time
EN = Ch1, Vout = Ch2, FLAG = Ch3
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NCP391
TYPICAL OPERATING CHARACTERISTICS
Figure 13. Inrush Current with Cout = 100 mF,
I charge = 1 A, Output Wall Adaptor Inductance 1 mH
Figure 14. Output Short Circuit
Figure 15. Output Short Circuit (Zoom Fig. 14)
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8
NCP391
CONDITIONS
IN
OUT
VIN > OVLO
0 < VIN < UVLO
And/Or
VOLTAGE DETECTION
/EN = 1
Figure 16. Simplified Diagram
CONDITIONS
IN
OUT
/EN = 0
&
UVLO < VIN < OVLO
VOLTAGE DETECTION
Figure 17. Simplified Diagram
Operation
overtaking undervoltage UVLO (Figure 3). The NCP391
provides a FLAG output, which alerts the system that a fault
has occurred. A tstart additional delay, regarding available
output (Figure 3) is added between output signal rising up
and to FLAG signal rising up. FLAG pin is an open drain
output.
The NCP391 provides overvoltage protection for
positive voltage, up to 28 V. A low RDS(on) NMOSFET
protects the systems (i.e.: charger) connected on the Vout
pin, against positive overvoltage. At powerup, with EN pin
= low, the output is rising up ton soft−start after the input
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9
NCP391
Vout = 0
FLAG = Low
Reset Timer
Vin < UVLO or
Vin > OVLO
Vout = 0
FLAG = Low
Timer Count
OVLO > Vin > UVLO
Timer Check
T < ton
T = ton
Reset Timer
Vin < UVLO or
Vin > OVLO
Check Vin
FLAG = Low
Timer Count
UVLO < Vin < OVLO
EN = 1
EN = 0
Check EN
Vout = Open
Vin < UVLO or
Vin > OVLO
Vout = Vin
T < ton
Timer Check
T = ton
Check EN
UVLO < Vin < OVLO
EN = 1
UVLO < Vin < OVLO
EN = 0
Vout = Vin
FLAG = High
Check Vin
Vout = Open
FLAG = High
Check Vin
Vin < UVLO or
Vin > OVLO
Figure 18. State Machine
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10
NCP391
NMOS losses = RDS(on) x Iout2 = 0.12 x 0.6152 = 45 mW
Undervoltage Lockout (UVLO)
To ensure proper operation under any conditions, the
device has a built−in undervoltage lockout (UVLO) circuit.
During Vin positive going slope, the output remains
disconnected from input until Vin voltage is below UVLO,
plus hysteresis, nominal. The FLAG output is tied to low as
long as Vin does not reach UVLO threshold. This circuit has
a built−in hysteresis to provide noise immunity to transient
condition. Additional UVLO thresholds ranging from
UVLO can be manufactured. Contact your ON
Semiconductor representative for availability.
ESD Tests
The NCP391 input pin fully supports the IEC61000−4−2.
1.0 mF (minimum) must be connected between Vin and
GND, close to the device.
That means, in Air condition, Vin has a "15 kV ESD
protected input. In Contact condition, Vin has "8.0 kV
ESD protected input.
Please refer to Figure 19 to see the IEC 61000−4−2
electrostatic discharge waveform.
Overvoltage Lockout (OVLO)
To protect connected systems on Vout pin from
overvoltage, the device has a built−in overvoltage lockout
(OVLO) circuit. During overvoltage condition, the output
remains disabled as long as the input voltage exceeds
typical OVLO. Additional OVLO thresholds ranging from
OVLO can be manufactured. Contact your ON
Semiconductor representative for availability.
FLAG output is tied to low until Vin is higher than OVLO.
This circuit has a built−in hysteresis to provide noise
immunity to transient conditions.
FLAG Output
The NCP391 provides a FLAG output, which alerts
external systems that a fault has occurred.
This pin is tied to low as soon the OVLO threshold is
exceeded or when the Vin level is below the UVLO
threshold. When Vin level recovers normal condition,
FLAG is held high, keeping in mind that an additional tstart
delay has been added between available output and FLAG
= high. The pin is an open drain output, thus a pull up
resistor (typically 1 MW, minimum 10 kW) must be added
to Vbat. Minimum Vbat supply must be 2.5 V. The FLAG
level will always reflects Vin status, even if the device is
turned off (EN = 1).
Figure 19. Electrostatic Discharge Waveform
PCB Recommendations
The NCP391 integrates a 2 A rated NMOSFET, and the
PCB rules must be respected to properly evacuate the heat
out of the silicon.
Theta JA curve with PCB cu thk 1.0 oz
Theta JA curve with PCB cu thk 2.0 oz
Power curve with PCB cu thk 2.0 oz
Power curve with PCB cu thk 1.0 oz
Theta JA (C/W)
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin,
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
Internal NMOSFET
The NCP391 includes an internal Low RDS(on) NMOS
FET to protect the systems, connected on OUT pin, from
positive overvoltage. Regarding electrical characteristics,
the RDS(on), during normal operation, will create low losses
on Vout pin.
As example: Rload = 8.0 W, Vin = 5.0 V
Typical RDS(on) = 120 mW, Iout = 615 mA
Vout = 8 x 0.615 = 4.926 V
200
1.75
180
1.5
160
1.25
140
1
120
0.75
100
0.5
80
60
0
100
200
300
400
500
600
Copper heat spreader area (mm^2)
Figure 20.
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11
Max Power (W)
EN Input
0.25
700
NCP391
ORDERING INFORMATION
Marking
Package
Shipping†
NCP391FCALT2G
391L
WLCSP6
(Pb−Free)
3000 / Tape & Reel
NCP391FCCADT2G
391D
WLCSP6
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
SELECTION GUIDE
The NCP391 can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows:
NCP391FCxxT1G
ab
Code
Contents
a
UVLO Typical Threshold
a: A = 2.95 V
b
OVLO Typical Threshold
b: D = 4.95 V
b: L = 7.4 V
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12
NCP391
PACKAGE DIMENSIONS
WLCSP6, 1.31x1.04
CASE 499BP
ISSUE A
ÈÈ
ÈÈ
D
PIN A1
REFERENCE
0.10 C
2X
0.10 C
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
A B
E
DIM
A
A1
A2
b
D
E
eD
eE
TOP VIEW
A2
0.10 C
A
6X
6X
A1
C
SIDE VIEW
b
SEATING
PLANE
0.40
PACKAGE
OUTLINE
0.60
eD
eE
0.05 C A B
0.03 C
RECOMMENDED
SOLDERING FOOTPRINT*
0.05 C
NOTE 3
MILLIMETERS
MIN
MAX
0.50
0.56
0.17
0.23
0.33
0.39
0.24
0.29
1.31 BSC
1.04 BSC
0.40 BSC
0.60 BSC
B
6X
0.26
A
3
2
DIMENSIONS: MILLIMETERS
1
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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13
NCP391
PACKAGE DIMENSIONS
WLCSP6, 1.31x1.04
CASE 567JW
ISSUE O
D
ÈÈ
ÈÈ
PIN A1
REFERENCE
0.10 C
2X
0.10 C
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
A B
E
DIM
A
A1
A2
b
D
E
eD
eE
TOP VIEW
A2
0.10 C
RECOMMENDED
SOLDERING FOOTPRINT*
A
6X
0.05 C
NOTE 3
6X
A1
C
SIDE VIEW
b
SEATING
PLANE
0.40
PACKAGE
OUTLINE
0.60
eD
eE
0.05 C A B
0.03 C
MILLIMETERS
MIN
MAX
0.50
0.62
0.17
0.23
0.33
0.39
0.24
0.29
1.31 BSC
1.04 BSC
0.40 BSC
0.60 BSC
B
6X
0.26
A
3
2
DIMENSIONS: MILLIMETERS
1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
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For additional information, please contact your local
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NCP391/D