Lattice USB Type-C Solution - Documentation

Lattice USB Type-C Solution
August 2015
Reference Design RD1209
Introduction
The USB Type-C receptacle, plug and cable provide a smaller, thinner and more robust alternative to existing
USB interconnect. This new solution targets use in a variety of platforms, ranging from notebooks, PCs and monitors to smartphones and tablets, where existing Standard-A and Micro-AB receptacles are deemed too large, difficult to use, or inadequately robust. The USB Type-C plug enhances ease of use by being pluggable in either
upside-up or upside-down directions and in either direction between host and devices. Determination of this hostto-device relationship is accomplished through a Configuration Channel (CC) that is connected through the cable.
These various solutions demonstrate the capabilities of the Lattice device as USB 3.1 Power Delivery and Type-C
ASSP. The solution include a DRP (dual-role port) function, hence it can be used as both DFP/Host/Source and
UFP/Device/Sink after role resolution.
One of the most important features of USB Type-C is the reversible nature of the connector and plug. This design
also provides the provision to control a Super Speed switch required for data channel alignment/orientation management. Lattice PD controller can control both the SS (Super Speed Switch) and the HS (High Speed Switch)
providing a seamless interface with Type C connector without any intervention from the main processor.
The USB PD specifications have another exciting functional extension using the Type-C connector known as
Alternate Modes. Lattice PD controller provides support for Structured VDM (Vendor Defined Messages) to handle these alternate modes like VESA Display Port over Type-C.
This document is based on Universal Serial Bus Power Delivery Specification revision 2.0 version 1.0 and Universal Serial Bus Type-C Cable and Connector Specification revision 1.1. Any references in this document to the PD
specification and Type-C specification should be understood.
Features
• Three solutions cover majority of USB Type-C Power Delivery (PD) and Cable Detect (CD) applications:
— CD/PD for charger
— CD/PD-Phy for hosts/device
— CD/PD for hosts/device
• Logical based PHY provides fast deterministic response and low power, typical solution power is 7 mW
• Standby power less than 100 uW
• Flexible 8-Bit uC policy engine enables easy modifications
• Support for fast development
— Industry proven solutions reduce design risk
— Schematics and BOMs available to minimize system design effort
• Wide range of packages to match PCB technology
— 36 WLCSP
— 48 QFN
— 36 ucBGA
— 81 ucBGA
• Ultra-small form factor, as small as 2.078 mm X 2.078 mm
• USB Type-C PHY
• USB Type-C Cable Detect (CD) support per USB Cable and Connector Specification
• USB Power Delivery (PD) support per Power Delivery Specification
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1
RD1209_1.3
Lattice USB Type-C Solution
Table 1. USB Type-C Device Table
Package, Ball Pitch,
Dimension
Solution
Typical End Application
48 QFN, 0.50 mm, 
7.00 mm x 7.00 mm
CD/PD for Charger
OPN
Charger
LIF-UC110-SG48I
CD/PD Phy for Hosts/Devices 36 WLCSP, 0.35 mm,
2.078 mm x 2.078 mm
Smartphone Tablet
LIF-UC120-SWG36I
36 ucBGA, 0.40 mm, 
2.50 mm x 2.50 mm
Smartphone Tablet
LIF-UC120-CM36I
Tablet
LIF-UC140-CM81I
CD/PD for Hosts/Devices
81 ucBGA, 0.40 mm,
4.00 mm x 4.00 mm
System Block Diagram
Figure 1 shows the system block diagram of the USB Type-C Solution.
Figure 1. Block Diagram
VBUS
Power
Control
SPI/I2C
EC/AP
USB
Type-C
CD/PD
Solution
(LIF-UC1xx)
VBUS
CC1
CC2
Type-C
SS-DATA
SS-Switch
Specifications
The design consists of the specifications described in this section.
Recommended Operating Conditions
See DS1052, Lattice USB Type-C Solution Data Sheet.
Power Supply Ramp Rates
See DS1052, Lattice USB Type-C Solution Data Sheet.
Power-on-Reset Voltage Levels
See DS1052, Lattice USB Type-C Solution Data Sheet.
ESD Performance
See DS1052, Lattice USB Type-C Solution Data Sheet.
DC Electrical Characteristics
See DS1052, Lattice USB Type-C Solution Data Sheet.
Power Supply Current
See DS1052, Lattice USB Type-C Solution Data Sheet.
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Lattice USB Type-C Solution
Absolute Maximum Ratings
See DS1052, Lattice USB Type-C Solution Data Sheet.
Signal Descriptions
Table 2. Signal Descriptions
Signal Name
Type
Description
CLK_IN
I
5 MHz Reference Clock
EC_SCL
I/O
I2C Serial Clock
EC_SDA
I/O
I2C Data
EC_INT
O
Interrupt signal from FPGA to EC
EC_CS
I
Chip select signal from EC to FPGA
VSEL1,VSEL2,VSEL3,VSEL4
I/O
Voltage selection lines for selecting output voltages
SS_SEL1,SS_SEL2,SS_SEL3, SS_SEL4
O
SS/HS Switch Control Signal
VBUS_SOURCE_EN
O
Enable Signal for VBUS Source
VBUS_SINK_EN
O
Enable Signal for VBUS Sink
VBUS_DSICHARGE_EN
O
Enable Signal for VBUS Discharge
VCC
I
1.2 V Core Supply
VCCIO
I
3.3 V/1.8 V IO Power Supply
VBUS
I
VBUS
GND
I
Ground
See DS1052, Lattice USB Type-C Solution Data Sheet for detailed signal descriptions.
Electrical Requirements and Lattice Implementation Models
Lattice CD/PD controller implements the USB Power Delivery over USB Type-C. There are many requirements
starting from successful detection to the final explicit contract. Based on the USB Type-C specification, there are
two major electrical events between attach, negotiate and explicit contract states. The following sections will show
the functional models of the approach used while implementing the Lattice CD/PD controller solution.
Cable Attach/Detach Determination
Cable attach and detach detection is the basic requirement of any Type-C port. The USB Type-C specification
defines the process that has to be followed to detect these events along with the role information to be extracted
based on the CC line voltage for a DFP and the presence of VBUS in case of a UFP.
Lattice CD/PD controller is a Dual-Role Port (DRP) hence it needs the capability to detect the presence of both the
RP/RD resistors (i.e. vRd) as well as VBUS. Apart from detecting the port partner RP/RD, the logic should also be
able to assert and de-assert its on RP and RD during the role-resolution phase.
Normal Mode Rp/Rd Functional Model
This model shows the implementation of Rp and Rd resistor based device detection method. This is just for illustration purpose and does not include the CC2 line. Under normal operation, the device is either a DFP or a UFP
based on the resistors used in the device frontend.
• DFP Detection – A DFP device exposes a Rp resistor pulled up to Vp which in this case is 3.3 V always. This is
done by driving ‘1’ on the “Rp_ENB_CC1” signal.
• UFP Detection – A UFP shall expose Rd resistor pulled down to Gnd in order to get detected by a DFP. This is
done by driving ‘0’ on the “Rd_ENB_CC1” signal which acts as a pseudo ground when driven low.
• Once the DFP detects the UFP via the specification defined vRd on the CC line, it will turn ON its VBUS
_SOURCE.
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Lattice USB Type-C Solution
• The UFP will then detect the presence of this voltage on the VBUS line and complete the connection.
Figure 2. RP and RD Functional Model for a DRP-DRP
Host/DRP
Rp36K
RP_ENB_CC1
VCONN 5 V
CC1
ADC_IN
CC_BMC_DATA
SPDT
After this is third party DRP device
Normal Operation
USB Type-C
Compatible DRP
Rd 5.1 K
Enb_VCONN_CC1
LIF-UC1xx
Note: Only one section is active at a time. If you act as DFP, the upper section is active.
Otherwise, the section below is active.
Below is UFP implementation
Vp 3.3 V
VCONN 5 V
ADC_IN
Rp 36 K
CC_BMC_DATA
CC1
RD_ENB_CC1
SPDT
Rd 5.1 K
This DRP supplies
Vp if we are UFP
Enb_VCONN_CC1
Optionally disable
via VCONN
Disable Clamp
VLT
510K
Dead Battery Detection/Unpowered Port Detection
The Power Delivery specification provides a mechanism for a USB Device to provide power to a USB Host under
the circumstances where the USB Host:
• Has a Dead Battery that requires charging
• Has lost its power source
• Does not have a power source
• Does not want to provide power
The USB Peripheral primarily acts as a USB Device that may also provide power to the USB Host if the correct
detection is carried out. Lattice CD/PD controller has a provision to be able to expose pull down resistor on both CC
lines so that it is detected as a Device with no power by the port partner and hence will be provide VBUS to get the
power for device operation.
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Lattice USB Type-C Solution
Dead Battery/Lattice Device OFF Functional Model
Figure 3. Clamp Voltage Based Device Detection for a Dead Battery/Unpowered Device
DFP Section Not
Required Under Dead Battery
Host/DRP
Rp36K
VCONN 5 V
RP_ENB_CC1
CC1
After this is third party
DRP device
Rp and Rd Functional Model for a DRP-DRP
Dead Battery Rd Detection
USB Type-C
Compatible
Third Party DRP
ADC_IN
CC_BMC_DATA
Rd 5.1 K
Enb_VCONN_CC1
LIF-UC1xx
Below is UFP implementation
Vp 3.3 V
VCONN 5 V
ADC_IN
Rp 36 K
CC_BMC_DATA
CC1
RD_ENB_CC1
SPDT
Rd 5.1 K
This DRP supplies
Vp if we are UFP
Enb_VCONN_CC1
Optionally disable
via VCONN
Disable Clamp
VLT
510K
This 510K along with FET acts as a clamp
showing ~1 V on CC line making our DFP
detectable even if iCE40 is powered OFF.
This model is an illustration of how the design handles the use case when the Lattice device is unable to turn ON
and thus cannot drive the Gates of the FET operating in the switching mode. If the DRP has no power, it should
expose the Rd resistors in order to be detected by the far end DRP as a Sink. To achieve this, the design has a
PFET with the Gate pulled to GND line. This enables enough vClamp (~1 V) on the CC line, which leads to the
detection of LIF-UC1xx as a Sink DRP and the port partner (source) starts providing the VBUS. This situation will
continue until the point when LIF-UC1xx PD frontend is turned ON. After the LIF-UC1xx frontend is configured and
the detection FSM is controlling the Rp and Rd enable signals, the Disable Clamp signal will disable the clamp and
FSM will expose either the Rp or Rd resistors depending on which DRP mode it is in. Alternately the clamp can be
disconnected automatically using the VCONN supply but this will require proper sequencing of VCONN.
The time taken for the LIF-UC1xx to start operating is system dependent based on the Embedded Controller and
other Power Management ICs.
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Lattice USB Type-C Solution
Functional Descriptions
This section describes the function of each sub-block in the USB Type-C solution. See RD1210, Lattice USB Type-C
Solution Design Document for more details.
Figure 4. Functional Block Diagram
3.3 V/BMC Interface
USB Type-C Power Delivery Solution
VBUS
Power
Control
VCCIO 3.3 V/1.8 V
VCCore 1.2 V
VBUS 5 V
510 k
510 k
ADC3
PD Manager
Detect and Control Link
VBUS_DETECT
+
–
FB
ADC1
DPM
+
–
CC1
VCONN 5 V
EC_SCL
EC_SDA
EC_RST
Policy
Engine
ADC2
+
–
CC1_RX
+
–
PD PHY
CC2_RX
+
–
TX_DATA
RX_DATA
EC_INT_N
EC/AP
CC2
VCCore
FB
TX_ENABLE
Register
Interface
TYPE-C RECEPTACLE
FB
CC1_TX
CC1_TX GND
CC2_TX
CC2_TX GND
Protocol
Layer
LIF-UC1xx
SS_SEL0
SS_SEL1
SS_SEL1
SS_SEL2
SS_Switch
SS-DATA
GND
*Lattice FPGAs can be programmed through SPI Interface
CD or Cable Detect
This is the electrical/analog frontend. It controls the SS switch select signals as well as detects which CC line is
connected by the cable with the port partner, and based on this information, it changes the SS switch select lines.
This module also includes the Dual-Role Port FSM as described in the USB Type-C specification.
Sigma Delta ADC for Voltage Detection
The Type-C cable detection can be further divided into two parts:
• DFP/Source side CC vRd detection for ‘Attach’ and vOpen detection for ‘Detach’
• UFP/Sink side presence of VBUS for ‘Attach’ and absence for ‘Detach’
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Lattice USB Type-C Solution
Table 3. DFP and UFP Behaviors by State
State
DFP Behavior
Nothing attached
UFP attached
Powered cable/No UFP attached
Powered cable/UFP attached
Debug Accessory Mode attached
Audio Adapter Accessory Mode attached
UFP Behavior
– Sense CC pins for attach
– Do not apply VBUS or VCONN
– Sense CC for orientation
– Sense CC for detach
– Apply VBUS or VCONN
– Sense CC for attach
– Do not apply VBUS or VCONN
– Sense CC for orientation
– Sense CC for detach
– Apply VBUS or VCONN
– Sense CC for detach
– Reconfigure for debug
– Sense CC for detach
– Reconfigure for analog audio
– Sense VBUS for attach
– Sense CC pins for orientation
– Sense loss of VBUS for detach
– Sense VBUS for attach
– Sense CC for orientation
– Sense loss of VBUS for detach
– N/A
– N/A
Table 4. USB Type-C DFP Connection States
CC1
CC2
Open
Open
Rd
Open
Open
Rd
State
vOpen
Nothing attached
vRd
UFP attached
vRa
Powered cable / No UFP attached
Open
Ra
Ra
Open
Rd
Ra
Ra
Rd
vRd +
vRa
Powered cable / UFP attached
Rd
Rd
vRd CC1
and CC2
Debug accessory mode attached (can be supported)
Ra
Ra
vRa CC1
and CC2
Audio Adapter Accessory Mode attached
CC Line vRd and vOpen Detection
This design uses RD1066, Simple Sigma-Delta to implement an ADC. This reference design provides two different
topologies for ADC implementation, viz Direct topology and Network topology.
The ADC topologies used for vRd detection in the three solutions (CD/PD for Charger, CD/PD PHY for
host/devices and CD/PD for host/devices) are different. See DS1052, Lattice USB Type-C Solution Data Sheet for
details.
Table 5. CC Voltages on DFP Side - 3.0 A @ 5 V
Minimum Voltage
Maximum Voltage
Threshold
Powered cable / adapter (vRa)
0.00 V
0.75 V
0.80 V
UFP (vRd)
0.85 V
2.45 V
2.60 V
No connection (vOpen)
2.75 V
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Lattice USB Type-C Solution
Table 6. Voltage on UFP CC pins (Multiple DFP Current Advertisements)
Detection
vRa
vRd-Connect
Minimum Voltage
Maximum Voltage
Threshold
–0.25 V
0.15 V
0.2 V
0.25 V
2.04 V
vRd-USB
0.25 V
0.61 V
0.66 V
vRd-1.5
0.70 V
1.16 V
1.23 V
vRd-3.0
1.31 V
2.04 V
VBUS Detection
On the UFP/Sink side, the first event after cable connection is the presence of VBUS on the Type-C receptacle. It is
mandatory for a Device/Sink/UFP to detect this voltage and enter the ‘Attached UFP’ state as mentioned in the
DRP FSM of the USB Type-C specification.
SS Switch Selection
One of the most exciting feature of the USB Type-C is the reversible nature of the plug. But this new feature calls for
the need of detecting the orientation which is successfully done by Configuration Channel (CC1 and CC2) vRd
detection. But once this orientation is detected, the device should be able to re-arrange its Data Channels to proper
alignment in order to send the data across to the Port-Partner. This is done by means of external Super-Speed
Switches (SS Switch) for the SSTX and the SSRX data lanes of USB3.1.
This design provides flexible number of IOs that can be used to perform the SS switch lane selection by controlling
the select lines available on the switches. The design can provide up to four IOs for the select lines.
It is important to note that not all USB Type-C devices need the SS switches. This requirement is only for the USB
communications capable devices. Devices such as USB Chargers and devices with Captive Cables may not need
these cross bar switches since the orientation is either fixed due to captive nature or no requirement of USB data
communication.
DRP FSM
This design is implemented in order to achieve the full functionality defined in the USB Type-C. Based on the specification, there are three type of ports, UFP (Device type), DFP (Host type) and the DRP (can be both UFP and a
DFP).
PD PHY
This module has three internal modules:
• Register Interface
• Tx with 4B5B and BMC encoding
• Rx with BMC decoding, start/stop detection and 4B5B decoder
PD PHY Manager
This module handles the USB PD implementation and responsible for transmission and reception of Power Delivery messages. The Figure 6 depicts the architecture of Power Delivery Manager.
8
Lattice USB Type-C Solution
Figure 5. Architecture of Power Delivery Manager
Construct
Msg
Caps
Mem
ProtoTx
PHY
Ctrl
Wishbone
I2C
PHY
DPM
Rx
Decoder
ProtoRx
Policy
Engine
Hard
Reset
I2C Slave Controller
I2C Slave controller is used as the communication channel between Application Processor (AP) and Lattice PD.
Power Delivery process is interrupt driven.
Device Policy Manager (DPM)
The Device Policy Manager is responsible for applying local policies based on the fixed I2C Register Set or inputs
from the AP, to the Power Delivery negotiation process.
Capabilities Memory
This is a pre-initialized memory which has the default Port Source and Sink Power capabilities (PDO) defined. In
addition, it has space to hold the received port partners Source and Sink Power capabilities (PDO) for the AP to
access.
Policy Engine (PE)
The Policy Engine interprets the Device Policy Manager’s input in order to implement Policy for a given Port and
directs the Protocol Layer to send appropriate messages.
Protocol Layer
The Protocol Layer is divided into three modules:
• Proto Tx
• Proto Rx
• Hard reset
Proto Tx
Proto Tx module is responsible for transmission of a Power Delivery packet.
9
Lattice USB Type-C Solution
Proto Rx
Proto Rx module is responsible for reception of a Power Delivery Packet.
Hard Reset
Hard Reset module handles the hard reset condition if received by the port partner or if initiated by own port. On a
hard reset condition, this module makes sure that all power levels and protocol layer is reset to default before any
further PD communication.
PHY Control
The PHY control module is used as a communication interface between the Protocol Layer and the PHY
EC/AP Interface to Lattice Device
The registers provided in Lattice device may be accessed through most of the serial interfaces based on custom
Requirements. By default Lattice solution offers ready access via I2C serial interface. See the Appendix A. Register
Settings section for register descriptions.
VBUS Power Control
VBUS Power control logic generates control signals to control VBUS source, VBUS Sink and VBUS discharge FETs.
For application like charger or multiple PD power profile, Lattice solution generates necessary control signals to
select the multiple voltages.
10
Lattice USB Type-C Solution
Lattice Type-C Solutions
CD PD for Charger
Figure 6. USB CD/PD Charger (Captive or Non-captive Cable) Block Diagram
CD/PD
Manager
CD/PD
PHY
Type C Connector
LIF-UC110
CC
VBUS VBUS
Power
Control
CD = Cable Detect
PD = Power Delivery
Lattice CD PD Charger is targeted for USB Type-C based chargers. This solution comes with the following:
• Cable Detect (CD) Logic
• PD PHY
• PD PHY Manager
• VBUS Power control signals for VBUS Source, discharge and selecting multiple PD Profiles
CD PD PHY for Hosts/Devices
Figure 7. CD/PD PHY for Hosts/Devices Block Diagram
Tx1/Rx1
Tx/Rx
SS
Switch
SS Sel
Tx2/Rx2
Type-C Connector
USB
Chipset
LIF-UC120
AP
SPI
IRPT
PD
Manager
CD/PD
PHY+
VBUS Power Control
CD = Cable Detect
PD = Power Delivery
11
CC
VBUS
Power
Control
VBUS
Lattice USB Type-C Solution
This solution is targeted for applications in smartphones and tablets. This solution comes with the following:
• Cable Detect (CD) Logic
• PD PHY
This solution does not include PD manger in Lattice FPGA, external AP has PD manger which controls the CD/PD
PHY. AP has to control the SS switch and VBUS power related signals.
CD PD for Hosts/Devices
Figure 8. USB CD/PD for Hosts/Devices Block Diagram
Tx1/Rx1
USB
Chipset
SS
Switch
Tx/Rx
Tx2/Rx2
Type-C Connector
Video
LIF-UC140
SPI
IRPT
AP/
CPU/
EC
CD/PD
Manager
CD/PD
PHY
VBUS Power Control
CC
VBUS
Power
Control
VBUS
CD = Cable Detect
PD = Power Delivery
This solution is targeted for mobile applications in notebooks, smartphones and tablets. This solution comes with
the following:
• Cable Detect (CD) Logic
• PD PHY
• PD PHY Manager
• VDM Support
• Power Role and Data Role Swap
• Enter Billboard Mode signal for EC/AP
• SS Switch Control signals
• VBUS Power control signals for VBUS Source, Sink and discharge
12
Lattice USB Type-C Solution
Test Results
This section describes the results of a few tests performed using Rev A of Lattice USB 3.1 Type-C Development
Kit. The full test report can be found in Lattice USB 3.1-Type C Test Report document. For access to this document, please contact your Lattice Sales Representative.
Dual Role Port (DRP)
A dual role port is capable of both sourcing and sinking and can become either a DFP or a UFP after role resolution
with the partner port.
Pass Criteria
The tDRP parameter represents the overall period for a single cycle during which the port must be exposed as both
a DFP and a UFP.
Figure 9. DRP Timing as Per Specification
dcDFP.DRP tDRP
tDRPTransition
Expose as DFP
Expose as UFP
tDRPTransition
tDRP
Table 7. DRP Timing Parameters
tDRP
dcDFP.DRP
tDRPTransition
tDRPHold
Minimum
Maximum
Description
50 ms
100 ms
The period a DRP shall complete a DFP to UFP and back
advertisement
30%
70%
The percent of time that a DRP shall advertise DFP during
tDRP
0 ms
1 ms
The time a DRP shall complete transitions between DFP
and UFP roles during role resolution
100 ms
150 ms
Wait time associated with the Attach.DFP.DRPWait state
Results
Figure 11 shows the CC line on the Lattice demo board when no port partner is connected. Note the difference in
the duty cycle implying that RP is exposed for a longer period then RD, thus providing a provision of applying a preferred DFP implementation.
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Lattice USB Type-C Solution
Figure 10. RP/RD Exposure on CC Line
Trying as
DFP
Trying as
UFP
Cable Attach
Pass Criteria:
As soon as a port partner (UFP) is connected, DRP should go to the attached state and the CC line voltage is seen
for default USB current rating as per below specification table. Note that based on the RP resistor mounted on the
demo board, the voltage level on the CC line falls between any of the three different ranges as mentioned in the
USB TYPE-C specification.
Table 8. CC Voltages on DFP Side – Default USB
Minimum Voltage
Maximum Voltage
Threshold
Powered cable / adapter (vRa)
0.00 V
0.15 V
0.20 V
UFP (vRd)
0.25 V
1.50 V
1.60 V
No connection (vOpen)
1.65 V
Results
A voltage of ~1 V is observed on the connected CC line.
14
Lattice USB Type-C Solution
Figure 11. CC Voltage on DFP Side
Attached
BMC Started
Cable Detach
Pass Criteria
As soon as the port partner is disconnected, the Lattice DRP should go back to the role resolution state where it restarts the RP/RD alternate exposure on the CC line.
Results
Figure 13 shows the DRP entering the role-resolution state after a detach condition.
15
Lattice USB Type-C Solution
Figure 12. Detach Event Leading to DFP to UFP and Back Advertisement (Role Resolution)
Detached
DRP
Cable Flip
Pass Criteria
The cable detect logic should successfully change the orientation by detecting the used CC line. If the Cable attach
test is passed then the BMC transmission should follow on the connected Configuration Channel.
Result
Figure 15 shows the BMC data changing from CC1 to CC2 based on the orientation detection done by the cable
detect logic.
16
Lattice USB Type-C Solution
Figure 13. BMC on CC1 Shows No Cable Flip
BMC
CC1
CC2
Figure 14. BMC on CC2 Shows Cable Flip
CC1
BMC
CC2
17
Lattice USB Type-C Solution
PD Contract
Pass Criteria
After cable detection, a power negotiation should lead to successful contract between port partners and hence
enter into explicit power contract. Based on the design loaded on the demo board, different capabilities will be
advertised by the DFP. In general, Lattice demo solutions hold the USB PD Fixed Supply Object i.e. Profile 0 at 5 V
as the default capability.
Results
Figure 16 shows an “ACCEPT” message been sent followed by a “PS_RDY” after tSnkTransition (35ms).
Figure 15. CC Line Showing BMC Messages and a Test Point Showing Successful PD Contract
BMC
PD contact is established
Eye Mask
Below test results are obtained using GRL software/masks on the Agilent DSA91304A. The eye masks are defined
in the USB PD USB Type-C specification.
Pass Criteria
Transmitter (Near end) and Receiver (Far end) eye mask test should pass with GRL software. Since the USB Type-C
has three different RP pull up resistor values that can change the CC line characteristics. Hence it is mandatory that
the Eye Diagrams are captured and passed for all three RP values (36K, 12K and 4.7K.)
Results
Near End Eye Diagram (Tx) With Rp = 36 K
Eye diagrams tests are done with the resistor values of 45 Ω, 100 Ω and 2nF for the transmitter.
18
Lattice USB Type-C Solution
Figure 16. Near End Eye Diagram for ‘1’ with Rp = 36 KΩ
BMC One Bit Eye Diagram
Figure 17. Near End Eye Diagram for ‘0’ with Rp=36 KΩ
BMC Zero Bit Eye Diagram
Far End Eye Diagram (Rx) With Rp = 36 K
Eye diagrams tests are done with the resistor values of 45 Ω, 100 Ω and 2nF for the transmitter.
19
Lattice USB Type-C Solution
Figure 18. Far End Eye Diagram for ‘1’ with Rp=36 KΩ
BMC One Bit Eye Diagram
Figure 19. Far End Eye Diagram for ‘0’ with Rp=36 KΩ
BMC Zero Bit Eye Diagram
20
Lattice USB Type-C Solution
Test Results Summary
Table 9. Lattice CD/PD Test Cases and Results
S:No
Test
Pass
1
Dual Role Port
Yes
2
Cable Attach
Yes
3
Cable Detach
Yes
4
Cable Flip
Yes
5
Rise/Fall time
Yes
6
Dead Battery
Yes
7
Capability Exchange
Yes
8
PD Contract (Fixed PDO 0)
Yes
9
Multiple PD Contract
Yes
10
Reject Message
Yes
11
Capability Retrying
Yes
12
Hard Reset
Yes
13
Eye Mask for TX/RX
Yes
14
Power Role Swap
Yes
15
Data Role Swap
Yes
16
Structured VDM Discovery Identity
Yes
17
Structured VDM Entry/Exit
Yes
Functional Simulation Results
Figure 20. Functional Simulation Waveform
21
Comments
Lattice USB Type-C Solution
ActiveHDL Console Results
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Asserting Reset
De-asserting Reset
Applying 2 kHz sawtooth input
---------------- Initial PD contract ---------------###################### PD
######################
@
14788620ps
>>
********** Fixed supply match**************
@
16085600ps
3. SINK :
@
17245220ps
4. SOURCE
********** Source Capability Match **************
********** Source Comparison done **************
@
17248420ps
>>
@
17248420ps
5. SOURCE
@
18285600ps
6. SINK :
###################### EC
SOURCE : SEND CAPABILITIES <<
SEND REQUEST
: REQUEST RECEIVED
SOURCE : EVALUATE REQUEST <<
: SEND ACCEPT
ACCEPT RECEIVED
######################
Power Transition Request Interrupt Received @UFP
Clear Interrupt Registers @UFP
Power Transition Request Interrupt Received @DFP
Clear Interrupt Registers @DFP
Set Power Transition Request Done in CTRL REG 1 @DFP
Set Power Transition Request Done in CTRL REG 1 @UFP
###################### PD
@
@
@
######################
18983620ps
18983620ps
20004000ps
###################### EC
>> SOURCE: POWER SUPPLY ADJUSTMENT <<
7. SOURCE : SEND PS_RDY
8. SINK : PS_RDY RECEIVED
######################
PD contract established @UFP
Clear Interrupt Registers @UFP
PD contract established @DFP
Clear Interrupt Registers @DFP
---------------- New source PDO count update ---------------###################### EC
######################
Read PDO count @DFP
PDO count @DFP = x46000001
@
31087620ps
###################### PD
Write Source PDO count update 'x86_00_00_09' @DFP
>> SOURCE : SEND CAPABILITIES <<
######################
********** Fixed supply match**************
@
32649600ps
3. SINK : SEND REQUEST
@
33810020ps
4. SOURCE : REQUEST RECEIVED
********** Source Capability Match **************
********** Source Comparison done **************
@
33813220ps
>> SOURCE : EVALUATE REQUEST <<
22
Lattice USB Type-C Solution
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@
@
33813220ps
34847200ps
5. SOURCE : SEND ACCEPT
6. SINK : ACCEPT RECEIVED
###################### EC
######################
Power Transition Request Interrupt Received @UFP
Clear Interrupt Registers @UFP
Power Transition Request Interrupt Received @DFP
Clear Interrupt Registers @DFP
Set Power Transition Request Done in CTRL REG 1 @DFP
Set Power Transition Request Done in CTRL REG 1 @UFP
###################### PD
@
@
@
######################
35548220ps
35548220ps
36568800ps
>> SOURCE: POWER SUPPLY ADJUSTMENT <<
7. SOURCE : SEND PS_RDY
8. SINK : PS_RDY RECEIVED
---------------- New Sink PDO number update ---------------###################### EC
######################
Read PDO count @UFP
PDO count @UFP = x46000001
Write new Sink PDO number 'x46_00_00_0B' @UFP
###################### PD
######################
********** Fixed supply match**************
********** Source Capability Match **************
********** Source Comparison done **************
@
42470820ps
>> SOURCE : EVALUATE REQUEST <<
@
42470820ps
5. SOURCE : SEND ACCEPT
@
43504800ps
6. SINK : ACCEPT RECEIVED
###################### EC
######################
Power Transition Request Interrupt Received @DFP
Clear Interrupt Registers @DFP
Power Transition Request Interrupt Received @UFP
Clear Interrupt Registers @UFP
Set Power Transition Request Done in CTRL REG 1 @DFP
Set Power Transition Request Done in CTRL REG 1 @UFP
###################### PD
@
@
@
44037020ps
44037020ps
45056800ps
######################
>> SOURCE : POWER SUPPLY ADJUSTMENT <<
7. SOURCE : SEND PS_RDY
8. SINK : PS_RDY RECEIVED
23
Lattice USB Type-C Solution
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.
Revision History
Date
Version
August 2015
1.3
Change Summary
Updated the Features section.
— Removed 81 caBGA package.
— Updated Table 1, USB Type-C Device Table. 
Revised heading to Package, Ball Pitch, Dimension and data.
Removed the 81 BGA, 0.8 mm, 8 mm x 8 mm package.
Updated the Lattice Type-C Solutions section. Revised the following diagrams:
— Figure 6, USB CD/PD Charger (Captive or Non-captive Cable) Block
Diagram.
— Figure 7, CD/PD PHY for Host/Devices Block Diagram.
— Figure 8, USB CD/PD for Hosts/Devices Block Diagram.
June 2015
1.2
Updated for Universal Serial Bus Type-C Cable and Connector Specification revision 1.1
General update – removed version number references in specifications.
Updated Introduction section. Added paragraph on specifications.
Updated Features section. Removed specification revision numbers.
Updated Functional Descriptions section. The following subsections are
revised:
— CC line vRd and vOpen Detection
— VBUS Detection
— SS Switch Selection
— DRP FSM
— PD PHY
— I2C Slave Controller
— Device Policy Manager (DPM)
— Policy Engine (PE)
— Proto Tx
— Proto Rx
— Hard Reset. Removed reference to USB PD specification.
Updated Technical Support Assistance section.
March 2015
1.1
Updated CD or Cable Detect section.
— Revised Table 4, USB Type-C DFP Connection States.
— Revised Table 6, Voltage on UFP CC pins (Multiple DFP Current
Advertisements).
Updated Cable Attach/Detach Determination section.
— Revised Figure 2, RP and RD Functional Model for a DRP-DRP.
Changed 1M to 510K.
Updated Dead Battery Detection/Unpowered Port Detection section.
— Revised Figure 3, Clamp Voltage Based Device Detection for a Dead
Battery/Unpowered Device.
Updated CD PD for Charger section.
— Revised heading to Figure 7, USB CD/PD Charger (Captive or Noncaptive Cable) Block Diagram.
Updated CD PD PHY for Hosts/Devices section.
— Revised Figure 8, CD/PD PHY for Hosts/Devices Block Diagram.
— Updated solution description.
February 2015
1.0
Initial release.
24
Lattice USB Type-C Solution
Appendix A. Register Settings
I2C Serial Interface
The registers provided in a Lattice device may be accessed through most of the serial interfaces based on custom
requirements. By default, the Lattice solution offers ready access via I2C serial interface.
The Lattice device is a bus slave. The I2C is employed to write and read data into registers. There are two signals
associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional
line used for sending and receiving data to/from the interface. Both the lines must be connected to 3.3 V through an
external pull-up resistor. When the bus is free, both the lines are high.
For detailed descriptions of all I2C Registers, Refer to the Lattice CC/PD Register Reference Guide. For access to
this document, please contact your Lattice Sales Representative.
I2C Operation
• Write Slave address = 7’b100_0001 + 1’b0 (8’h82)
• Read Slave address = 7’b100_0001 + 1’b1 (8’h83)
Slave address [7:1]
R/W [0]
I 2C Slave address [7:0]
Example
I2C Write Operation
1. Master issues a START condition.
2. Master sends Write Slave address.
3. Slave issues ACK to master if address matches.
4. Master sends the address the data to be written to.
5. Slave issues ACK after receiving the address.
6. Master sends data to slave, byte-wise and slave issues a ACK for each byte written.
7. Master stops the operation by issuing a STOP condition after slave’s ACK.
Start
Write Slave Address
Write Data 2
ACK
ACK
Register
Address
…..
ACK
Write Data N
I2C Read Operation
1. Master issues a START condition.
2. Master sends Write Slave address.
3. Slave issues ACK to master if address matches.
4. Master sends address to be read from.
5. Slave issues ACK to master.
25
Write Data 1
ACK
ACK
STOP
Lattice USB Type-C Solution
6. Master issues a repeated START condition.
7. Master sends Read Slave address.
8. Slave sends ACK to master if address matches.
9. Master receives data, byte wise and issues a ACK for each received byte.
10.Master stops the operation by issuing a NACK after the last byte, follow by a STOP condition.
Start
Write Slave
Address
Read Data 1
ACK
ACK
Register
Address
Read Data 2
ACK
ACK
From Master
Restart
…..
Read Slave Address
Read Data N
ACK
NACK
STOP
From Slave
I2C Register Map
Below is the mapping of registers that will be accessed by the EC.
Figure 21. I2C Register Map
No
Object
Address
1
Control Register 0
8’h00
2
Control Register 1
8’h01
3
Status Register 0
8’h02
4
Status Register 1
8’h03
5
Interrupt Register 0
8’h06
6
Interrupt Register 1
8’h07
7
Status Register 2
8’h0C
Control Register 0 (8’h00)
Table 10. Control Register 0 (8’h00)
7
6
5
4
3
2
1
0
Name
Bit
Get Sink
Caps
Get Source
Caps
PR Swap
Request
DR Swap
Request
Hard Reset
Request
VDM Start
Alt Mode
VDM Exit
Alt Mode
VDM Enter
Mode
Default
0
0
0
0
0
0
0
0
Access
W
W
W
W
W
W
W
W
Get Sink Caps
Get the port partner sink capabilities and update in the partner port sink capabilities register.
Get Source Caps
Get the port partner source capabilities and update in the partner port source capabilities register.
PR Swap Request
Request the partner port for a Port Role Swap, if attached partner port is a Dual-Role port (swap between PD
Source and Sink roles).
26
Lattice USB Type-C Solution
DR Swap Request
Request the partner for a Data Role swap (swap between DFP and UFP).
Hard Reset Request
If EC wants to reset the device after some config changes, then hard reset is required to reset the port partner.
VDM Start Alt Mode
Used only when operating as a DFP. Start Structured VDM messaging sequence to enter Alternate Port Mode. The
DFP SVID register must be loaded with the SVID to be checked for before this bit is set.
VDM Exit Alt Mode
Used only when operating as a DFP. When in Alternate Port mode, exit Alt mode and switch to USB configuration.
VDM Enter Mode
Used only when operating as a DFP. Must be set once the EC reads the modes and loads the VDM configuration
register.
Control Register 1 (8’h01)
Table 11. Control Register 1 (8’h01)
Bit
Name
7
Mode Num
[2]
6
Mode Num
[1]
5
Mode Num
[0]
4
Enter x2DP
3
VDM Enter
Bill Board
2
1
0
VDM send
Attention
POWER
TXN REQ
DONE
VDM CONFIG
Default
0
0
0
0
0
0
0
0
Access
W
W
W
W
W
W
W
W
Mode Num [2:0]
Once Modes received interrupt is generated, EC should read all the modes received and once decision is made on
which mode to enter into, the corresponding mode number must be loaded here before asserting the Enter Mode
bit of Control Register 0
Enter x2DP
Used when operating as DFP_D. When set to ‘1’ by EC, PD controller will use 2-lane DP configuration. If reset to ‘0’
PD will use 4-lane DP configuration for the partner UFP_D device. Must be written after reading Status Register
0[bit-0] to ensure that UFP_D supports 2-lane modes.
• 1 – to configure partner UFP_D with 2 lane pin assignment
• 0 – to configure partner UFP_D with 4 lane mode only
VDM Enter Bill Board
Used when operating as DFP. When set by the EC, the device will connect to Billboard.
VDM Send Attention
Used when operating as UFP. When set an attention command is sent to the attached DFP. EC must update the
VDM status register before updating this bit.
POWER TXN REQ DONE
Set this bit once the power supply is adjusted to negotiated output.
VDM CONFIG
Set this bit once the VDM UFP configuration register is loaded with the correct pin configuration for Alternate mode.
Setting this bit will initiate a VDM configuration message.
27
Lattice USB Type-C Solution
Status Register 0 (8’h02)
This register reflects the status of the PD manager.
Table 12. Status Register 0 (8’h02)
Bit
6
5
PROLE
DROLE
Valid PD
Contract
Alt Mode
Reserved
Default
0
0
0
0
Access
R
R
R
R
Name
7
4
3
2
1
0
Reserved
Reserved
x2DP
Available
0
0
0
0
R
R
R
R
PROLE
Indicates the present port role
• 0 – Sink
• 1 – Source
DROLE
Indicates the present data role.
• 0 – UFP
• 1 – DFP
Valid PD Contract
Indicates a presence of a valid PD contract between the attached port partners.
• 0 – No valid PD contract
• 1 – Valid PD contract exists
Alt Mode
Indicates if the port partners are operating in Alternate mode or USB mode.
• 0 – USB mode
• 1 – Alt mode
BIST Test Data Mode
Entered BIST Test Data Mode.
BIST Carrier Mode 2
Entered BIST Carrier Mode 2.
x2DP Available
Indicates the availability of 2-lane DP modes from partner UFP_D device. EC must read this register after the VDM
Attention received interrupt is asserted.
28
Lattice USB Type-C Solution
Status Register 1(8’h03)
This status register contains the error flags. On the event of interrupt and ‘Error’ bit of the Interrupt request register
is set, status register 1 should be set to know the source of error.
Table 13. Status Register 1(8’h03)
Bit
Name
7
6
5
4
3
2
1
0
Caps
Mismatch
Reserved
Reserved
Reserved
Reserved
Reserved
Swap Status
Default
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Swap Status
Indicates a ACCEPT/WAIT/REJECT message was received for the corresponding SWAP request made.
• 00 – NA
• 01 – ACCEPT received
• 10 – WAIT received
• 11 – REJECT received
Caps Mismatch
A Capability Mismatch occurs when the Sink cannot satisfy its power requirements from the capabilities offered by
the Source.
Status Register 2 (8’h0C)
Table 14. Status Register 2 x0C
Bit
Name
Default
Access
7
Reserved
0
Reserved
CC Line
0
R
CC Line: Indicates which CC line is connected:
— 1’b0 – CC1 is connected
— 1’b1 – CC2 is connected
6
[5:4]
Description
UFP POWER
01
R
UFP POWER: Indicates the Type-C current advertisement by the port partner DFP:
— 2’b01 – Standard USB
— 2’b10 – 1.5A
— 2’b11 – 3A
3
DFP CONNECTION
0
R
Set when a DFP port partner is connected.
2
UFP CONNECTION
0
R
Set when a UFP port partner is connected.
1
Cable Attach
0
R
Set when a Type-C cable connection is detected.
0
Cable Detach
0
R
Set when the Type-C cable connection is detached.
29
Lattice USB Type-C Solution
Interrupt Request Register 0 (8’h06)
Every bit of the Interrupt Request Register is capable of generating an interrupt. The bit which is set will be cleared
on a write to this register by the EC.
Table 15. Interrupt Request Register 0 (8’h06)
Bit
7
6
5
4
3
2
1
0
PD Contract
Current
Rating
Update
Power
Transition
Request
Vconn Swap
Request
Received
PR Swap
Request
Received
DR Swap
Request
Received
Cable Attach
Cable
Detach
Name
Default
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PD Contract
Will be set when a PD contract has been established once a USB connection is detected. Cleared on a write to this
register by EC.
Current Rating Update
Will be set when there is a new current advertisement from the DFP by increasing the CC line voltage as given in
the Type-C specification.
Power Transition Request
Will be set when there is a PD manager wants the EC to transition the power supply from one level to another during the PD process with a port partner. The EC will have to read the ‘Power Transition Request’ registers to know
the requested power levels, once this bit is set. Cleared on a write to this register by EC.
Vconn Swap Request Received
Set when the Vconn swap request received. Cleared on a write to this register by EC.
PR Swap Request Received
Set when the attached port partner requests for a port role swap. Cleared on a write to this register by EC.
• PD manager sends a wait command for swap request received and then waits for EC to decide.
— If EC wants to accept the PR swap request,
— Set the PR_SWAP OK bit of Control register 2 (0x0B), then
— Set the PR swap request bit of control register 0 to 1.
— If EC wants to reject the PR swap requests received in future,
— Set the PR_SWAP REJECT bit of Control Register 2 (0x0B)
DR Swap request received
Set when the attached port partner requests for a data role swap. Cleared on a write to this register by EC.
• Same as PR swap request
Cable Attach
Set when a USB cable connection is detected. Cleared on a write to this register by EC.
Cable Detach
Set when the USB cable connection is detached. Cleared on a write to this register by EC.
30
Lattice USB Type-C Solution
Interrupt Request Register 1 (8’h07)
Every bit of the Interrupt Request Register is capable of generating an interrupt. The bit which is set will be cleared
on a write to this register by the EC.
Table 16. Interrupt Request Register 1 (8’h07)
Bit
Name
7
6
5
Swap
Status
Updated
Hard
Reset
Received
BIST
Mode
Entered
4
3
Alt Mode
Entered
Billboard
Mode
Entered
2
1
0
ALT Mode
Exit Req
VDM
Attention
Received
VDM
Modes
Received
Default
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Swap Status Updated
Will be set once the ACCEPT/WAIT/REJECT message was received for the corresponding SWAP request made.
Read the status register 1 to know the swap result. Cleared on a write to this register by EC.
Hard Reset Received
Will be set once the device receives a hard reset. Cleared on a write to this register by EC.
BIST Mode Entered
Will be set once the device enters into BIST mode. Cleared on a write to this register by EC.
Alt Mode Entered
Will be set once the Display port alternate mode has been entered successfully. Cleared on a write to this register
by EC.
Billboard Mode Entered
Will be set on the event of a Display port SID mismatch or the DP sink responded with a NACK for Enter mode
command. Cleared on a write to this register by EC.
VDM Modes Received
Used when operating as a DFP.EC should read the VDM modes register to decide upon the supported modes for a
specific SVID. If no mode matches, then EC should set VDM Enter Bill Board mode bit in Control Register 1, else
load the VDM register and set VDM Enter Mode bit in Control register 0.
VDM Attention Received
Used when operating as a DFP. EC should read the status register once this interrupt has been generated to know
the status of the attached UFP.
31