KAD5512P ® Data Sheet March 4, 2009 Low Power 12-Bit, 250/210/170/125MSPS ADC The KAD5512P is the low-power member of the KAD5512 family of 12-bit analog-to-digital converters. Designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. The KAD5512P is part of a pin-compatible portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging from 125MSPS to 500MSPS. A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of various parameters such as gain and offset. FN6807.2 Features • Pin-Compatible with the KAD5512HP Family, Operating at Half the Power • Programmable Gain, Offset and Skew Control • 1.3GHz Analog Input Bandwidth • 60fs Clock Jitter • Over-Range Indicator • Selectable Clock Divider: ÷1, ÷2 or ÷4 • Clock Phase Selection • Nap and Sleep Modes Digital output data is presented in selectable LVDS or CMOS formats. The KAD5512P is available in 72- and 48-contact QFN packages with an exposed paddle. Operating from a 1.8V supply, performance is specified over the full industrial temperature range (-40°C to +85°C). • Two’s Complement, Gray Code or Binary Data Format Key Specifications • Pb-Free (RoHS Compliant) • SNR = 66.1dBFS for fIN = 105MHz (-1dBFS) • Single-Supply 1.8V Operation • Power Amplifier Linearization • Total Power Consumption - 267/219mW @ 250/125MSPS (SDR Mode) - 234/189mW @ 250/125MSPS (DDR Mode) • Radar and Satellite Antenna Array Processing • Broadband Communications • High-Performance Data Acquisition OVDD CLKDIV • Programmable Built-in Test Patterns Applications • SFDR = 87dBc for fIN = 105MHz (-1dBFS) AVDD • SDR/DDR LVDS-Compatible or LVCMOS Outputs • Communications Test Equipment • WiMAX and Microwave Receivers CLKP CLKOUTP CLOCK GENERATION CLKN CLKOUTN D[11:0]P 12-BIT 250 MSPS ADC VINN NAPSLP 1.25V + – AVSS VCM SPI CONTROL CSB SCLK SDIO SDO SHA 1 MODEL RESOLUTION SPEED (MSPS) DIGITAL ERROR CORRECTION D[11:0]N KAD5514P-25 14 250 ORP KAD5514P-21 14 210 LVDS/CMOS DRIVERS KAD5514P-17 14 170 OUTFMT KAD5514P-12 14 125 KAD5512P-50 12 500 KAD5512P-25, KAD5512HP-25 12 250 KAD5512P-21, KAD5512HP-21 12 210 KAD5512P-17, KAD5512HP-17 12 170 KAD5512P-12, KAD5512HP-12 12 125 KAD5510P-50 10 500 ORN OUTMODE OVSS VINP Pin-Compatible Family CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. KAD5512P Ordering Information PART NUMBER PART MARKING SPEED (MSPS) TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # KAD5512P-25Q72 (Note 2) KAD5512P-25 Q72EP-I 250 -40 to +85 72 Ld QFN L72.10X10D KAD5512P-21Q72 (Note 2) KAD5512P-21 Q72EP-I 210 -40 to +85 72 Ld QFN L72.10X10D KAD5512P-17Q72 (Note 2) KAD5512P-17 Q72EP-I 170 -40 to +85 72 Ld QFN L72.10X10D KAD5512P-12Q72 (Note 2) KAD5512P-12 Q72EP-I 125 -40 to +85 72 Ld QFN L72.10X10D KAD5512P-25Q48 (Note 1) KAD5512P-25 Q48EP-I 250 -40 to +85 48 Ld QFN L48.7X7E KAD5512P-21Q48 (Note 1) KAD5512P-21 Q48EP-I 210 -40 to +85 48 Ld QFN L48.7X7E KAD5512P-17Q48 (Note 1) KAD5512P-17 Q48EP-I 170 -40 to +85 48 Ld QFN L48.7X7E KAD5512P-12Q48 (Note 1) KAD5512P-12 Q48EP-I 125 -40 to +85 48 Ld QFN L48.7X7E NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN6807.2 March 4, 2009 KAD5512P Table of Contents Serial Peripheral Interface ........................................... 22 Absolute Maximum Ratings ......................................... 4 Thermal Information...................................................... 4 Electrical Specifications ............................................... 4 Digital Specifications .................................................... 6 Timing Diagrams ........................................................... 7 Switching Specifications .............................................. 7 Pinout/Package Information......................................... 9 SPI Physical Interface................................................ SPI Configuration....................................................... Device Information ..................................................... Indexed Device Configuration/Control ....................... Global Device Configuration/Control.......................... Device Test ................................................................ SPI Memory Map ....................................................... 22 22 23 23 24 25 26 Equivalent Circuits ....................................................... 27 Layout Considerations................................................. 28 Typical Performance Curves ........................................ 13 Split Ground and Power Planes................................. Clock Input Considerations ........................................ Exposed Paddle......................................................... Bypass and Filtering .................................................. LVDS Outputs ............................................................ LVCMOS Outputs ...................................................... Unused Inputs............................................................ Theory of Operation ...................................................... 16 Definitions ..................................................................... 29 Pin Descriptions - 72QFN........................................... Pinout ......................................................................... Pin Descriptions - 48QFN........................................... Pinout ......................................................................... 9 10 11 12 Functional Description ................................................. 16 Power-On Calibration .................................................. 16 User-Initiated Reset ..................................................... 17 Analog Input ................................................................ 17 Clock Input .................................................................. 18 Jitter ............................................................................. 19 Voltage Reference....................................................... 19 Digital Outputs ............................................................. 19 Over Range Indicator .................................................. 19 Power Dissipation ........................................................ 19 Nap/Sleep.................................................................... 19 Data Format ................................................................ 20 3 28 28 28 28 28 28 28 Revision History ........................................................... 30 Package Outline Drawings........................................... 31 L48.7x7E.................................................................... 31 L72.10x10D................................................................ 32 FN6807.2 March 4, 2009 KAD5512P Absolute Maximum Ratings Thermal Information AVDD to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V AVSS to OVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V Analog Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Logic Inputs to OVSS. . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Thermal Resistance (Typical, Note 3) θJA (°C/W) 48 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 72 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). KAD5512P-25 PARAMETER SYMBOL CONDITIONS KAD5512P-21 KAD5512P-17 KAD5512P-12 MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS 1.40 1.47 1.54 1.40 1.47 1.54 1.40 1.47 1.54 1.40 1.47 1.54 DC SPECIFICATIONS (Note 4) Analog Input Full-Scale Analog Input Range VFS Differential Input Resistance RIN Differential 1000 1000 1000 1000 Ω Input Capacitance CIN Differential 1.8 1.8 1.8 1.8 pF Full Scale Range Temp. Drift AVTC Full Temp 90 90 90 90 ppm/°C Input Offset Voltage VOS Gain Error -10 EG Common-Mode Output Voltage ±2 10 -10 ±0.6 VCM 435 535 ±2 10 -10 ±0.6 635 435 535 ±2 10 -10 ±0.6 635 435 535 ±2 10 mV ±0.6 635 435 535 VP-P % 635 mV Clock Inputs Inputs Common Mode Voltage 0.9 0.9 0.9 0.9 V CLKP,CLKN Input Swing 1.8 1.8 1.8 1.8 V Power Requirements 1.8V Analog Supply Voltage AVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V 1.8V Digital Supply Voltage OVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V 1.8V Analog Supply Current IAVDD 90 96 83 89 77 82 69 74 mA 1.8V Digital Supply Current (SDR) (Note 4) I 62 56 60 54 58 52 56 mA 1.8V Digital Supply Current (DDR) (Note 4) I OVDD 3mA LVDS 58 OVDD 3mA LVDS 39 4 38 36 35 mA FN6807.2 March 4, 2009 KAD5512P Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued) KAD5512P-25 PARAMETER Power Supply Rejection Ratio SYMBOL CONDITIONS MIN TYP PSRR 30MHz, 200mVP-P signal on AVDD -36 KAD5512P-21 MAX MIN TYP KAD5512P-17 MAX MIN -36 TYP KAD5512P-12 MAX MIN -36 TYP MAX UNITS -36 dB Total Power Dissipation Normal Mode (SDR) PD 3mA LVDS 267 286 252 271 237 Normal Mode (DDR) PD 3mA LVDS 234 Nap Mode PD 84 95 80 91 78 88 74 84 mW Sleep Mode PD 15 20 14 19 13 19 13 19 mW 219 253 219 204 235 189 mW mW AC SPECIFICATIONS (Note 5) Differential Nonlinearity DNL -0.8 ±0.3 0.8 -0.8 ±0.3 0.8 -0.8 ±0.3 0.8 -0.8 ±0.3 0.8 LSB Integral Nonlinearity INL -2.0 ±0.8 2.0 -2.0 ±1.1 2.0 -2.0 ±1.1 2.0 -2.5 ±1.4 2.5 LSB 40 MSPS Minimum Conversion Rate (Note 6) fS MIN Maximum Conversion Rate fS MAX Signal-to-Noise Ratio Signal-to-Noise and Distortion Effective Number of Bits SNR 40 250 fIN = 10MHz fIN = 105MHz SINAD 210 66.1 64.0 66.1 40 170 66.6 64.5 66.6 125 66.9 65.0 66.9 65.2 MSPS 67.1 dBFS 67.1 dBFS fIN = 190MHz 65.9 66.3 66.7 66.8 dBFS fIN = 364MHz 65.4 65.7 66.1 66.1 dBFS fIN = 695MHz 63.8 64.2 64.4 64.1 dBFS fIN = 995MHz 62.6 62.4 62.7 62.4 dBFS fIN = 10MHz 65.3 65.6 66.8 66.3 dBFS 66.3 dBFS fIN = 105MHz ENOB 40 63.3 65.3 63.8 65.6 64.3 65.8 64.3 fIN = 190MHz 64.6 65.2 65.5 65.6 dBFS fIN = 364MHz 63.9 64.3 64.7 64.1 dBFS fIN = 695MHz 56.9 57.2 57.9 57.4 dBFS fIN = 995MHz 49.6 44.9 48.3 49.3 dBFS fIN = 10MHz 10.6 10.6 10.6 10.7 Bits 10.7 Bits fIN = 105MHz 10.3 10.6 10.4 10.6 10.5 10.6 10.5 fIN = 190MHz 10.4 10.5 10.6 10.6 Bits fIN = 364MHz 10.3 10.4 10.5 10.4 Bits fIN = 695MHz 9.2 9.2 9.3 9.2 Bits fIN = 995MHz 7.9 7.2 7.7 7.9 Bits 5 FN6807.2 March 4, 2009 KAD5512P Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued) KAD5512P-25 PARAMETER Spurious-Free Dynamic Range SYMBOL SFDR CONDITIONS MIN TYP fIN = 10MHz fIN = 105MHz KAD5512P-21 MAX MIN 83.0 70 TYP KAD5512P-17 MAX MIN 81.4 87 70 86.2 TYP KAD5512P-12 MAX MIN 78.8 70 84.4 70 TYP MAX UNITS 79.6 dBc 86 dBc fIN = 190MHz 79.4 80.5 81.8 82.0 dBc fIN = 364MHz 76.1 76.1 78.2 71.8 dBc fIN = 695MHz 60.6 61.4 61.6 61.6 dBc fIN = 995MHz 50.7 46.4 49.2 50.3 dBc fIN = 70MHz -85.7 -92.1 -94.5 -95.1 dBFS fIN = 170MHz -97.1 -87.1 -91.6 -85.7 dBFS Intermodulation Distortion IMD Word Error Rate WER 10-12 10-12 10-12 10-12 Full Power Bandwidth FPBW 1.3 1.3 1.3 1.3 GHz NOTES: 4. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output. 5. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to “Power-On Calibration” on page 16 and “User-Initiated Reset” on page 17 for more details. 6. The DLL Range setting must be changed for low speed operation. See “Serial Peripheral Interface” on page 22 for more detail. Digital Specifications PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0 1 10 µA -25 -12 -5 µA INPUTS Input Current High (SDIO,RESETN) IIH VIN = 1.8V Input Current Low (SDIO,RESETN) IIL VIN = 0V Input Voltage High (SDIO, RESETN) VIH Input Voltage Low (SDIO, RESETN) VIL Input Current High (OUTMODE, NAPSLP, CLKDIV, OUTFMT) (Note 9) IIH 15 Input Current Low (OUTMODE, NAPSLP, CLKDIV, OUTFMT) IIL -40 Input Capacitance CDI 1.17 V .63 V 25 40 µA 25 -15 µA 3 pF 620 mVP-P LVDS OUTPUTS Differential Output Voltage Output Offset Voltage VT 3mA Mode VOS 3mA Mode 950 965 980 mV Output Rise Time tR 500 ps Output Fall Time tF 500 ps OVDD - 0.1 V CMOS OUTPUTS Voltage Output High VOH IOH = -500µA Voltage Output Low VOL IOL = 1mA OVDD - 0.3 0.1 0.3 V Output Rise Time tR 1.8 ns Output Fall Time tF 1.4 ns 6 FN6807.2 March 4, 2009 KAD5512P Timing Diagrams SAMPLE N SAMPLE N INP INP INN INN tA tA CLKN CLKP CLKN CLKP tCPD LATENCY = L CYCLES tCPD CLKOUTN CLKOUTP LATENCY = L CYCLES CLKOUTN CLKOUTP tDC tDC tPD D[10/8/6/4/2/0]P ODD BITS N-L D[10/8/6/4/2/0]N EVEN BITS ODD BITS EVEN BITS ODD BITS EVEN BITS N-L + 1 N-L + 1 N-L + 2 N-L + 2 N-L EVEN BITS N tPD D[11/0]P D[11/0]N DATA N-L FIGURE 1A. DDR DATA N-L + 1 DATA N FIGURE 1B. SDR FIGURE 1. LVDS TIMING DIAGRAMS SAMPLE N SAMPLE N INP INP INN INN tA tA CLKN CLKP CLKN CLKP tCPD LATENCY = L CYCLES LATENCY = L CYCLES tCPD CLKOUT CLKOUT tDC tDC tPD ODD BITS N-L D[10/8/6/4/2/0] EVEN BITS ODD BITS N-L N-L + 1 EVEN BITS ODD BITS EVEN BITS N-L + 1 N-L + 2 N-L + 2 tPD EVEN BITS N DATA N-L D[11/0] FIGURE 2A. DDR DATA N DATA N-L + 1 FIGURE 2B. SDR FIGURE 2. CMOS TIMING DIAGRAM Switching Specifications PARAMETER CONDITION SYMBOL MIN TYP MAX UNITS ADC OUTPUT Aperture Delay tA 375 ps RMS Aperture Jitter jA 60 fs Output Clock to Data Propagation Delay, LVDS Mode (Note 10) Output Clock to Data Propagation Delay, CMOS Mode (Note 10) 7 DDR Rising Edge tDC -260 -50 120 ps DDR Falling Edge tDC -160 10 230 ps SDR Falling Edge tDC -260 -40 230 ps DDR Rising Edge tDC -220 -10 200 ps DDR Falling Edge tDC -310 -90 110 ps SDR Falling Edge tDC -310 -50 200 ps FN6807.2 March 4, 2009 KAD5512P Switching Specifications (Continued) PARAMETER CONDITION SYMBOL MIN TYP MAX UNITS Latency (Pipeline Delay) L 7.5 cycles Over Voltage Recovery tOVR 1 cycles SPI INTERFACE (Notes 7, 8) SCLK Period Write Operation t CLK 64 ns Read Operation tCLK 264 ns SCLK Duty Cycle (tHI/tCLK or tLO/tCLK) Read or Write SCLK↑ to CSB↓ Setup Time Read or Write tS -4 ns SCLK↑ to CSB↑ Hold Time Read or Write tH -12 ns SCLK↑ to Data Setup Time Read or Write tDS -4 ns SCLK↑ to Data Hold Time Read or Write tDH -12 ns 25 50 75 % NOTES: 7. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled proportionally for lower sample rates. 8. The SPI may operate asynchronously with respect to the ADC sample clock. 9. The Tri-Level Inputs internal switching thresholds are approximately .43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending on desired function. 10. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most applications. Contact factory for more info if needed. 8 FN6807.2 March 4, 2009 KAD5512P Pinout/Package Information Pin Descriptions - 72QFN PIN NUMBER LVDS [LVCMOS] NAME LVDS [LVCMOS] FUNCTION 1, 6, 12, 19, 24, 71 AVDD 1.8V Analog Supply 2-5, 13, 14, 17, 18, 28-31 DNC Do Not Connect 7, 8, 11, 72 AVSS Analog Ground 9, 10 VINN, VINP 15 VCM 16 CLKDIV Tri-Level Clock Divider Control 20, 21 CLKP, CLKN Clock Input True, Complement 22 OUTMODE Tri-Level Output Mode Control (LVDS, LVCMOS) 23 NAPSLP Tri-Level Power Control (Nap, Sleep modes) 25 RESETN Power On Reset (Active Low, see page 17) 26, 45, 55, 65 OVSS Output Ground 27, 36, 56 OVDD 1.8V Output Supply 32, 33 D0N, D0P [NC, D0] LVDS Bit 0 (LSB) Output Complement, True [NC, LVCMOS Bit 0] 34, 35 D1N, D1P [NC, D1] LVDS Bit 1 Output Complement, True [NC, LVCMOS Bit 1] 37, 38 D2N, D2P [NC, D2] LVDS Bit 2 Output Complement, True [NC, LVCMOS Bit 2] 39, 40 D3N, D3P [NC, D3] LVDS Bit 3 Output Complement, True [NC, LVCMOS Bit 3] 41, 42 D4N, D4P [NC, D4] LVDS Bit 4 Output Complement, True [NC, LVCMOS Bit 4] 43, 44 D5N, D5P [NC, D5] LVDS Bit 5 Output Complement, True [NC, LVCMOS Bit 5] 46 RLVDS LVDS Bias Resistor (connect to OVSS with a 10kΩ, 1% resistor) 47, 48 CLKOUTN, CLKOUTP [NC, CLKOUT] LVDS Clock Output Complement, True [NC, LVCMOS CLKOUT] 49, 50 D6N, D6P [NC, D6] LVDS Bit 6 Output Complement, True [NC, LVCMOS Bit 6] 51, 52 D7N, D7P [NC, D7] LVDS Bit 7 Output Complement, True [NC, LVCMOS Bit 7] 53, 54 D8N, D8P [NC, D8] LVDS Bit 8 Output Complement, True [NC, LVCMOS Bit 8] 57, 58 D9N, D9P [NC, D9] LVDS Bit 9 Output Complement, True [NC, LVCMOS Bit 9] 59, 60 D10N, D10P [NC, D10] LVDS Bit 10 Output Complement, True [NC, LVCMOS Bit 10] 61, 62 D11N, D11P [NC, D11] LVDS Bit 11(MSB) Output Complement, True [NC, LVCMOS Bit 11] 63, 64 ORN, ORP [NC, OR] LVDS Over Range Complement, True [NC, LVCMOS Over Range] 66 SDO SPI Serial Data Output (4.7kΩ pull-up to OVDD is required) 67 CSB SPI Chip Select (active low) 68 SCLK SPI Clock 69 SDIO SPI Serial Data Input/Output 70 OUTFMT Exposed Paddle AVSS Analog Input Negative, Positive Common Mode Output Tri-Level Output Data Format Control (Two’s Comp., Gray Code, Offset Binary) Analog Ground NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection). 9 FN6807.2 March 4, 2009 KAD5512P Pinout AVSS AVDD OUTFMT SDIO SCLK CSB SDO OVSS ORP ORN D11P D11N D10P D10N D9P D9N OVDD OVSS KAD5512P (72 LD QFN) TOP VIEW 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVSS 7 48 CLKOUTP AVSS 8 47 CLKOUTN VINN 9 46 RLVDS VINP 10 45 OVSS AVSS 11 44 D5P AVDD 12 43 D5N DNC 13 42 D4P DNC 14 41 D4N VCM 15 40 D3P CLKDIV 16 39 D3N DNC 17 38 D2P DNC 18 37 D2N 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 OVDD 49 D6N D1P 6 D1N AVDD D0P 50 D6P D0N 5 DNC DNC DNC 51 D7N DNC 4 DNC DNC OVDD 52 D7P OVSS 3 RESETN DNC AVDD 53 D8N NAPSLP 2 OUTMODE DNC CLKN 54 D8P CLKP 1 AVDD AVDD FIGURE 3. PIN CONFIGURATION 10 FN6807.2 March 4, 2009 KAD5512P Pin Descriptions - 48QFN PIN NUMBER LVDS [LVCMOS] NAME LVDS [LVCMOS] FUNCTION 1, 9, 13, 17, 47 AVDD 1.8V Analog Supply 2-4, 11, 21, 22 DNC Do Not Connect 5, 8, 12, 48 AVSS Analog Ground 6, 7 VINN, VINP 10 VCM 14, 15 CLKP, CLKN 16 NAPSLP Tri-Level Power Control (Nap, Sleep modes) 18 RESETN Power On Reset (Active Low, see page 17) 19, 29, 42 OVSS Output Ground 20, 37 OVDD 1.8V Output Supply 23, 24 D0N, D0P [NC, D0] LVDS Bit 0 (LSB) Output Complement, True [NC, LVCMOS Bit 0] 25, 26 D1N, D1P [NC, D1] LVDS Bit 1 Output Complement, True [NC, LVCMOS Bit 1] 27, 28 D2N, D2P [NC, D2] LVDS Bit 2 Output Complement, True [NC, LVCMOS Bit 2] 30 RLVDS LVDS Bias Resistor (connect to OVSS with a 10kΩ, 1% resistor) 31, 32 CLKOUTN, CLKOUTP [NC, CLKOUT] LVDS Clock Output Complement, True [NC, LVCMOS CLKOUT] 33, 34 D3N, D3P [NC, D3] LVDS Bit 3 Output Complement, True [NC, LVCMOS Bit 3] 35, 36 D4N, D4P [NC, D4] LVDS Bit 4 Output Complement, True [NC, LVCMOS Bit 4] 38, 39 D5N, D5P [NC, D5] LVDS Bit 5 Output Complement, True [NC, LVCMOS Bit 5] 40, 41 ORN, ORP [NC, OR] 43 SDO SPI Serial Data Output (4.7kΩ pull-up to OVDD is required) 44 CSB SPI Chip Select (active low) 45 SCLK SPI Clock 46 SDIO SPI Serial Data Input/Output Exposed Paddle AVSS Analog Ground Analog Input Negative, Positive Common Mode Output Clock Input True, Complement LVDS Over Range Complement, True [NC, LVCMOS Over Range] NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection). 11 FN6807.2 March 4, 2009 KAD5512P Pinout AVSS AVDD SDIO SCLK CSB SDO OVSS ORP ORN D5P D5N OVDD KAD5512P (48 LD QFN) TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 AVSS 5 32 CLKOUTP VINN 6 31 CLKOUTN VINP 7 30 RLVDS AVSS 8 29 OVSS AVDD 9 28 D2P VCM 10 27 D2N DNC 11 26 D1P AVSS 12 25 D1N 13 14 15 16 17 18 19 20 21 22 23 24 D0P 33 D3N D0N 4 DNC DNC DNC 34 D3P OVDD 3 OVSS DNC RESETN 35 D4N AVDD 2 NAPSLP DNC CLKN 36 D4P CLKP 1 AVDD AVDD FIGURE 4. PIN CONFIGURATION 12 FN6807.2 March 4, 2009 KAD5512P Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate (per speed grade). -50 85 HD2 AND HD3 MAGNITUDE (dBc) SNR (dBFS) AND SFDR (dBc) 90 SFDR @ 125MSPS 80 75 SNR @ 125MSPS 70 65 60 SNR @ 250MSPS 55 SFDR @ 250MSPS -55 -60 0 200M 400M 600M 800M HD2 @ 250MSPS -70 -75 -80 -85 HD3 @ 125MSPS -90 -95 -100 50 HD2 @ 125MSPS -65 1G HD3 @ 250MSPS 0 200M FIGURE 5. SNR AND SFDR vs fIN -30 SNR AND SFDR HD2 & HD3 MAGNITUDE -20 90 SFDRFS (dBFS) 70 60 50 SNRFS (dBFS) 40 30 SFDR (dBc) 20 SNR (dBc) 10 0 -60 -50 -40 -20 -50 -60 -70 -10 HD2 (dBFS) -90 -100 -120 -60 0 HD3 (dBc) -80 HD3 (dBFS) -50 HD2 AND HD3 MAGNITUDE (dBc) SNR (dBFS) AND SFDR (dBc) SFDR 85 80 75 SNR 65 70 100 130 160 190 220 SAMPLE RATE (MSPS) FIGURE 9. SNR AND SFDR vs fSAMPLE 13 -30 -20 -10 0 FIGURE 8. HD2 AND HD3 vs AIN 95 60 40 -40 INPUT AMPLITUDE (dBFS) FIGURE 7. SNR AND SFDR vs AIN 70 1G HD2 (dBc) INPUT AMPLITUDE (dBFS) 90 800M -40 -110 -30 600M FIGURE 6. HD2 AND HD3 vs fIN 100 80 400M INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) 250 -60 -70 HD3 -80 -90 -100 HD2 -110 -120 40 70 100 130 160 190 220 250 SAMPLE RATE (MSPS) FIGURE 10. HD2 AND HD3 vs fSAMPLE FN6807.2 March 4, 2009 KAD5512P Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued) 300 1.5 250 1.0 200 0.5 DNL (LSBs) TOTAL POWER (mW) SDR 150 DDR 0 100 -0.5 50 -1.0 0 40 70 100 130 160 190 220 -1.5 250 0 512 1024 1536 SAMPLE RATE (MSPS) 1.5 3072 3584 4096 SNR (dBFS) & SFDR (dBc) 90 1.0 0.5 0 -0.5 -1.0 85 SFDR 80 75 70 65 SNR 60 55 -1.5 0 512 1024 1536 2048 2560 3072 3584 50 300 4096 400 CODE 500 600 700 800 INPUT COMMON MODE (mV) FIGURE 13. INTEGRAL NONLINEARITY FIGURE 14. SNR AND SFDR vs VCM 270000 0 AIN = -1.0dBFS SNR = 66.0dBFS SFDR = 82.5dBc SINAD = 65.9dBFS 240000 -20 AMPLITUDE (dBFS) 210000 NUMBER OF HITS 2560 FIGURE 12. DIFFERENTIAL NONLINEARITY FIGURE 11. POWER vs fSAMPLE IN 3mA LVDS MODE INL (LSBs) 2048 CODE 180000 150000 120000 90000 -40 -60 -80 60000 -100 30000 0 2050 2051 2052 2053 2054 2055 2056 CODE FIGURE 15. NOISE HISTOGRAM 14 2057 2058 -120 0 20 40 60 80 100 120 FREQUENCY (MHz) FIGURE 16. SINGLE-TONE SPECTRUM @ 10MHz FN6807.2 March 4, 2009 KAD5512P Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued) 0 0 AIN = -1.0dBFS SNR = 66.0dBFS SFDR = 86.5dBc SINAD = 65.9dBFS AIN = -1.0dBFS SNR = 65.7dBFS SFDR = 79.2dBc SINAD = 65.4dBFS -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -20 -40 -60 -80 -40 -60 -80 -100 -100 -120 0 -120 20 40 60 80 100 120 0 20 40 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 120 0 AIN = -1.0dBFS SNR = 64.4dBFS SFDR = 68.8dBc SINAD = 62.6dBFS -20 -40 -60 -80 AIN = -1.0dBFS SNR = 61.6dBFS SFDR = 49.8dBc SINAD = 49.8dBFS -40 -60 -80 -100 -100 0 20 40 60 80 100 -120 0 120 20 40 60 80 100 120 FREQUENCY (MHz) FREQUENCY (MHz) FIGURE 19. SINGLE-TONE SPECTRUM @ 495MHz FIGURE 20. SINGLE-TONE SPECTRUM @ 995MHz 0 0 IMD = -85.7dBFS IMD = -97.1dBFS -20 AMPLITUDE (dBFS) -20 AMPLITUDE (dBFS) 100 FIGURE 18. SINGLE-TONE SPECTRUM @ 190MHz 0 -40 -60 -80 -40 -60 -80 -100 -100 -120 80 FREQUENCY (MHz) FREQUENCY (MHz) FIGURE 17. SINGLE-TONE SPECTRUM @ 105MHz -120 60 0 20 40 60 80 100 FREQUENCY (MHz) FIGURE 21. TWO-TONE SPECTRUM @ 70MHz 15 120 -120 0 20 40 60 80 100 120 FREQUENCY (MHz) FIGURE 22. TWO-TONE SPECTRUM @ 170MHz FN6807.2 March 4, 2009 KAD5512P Theory of Operation A user-initiated reset can subsequently be invoked in the event that the previously mentioned conditions cannot be met at power-up. Functional Description The KAD5512P is based upon a 12-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 23). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. Decisions made during the successive approximation operations determine the digital code for each input value. The converter pipeline requires six samples to produce a result. Digital error correction is also applied, resulting in a total latency of seven and one half clock cycles. This is evident to the user as a time lag between the start of a conversion and the data being available on the digital outputs. Power-On Calibration The ADC performs a self-calibration at start-up. An internal power-on-reset (POR) circuit detects the supply voltage ramps and initiates the calibration when the analog and digital supply voltages are above a threshold. The following conditions must be adhered to for the power-on calibration to execute successfully: • A frequency-stable conversion clock must be applied to the CLKP/CLKN pins • DNC pins (especially 3, 4 and 18) must not be pulled up or down The SDO pin requires an external 4.7kΩ pull-up to OVDD. If the SDO pin is pulled low externally during power-up, calibration will not be executed properly. After the power supply has stabilized, the internal POR releases RESETN and an internal pull-up pulls it high, which starts the calibration sequence. If a subsequent user-initiated reset is required, the RESETN pin should be connected to an open-drain driver with a drive strength of less than 0.5mA. The calibration sequence is initiated on the rising edge of RESETN, as shown in Figure 24. The over-range output (OR) is set high once RESETN is pulled low, and remains in that state until calibration is complete. The OR output returns to normal operation at that time, so it is important that the analog input be within the converter’s full-scale range to observe the transition. If the input is in an over-range condition, the OR pin will stay high, and it will not be possible to detect the end of the calibration cycle. While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is set low. Normal operation of the output clock resumes at the next input clock edge (CLKP/CLKN) after RESETN is deasserted. At 250MSPS the nominal calibration time is 200ms, while the maximum calibration time is 550ms. • SDO (pin 66) must be high • RESETN (pin 25) must begin low • SPI communications must not be attempted CLOCK GENERATION INP SHA INN 1.25V + – 2.5-BIT FLASH 6-STAGE 1.5-BIT/STAGE 3-STAGE 1-BIT/STAGE 3-BIT FLASH DIGITAL ERROR CORRECTION LVDS/LVCMOS OUTPUTS FIGURE 23. ADC CORE BLOCK DIAGRAM 16 FN6807.2 March 4, 2009 KAD5512P CLKN CLKP 4 RESETN CALIBRATION BEGINS ORP CALIBRATION COMPLETE 3 SNR CHANGE (dBFS) CALIBRATION TIME 2 1 0 -1 -2 -3 CLKOUTP -4 -40 -15 FIGURE 24. CALIBRATION TIMING Recalibration of the ADC can be initiated at any time by driving the RESETN pin low for a minimum of one clock cycle. An open-drain driver with a drive strength of less than 0.5mA is recommended, RESETN has an internal high impedance pull-up to OVDD. As is the case during power-on reset, the SDO, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. The performance of the KAD5512P changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements. Best performance will be achieved by recalibrating the ADC under the environmental conditions at which it will operate. A supply voltage variation of less than 100mV will generally result in an SNR change of less than 0.5dBFS and SFDR change of less than 3dBc. 35 60 85 TEMPERATURE (°C) FIGURE 25. SNR PERFORMANCE vs TEMPERATURE AFTER +25°C CALIBRATION 15 SFDR CHANGE (dBc) User-Initiated Reset 10 10 5 0 -5 -10 -15 -40 -15 10 35 60 85 TEMPERATURE (°C) FIGURE 26. SFDR PERFORMANCE vs TEMPERATURE AFTER +25°C CALIBRATION In situations where the sample rate is not constant, best results will be obtained if the device is calibrated at the highest sample rate. Reducing the sample rate by less than 75MSPS will typically result in an SNR change of less than 0.5dBFS and an SFDR change of less than 3dBc. Analog Input Figures 25 and 26 show the effect of temperature on SNR and SFDR performance without recalibration. In each plot, the ADC is calibrated at +25°C and temperature is varied over the operating range without recalibrating. The average change in SNR/SFDR is shown, relative to the +25°C value. Best performance is obtained when the analog inputs are driven differentially. The common-mode output voltage, VCM, should be used to properly bias the inputs as shown in Figures 28 through 30. An RF transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (IF) inputs. Two different transformer input schemes are shown in Figures 28 and 29. 17 The ADC core contains a fully differential input (VINP/VINN) to the sample and hold amplifier (SHA). The ideal full-scale input voltage is 1.45V, centered at the VCM voltage of 0.535V as shown in Figure 27. FN6807.2 March 4, 2009 KAD5512P Ω 348O 1.8 Ω 69.8O 1.4 1.0 Ω 25O Ω 100O INN INP 0.725V CM VCM 0.6 25O Ω Ω 69.8O Ω 49.9O 0.2 Ω 348O This dual transformer scheme is used to improve commonHmode rejection, which keeps the common-mode level of the input matched to VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the KAD5512P is 1000Ω. ADT1-1WT 1000pF 0.1µF FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT FIGURE 27. ANALOG INPUT RANGE ADT1-1WT KAD5512P VCM Ω 100O 0.22µF 0.535V 217O Ω KAD5512P A differential amplifier, as shown in Figure 30, can be used in applications that require DC-coupling. In this configuration, the amplifier will typically dominate the achievable SNR and distortion performance. Clock Input The clock input circuit is a differential pair (see Figure 43). Driving these inputs with a high level (up to 1.8VPP on each input) sine or square wave will provide the lowest jitter performance. A transformer with 4:1 impedance ratio will provide increased drive levels. VCM The recommended drive circuit is shown in Figure 31. A duty range of 40% to 60% is acceptable. The clock can be driven single-ended, but this will reduce the edge rate and may impact SNR performance. The clock inputs are internally self-biased to AVDD/2 to facilitate AC coupling. 0.1µF FIGURE 28. TRANSFORMER INPUT FOR GENERAL PURPOSE APPLICATIONS 200pF TC4-1W ADTL1-12 ADTL1-12 1000pF 200pF 0.1µF 1000pF CLKP Ω 200O KAD5512P 1000pF VCM CLKN 200pF FIGURE 29. TRANSMISSION-LINE TRANSFORMER INPUT FOR HIGH IF APPLICATIONS The SHA design uses a switched capacitor input stage (see Figure 42), which creates current spikes when the sampling capacitance is reconnected to the input voltage. This causes a disturbance at the input which must settle before the next sampling point. Lower source impedance will result in faster settling and improved performance. Therefore a 1:1 transformer and low shunt resistance are recommended for optimal performance. FIGURE 31. RECOMMENDED CLOCK DRIVE A selectable 2X frequency divider is provided in series with the clock input. The divider can be used in the 2X mode with a sample clock equal to twice the desired sample rate. This allows the use of the Phase Slip feature, which enables synchronization of multiple ADCs. TABLE 1. CLKDIV PIN SETTINGS CLKDIV PIN DIVIDE RATIO AVSS 2 Float 1 AVDD 4 The clock divider can also be controlled through the SPI port, which overrides the CLKDIV pin setting. Details on this are contained in “Serial Peripheral Interface” on page 22. 18 FN6807.2 March 4, 2009 KAD5512P A delay-locked loop (DLL) generates internal clock signals for various stages within the charge pipeline. If the frequency of the input clock changes, the DLL may take up to 52µs to regain lock at 250MSPS. The lock time is inversely proportional to the sample rate. Jitter In a sampled data system, clock jitter directly impacts the achievable SNR performance. The theoretical relationship between clock jitter (tJ) and SNR is shown in Equation 1 and is illustrated in Figure 32. 1 SNR = 20 log 10 ⎛ --------------------⎞ ⎝ 2πf t ⎠ (EQ. 1) The 48-QFN package option contains six LVDS data outputs, and therefore can only support DDR mode. Additionally, the drive current for LVDS mode can be set to a nominal 3 mA or a power-saving 2 mA. The lower current setting can be used in designs where the receiver is in close physical proximity to the ADC. The applicability of this setting is dependent upon the PCB layout, therefore the user should experiment to determine if performance degradation is observed. The output mode and LVDS drive current are selected via the OUTMODE pin as shown in Table 2. IN J TABLE 2. OUTMODE PIN SETTINGS OUTMODE PIN MODE AVSS LVCMOS Float LVDS, 3mA AVDD LVDS, 2mA 100 95 tj = 0.1ps 90 14 BITS SNR (dB) 85 80 tj = 1ps 75 12 BITS The output mode can also be controlled through the SPI port, which overrides the OUTMODE pin setting. Details on this are contained in “Serial Peripheral Interface” on page 22. 70 tj = 10ps 65 60 10 BITS tj = 100ps 55 50 1 10 100 INPUT FREQUENCY (MHz) 1000 FIGURE 32. SNR vs CLOCK JITTER This relationship shows the SNR that would be achieved if clock jitter were the only non-ideal factor. In reality, achievable SNR is limited by internal factors such as linearity, aperture jitter and thermal noise. Internal aperture jitter is the uncertainty in the sampling instant shown in Figure 1. The internal aperture jitter combines with the input clock jitter in a root-sum-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. The total jitter, combined with other noise sources, then determines the achievable SNR. Voltage Reference A temperature compensated voltage reference provides the reference charges used in the successive approximation operations. The full-scale range of each A/D is proportional to the reference voltage. The voltage reference is internally bypassed and is not accessible to the user. Digital Outputs Output data is available as a parallel bus in LVDS-compatible or CMOS modes. Additionally, the data can be presented in either double data rate (DDR) or single data rate (SDR) formats. The even numbered output bits are active in DDR mode. When CLKOUT is low the MSB and all odd bits are output, while on the high phase the LSB and all even bits are presented. Figures 1 and 2 show the timing relationships for LVDS/CMOS and DDR/SDR modes. 19 An external resistor creates the bias for the LVDS drivers. A 10kΩ, 1% resistor must be connected from the RLVDS pin to OVSS. Over Range Indicator The over range (OR) bit is asserted when the output code reaches positive full-scale (e.g. 0xFFF in offset binary mode). The output code does not wrap around during an over-range condition. The OR bit is updated at the sample rate. Power Dissipation The power dissipated by the KAD5512P is primarily dependent on the sample rate and the output modes: LVDS vs. CMOS and DDR vs. SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate. The output supply dissipation is approximately constant in LVDS mode, but linearly related to the clock frequency in CMOS mode. Figures 36 and 37 illustrate these relationships. Nap/Sleep Portions of the device may be shut down to save power during times when operation of the ADC is not required. Two power saving modes are available: nap, and sleep. Nap mode is only available through SPI control, while Sleep mode can be selected with the pin or through SPI. Nap mode reduces power dissipation by approximately 70% (depending on operating state) and recovers to normal operation in approximately 1µs. Sleep mode reduces power dissipation to less than 20mW but requires 1ms to recover. The clock should remain running and at a fixed frequency during Nap or Sleep. Recovery time from Nap mode will FN6807.2 March 4, 2009 KAD5512P increase if the clock is stopped, since the internal DLL can take up to 52µs to regain lock at 250MSPS. By default after the device is powered on, the operational state is controlled by the NAPSLP pin as shown in Table 3. Converting back to offset binary from Gray code must be done recursively, using the result of each bit for the next lower bit as shown in Figure 34. GRAY CODE 11 10 9 •••• 1 0 TABLE 3. NAPSLP PIN SETTINGS NAPSLP PIN MODE AVSS Normal Float Sleep AVDD Nap •••• The power-down mode can also be controlled through the SPI port, which overrides the NAPSLP pin setting. Details on this are contained in “Serial Peripheral Interface” on page 22. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. •••• Data Format Output data can be presented in three formats: two’s complement, Gray code and offset binary. The data format is selected via the OUTFMT pin as shown in Table 4. OUTFMT PIN MODE AVSS Offset Binary Float Two’s Complement AVDD Gray Code When calculating Gray code the MSB is unchanged. The remaining bits are computed as the XOR of the current bit position and the next most significant bit. Figure 33 shows this operation. 9 9 •••• 1 0 TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING Offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the most positive input to 0xFFF (all ones). Two’s complement coding simply complements the MSB of the offset binary representation. 10 10 Mapping of the input voltage to the various data formats is shown in Table 5. The data format can also be controlled through the SPI port, which overrides the OUTFMT pin setting. Details on this are contained in “Serial Peripheral Interface” on page 22. 11 11 FIGURE 34. GRAY CODE TO BINARY CONVERSION TABLE 4. OUTFMT PIN SETTINGS BINARY BINARY •••• 1 INPUT TWO’S VOLTAGE OFFSET BINARY COMPLEMENT GRAY CODE –Full Scale 000 00 000 00 00 100 00 000 00 00 000 00 000 00 00 –Full Scale 000 00 000 00 01 100 00 000 00 01 000 00 000 00 01 + 1LSB Mid–Scale 100 00 000 00 00 000 00 000 00 00 110 00 000 00 00 +Full Scale – 1LSB 111 11 111 11 10 011 11 111 11 10 100 00 000 00 01 +Full Scale 111 11 111 11 11 011 11 111 111 1 100 00 000 00 00 0 •••• GRAY CODE 11 10 9 •••• 1 0 FIGURE 33. BINARY TO GRAY CODE CONVERSION 20 FN6807.2 March 4, 2009 KAD5512P CSB SCLK SDIO R/W W1 W0 A12 A11 A10 A1 A0 D7 D6 D5 D4 D3 D2 D1D 0 D2 D3 D4 D5 D6 D7 FIGURE 35. MSB-FIRST ADDRESSING CSB SCLK SDIO A0 A1 A2 A11 A12 W0 W1 R/W D0 D1 FIGURE 36. LSB-FIRST ADDRESSING tH tCLK tS tDS tHI tDH CSB tLO SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 FIGURE 37. INSTRUCTION/ADDRESS PHASE CSB STALLING CSB SCLK SDIO INSTRUCTION/ADDRESS DATA WORD 1 DATA WORD 2 FIGURE 38. 2-BYTE TRANSFER LAST LEGAL CSB STALLING CSB SCLK SDIO INSTRUCTION/ADDRESS DATA WORD 1 DATA WORD N FIGURE 39. N-BYTE TRANSFER 21 FN6807.2 March 4, 2009 KAD5512P Serial Peripheral Interface A serial peripheral interface (SPI) bus is used to facilitate configuration of the device and to optimize performance. The SPI bus consists of chip select (CSB), serial clock (SCLK) serial data output (SDO), and serial data input/output (SDIO). The maximum SCLK rate is equal to the ADC sample rate (fSAMPLE) divided by 16 for write operations and fSAMPLE divided by 66 for reads. At fSAMPLE = 250MHz, maximum SCLK is 15.63MHz for writing and 3.79MHz for read operations. There is no minimum SCLK rate. The following sections describe various registers that are used to configure the SPI or adjust performance or functional parameters. Many registers in the available address space (0x00 to 0xFF) are not defined in this document. Additionally, within a defined register there may be certain bits or bit combinations that are reserved. Undefined registers and undefined values within defined registers are reserved and should not be selected. Setting any reserved register or value may produce indeterminate results. SPI Physical Interface The serial clock pin (SCLK) provides synchronization for the data transfer. By default, all data is presented on the serial data input/output (SDIO) pin in three-wire mode. The state of the SDIO pin is set automatically in the communication protocol (described below). A dedicated serial data output pin (SDO) can be activated by setting 0x00[7] high to allow operation in four-wire mode. The SPI port operates in a half duplex master/slave configuration, with the KAD5512P functioning as a slave. Multiple slave devices can interface to a single master in four-wire mode only, since the SDIO output of an unaddressed device is asserted in three-wire mode. The chip-select bar (CSB) pin determines when a slave device is being addressed. Multiple slave devices can be written to concurrently, but only one slave device can be read from at a given time (again, only in four-wire mode). If multiple slave devices are selected for reading at the same time, the results will be indeterminate. The communication protocol begins with an instruction/address phase. The first rising SCLK edge following a high to low transition on CSB determines the beginning of the two-byte instruction/address command; SCLK must be static low before the CSB transition. Data can be presented in MSB-first order or LSB-first order. The default is MSB-first, but this can be changed by setting 0x00[6] high. Figures 35 and 36 show the appropriate bit ordering for the MSB-first and LSB-first modes, respectively. In MSB-first mode the address is incremented for multi-byte transfers, while in LSB-first mode it’s decremented. In the default mode the MSB is R/W, which determines if the data is to be read (active high) or written. The next two bits, W1 and W0, determine the number of data bytes to be read 22 or written (see Table 6). The lower 13 bits contain the first address for the data transfer. This relationship is illustrated in Figure 37, and timing values are given in “Switching Specifications” on page 7. After the instruction/address bytes have been read, the appropriate number of data bytes are written to or read from the ADC (based on the R/W bit status). The data transfer will continue as long as CSB remains low and SCLK is active. Stalling of the CSB pin is allowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. For transfers of four bytes or more, CSB is allowed stall in the middle of the instruction/address bytes or before the first data byte. If CSB transitions to a high state after that point the state machine will reset and terminate the data transfer. TABLE 6. BYTE TRANSFER SELECTION [W1:W0] BYTES TRANSFERRED 00 1 01 2 10 3 11 4 or more Figures 38 and 39 illustrate the timing relationships for 2-byte and N-byte transfers, respectively. The operation for a 3-byte transfer can be inferred from these diagrams. SPI Configuration ADDRESS 0X00: CHIP_PORT_CONFIG Bit ordering and SPI reset are controlled by this register. Bit order can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB first) to accommodate various microcontrollers. Bit 7 SDO Active Bit 6 LSB First Setting this bit high configures the SPI to interpret serial data as arriving in LSB to MSB order. Bit 5 Soft Reset Setting this bit high resets all SPI registers to default values. Bit 4 Reserved This bit should always be set high. Bits 3:0 These bits should always mirror bits 4:7 to avoid ambiguity in bit ordering. ADDRESS 0X02: BURST_END If a series of sequential registers are to be set, burst mode can improve throughput by eliminating redundant addressing. In 3-wire SPI mode the burst is ended by pulling the CSB pin high. If the device is operated in 2-wire mode the CSB pin is not available. In that case, setting the burst_end address determines the end of the transfer. FN6807.2 March 4, 2009 KAD5512P During a write operation, the user must be cautious to transmit the correct number of bytes based on the starting and ending addresses. ADDRESS 0X22: GAIN_COARSE ADDRESS 0X23: GAIN_MEDIUM ADDRESS 0X24: GAIN_FINE Bits 7:0 Burst End Address This register value determines the ending address of the burst data. Device Information ADDRESS 0X08: CHIP_ID ADDRESS 0X09: CHIP_VERSION The generic die identifier and a revision number, respectively, can be read from these two registers. Indexed Device Configuration/Control ADDRESS 0X10: DEVICE_INDEX_A A common SPI map, which can accommodate single-channel or multi-channel devices, is used for all Intersil ADC products. Certain configuration commands (identified as Indexed in the SPI map) can be executed on a per-converter basis. This register determines which converter is being addressed for an Indexed command. It is important to note that only a single converter can be addressed at a time. This register defaults to 00h, indicating that no ADC is addressed. Therefore Bit 0 must be set high in order to execute any Indexed commands. Error code ‘AD’ is returned if any indexed register is read from without properly setting device_index_A. ADDRESS 0X20: OFFSET_COARSE ADDRESS 0X21: OFFSET_FINE The input offset of the ADC core can be adjusted in fine and coarse steps. Both adjustments are made via an 8-bit word as detailed in Table 7. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. Gain of the ADC core can be adjusted in coarse, medium and fine steps. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. Multiple Coarse Gain Bits can be set for a total adjustment range of +/- 4.2%. ( ‘0011’ =~ -4.2% and ‘1100’ =~ +4.2% ) It is recommended to use one of the coarse gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the registers at 23h and 24h. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. TABLE 8. COARSE GAIN ADJUSTMENT 0x22[3:0] NOMINAL COARSE GAIN ADJUST (%) Bit3 +2.8 Bit2 +1.4 Bit1 -2.8 Bit0 -1.4 TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS PARAMETER 0x23[7:0] MEDIUM GAIN 0x24[7:0] FINE GAIN Steps 256 256 –Full Scale (0x00) -2% -0.20% Mid–Scale (0x80) 0.00% 0.00% +Full Scale (0xFF) +2% +0.2% Nominal Step Size 0.016% 0.0016% ADDRESS 0X25: MODES Steps 255 255 Two distinct reduced power modes can be selected. By default, the tri-level NAPSLP pin can select normal operation or sleep modes (refer to “Nap/Sleep” on page 19). This functionality can be overridden and controlled through the SPI. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. This register is not changed by a Soft Reset. –Full Scale (0x00) -133LSB (-47mV) -5LSB (-1.75mV) TABLE 10. POWER-DOWN CONTROL Mid–Scale (0x80) 0.0LSB (0.0mV) 0.0LSB TABLE 7. OFFSET ADJUSTMENTS PARAMETER 0x20[7:0] COARSE OFFSET 0x21[7:0] FINE OFFSET +Full Scale (0xFF) +133LSB (+47mV) +5LSB (+1.75mV) Nominal Step Size 1.04LSB (0.37mV) 0.04LSB (0.014mV) 23 VALUE 0x25[2:0] POWER DOWN MODE 000 Pin Control 001 Normal Operation 010 Nap Mode 100 Sleep Mode FN6807.2 March 4, 2009 KAD5512P Nap mode must be entered by executing the following sequence: SEQUENCE REGISTER VALUE 1 0x10 0x01 2 0x25 0x02 3 0x10 0x02 4 0x25 0x02 Return to Normal operation as follows: SEQUENCE REGISTER VALUE 1 0x10 0x01 2 0x25 0x01 3 0x10 0x02 4 0x25 0x01 Global Device Configuration/Control ADDRESS 0X71: PHASE_SLIP When using the clock divider, it’s not possible to determine the synchronization of the incoming and divided clock phases. This is particularly important when multiple ADCs are used in a time-interleaved system. The phase slip feature allows the rising edge of the divided clock to be advanced by one input clock cycle when in CLK/4 mode, as shown in Figure 40. Execution of a phase_slip command is accomplished by first writing a ‘0’ to bit 0 at address 71h followed by writing a ‘1’ to bit 0 at address 71h (32 sclk cycles ). CLK = CLKP – CLKN CLK 1.00ns controlled through the SPI, as shown in Table 11. This register is not changed by a Soft Reset. TABLE 11. CLOCK DIVIDER SELECTION VALUE 0x72[2:0] CLOCK DIVIDER 000 Pin Control 001 Divide by 1 010 Divide by 2 100 Divide by 4 ADDRESS 0X73: OUTPUT_MODE_A The output_mode_A register controls the physical output format of the data, as well as the logical coding. The KAD5512P can present output data in two physical formats: LVDS or LVCMOS. Additionally, the drive strength in LVDS mode can be set high (3mA) or low (2mA). By default, the tri-level OUTMODE pin selects the mode and drive level (refer to “Digital Outputs” on page 19). This functionality can be overridden and controlled through the SPI, as shown in Table 12. Data can be coded in three possible formats: two’s complement, Gray code or offset binary. By default, the tri-level OUTFMT pin selects the data format (refer to “Data Format” on page 20). This functionality can be overridden and controlled through the SPI, as shown in Table 13. This register is not changed by a Soft Reset. TABLE 12. OUTPUT MODE CONTROL VALUE 0x93[7:5] 000 Pin Control 001 LVDS 2mA 010 LVDS 3mA 100 LVCMOS CLK÷4 4.00ns CLK÷4 SLIP ONCE CLK÷4 SLIP TWICE FIGURE 40. PHASE SLIP: CLK÷4 MODE, fCLOCK = 1000MHz ADDRESS 0X72: CLOCK_DIVIDE The KAD5512P has a selectable clock divider that can be set to divide by four, two or one (no division). By default, the tri-level CLKDIV pin selects the divisor (refer to “Clock Input” on page 18). This functionality can be overridden and 24 TABLE 13. OUTPUT FORMAT CONTROL VALUE 0x93[2:0] OUTPUT FORMAT 000 Pin Control 001 Two’s Complement 010 Gray Code 100 Offset Binary ADDRESS 0X74: OUTPUT_MODE_B ADDRESS 0X75: CONFIG_STATUS Bit 6 DLL Range This bit sets the DLL operating range to fast (default) or slow. FN6807.2 March 4, 2009 KAD5512P Internal clock signals are generated by a delay-locked loop (DLL), which has a finite operating range. Table 14 shows the allowable sample rate ranges for the slow and fast settings. TABLE 14. DLL RANGES ADDRESS 0XC0: TEST_IO Bits 7:6 User Test Mode These bits set the test mode to static (0x00) or alternate (0x01) mode. Other values are reserved. DLL RANGE MIN MAX UNIT Slow 40 100 MSPS The four LSBs in this register (Output Test Mode) determine the test pattern in combination with registers 0xC2 through 0xC5. Refer to Table 16. Fast 80 fS MAX MSPS TABLE 15. OUTPUT TEST MODES The output_mode_B and config_status registers are used in conjunction to enable DDR mode and select the frequency range of the DLL clock generator. The method of setting these options is different from the other registers. READ OUTPUT_MODE_B 0x74 READ CONFIG_STATUS 0x75 WRITE TO 0x74 DESIRED VALUE FIGURE 41. SETTING OUTPUT_MODE_B REGISTER The procedure for setting output_mode_B is shown in Figure 41. Read the contents of output_mode_B and config_status and XOR them. Then XOR this result with the desired value for output_mode_B and write that XOR result to the register. Device Test The KAD5512 can produce preset or user defined patterns on the digital outputs to facilitate in-situ testing. A static word can be placed on the output bus, or two different words can alternate. In the alternate mode, the values defined as Word 1 and Word 2 (as shown in Table 15) are set on the output bus on alternating clock phases. The test mode is enabled asynchronously to the sample clock, therefore several sample clock cycles may elapse before the data is present on the output bus. 25 VALUE 0xC0[3:0] OUTPUT TEST MODE 0000 Off 0001 WORD 1 WORD 2 Midscale 0x8000 N/A 0010 Positive Full-Scale 0xFFFF N/A 0011 Negative Full-Scale 0x0000 N/A 0100 Checkerboard 0xAAAA 0x5555 0101 Reserved N/A N/A 0110 Reserved N/A N/A 0111 One/Zero 0xFFFF 0x0000 1000 User Pattern user_patt1 user_patt2 ADDRESS 0XC2: USER_PATT1_LSB ADDRESS 0XC3: USER_PATT1_MSB These registers define the lower and upper eight bits, respectively, of the first user-defined test word. ADDRESS 0XC4: USER_PATT2_LSB ADDRESS 0XC5: USER_PATT2_MSB These registers define the lower and upper eight bits, respectively, of the second user-defined test word. FN6807.2 March 4, 2009 KAD5512P SPI Memory Map Indexed Device Config/Control Info SPI Config TABLE 16. SPI MEMORY MAP Addr (Hex) Parameter Name Bit 7 (MSB) 00 port_config SDO Active 01 reserved Reserved 02 burst_end Burst end address [7:0] 03-07 reserved Reserved 08 chip_id 09 chip_version 10 device_index_A 11-1F reserved Reserved 20 offset_coarse 21 offset_fine 22 gain_coarse 23 gain_medium 24 gain_fine 25 modes 26-5F reserved Reserved 60-6F reserved Reserved 70 reserved Reserved 71 phase_slip Bit 5 LSB First Soft Reset Bit 2 Bit 1 Bit 0 (LSB) Def. Value (Hex) Indexed/ Global Mirror (bit5) Mirror (bit6) Mirror (bit7) 00h G 00h G Chip ID # Read only G Chip Version # Read only G 00h I Coarse Offset cal. value I Fine Offset cal. value I cal. value I Medium Gain cal. value I Fine Gain cal. value I 00h NOT affected by Soft Reset I 00h G Clock Divide [2:0] 000 = Pin Control 001 = divide by 1 010 = divide by 2 100 = divide by 4 other codes = reserved 00h NOT affected by Soft Reset G Output Format [2:0] 000 = Pin Control 001 = Twos Complement 010 = Gray Code 100 = Offset Binary other codes = reserved 00h NOT affected by Soft Reset G Bit 4 Bit 3 Reserved Reserved ADC00 Coarse Gain Power-Down Mode [2:0] 000 = Pin Control 001 = Normal Operation 010 = Nap 100 = Sleep other codes = reserved Reserved 72 Global Device Config/Control Bit 6 clock_divide Output Mode [2:0] 000 = Pin Control 001 = LVDS 2mA 010 = LVDS 3mA 100 = LVCMOS other codes = reserved Next Clock Edge 73 output_mode_A 74 output_mode_B DLL Range 0 = fast 1 = slow DDR Enable 00h NOT affected by Soft Reset G 75 config_status XOR Result XOR Result Read Only G 76-BF reserved Reserved 26 FN6807.2 March 4, 2009 KAD5512P Device Test TABLE 16. SPI MEMORY MAP (Continued) Addr (Hex) Parameter Name C0 test_io Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 0 (LSB) Bit 1 Def. Value (Hex) Indexed/ Global 00h G 00h G Output Test Mode [3:0] User Test Mode [1:0] 00 = Single 01 = Alternate 10 = Reserved 11 = Reserved 0 = Off 1 = Midscale Short 2 = +FS Short 3 = -FS Short 4 = Checker Board 5 = reserved 6 = reserved 7 = One/Zero Word Toggle 8 = User Input 9-15 = reserved C1 Reserved Reserved C2 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h G C3 user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 00h G C4 user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h G C5 user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 00h G C6-FF reserved Reserved Equivalent Circuits AVDD TO CLOCKPHASE GENERATION AVDD CLKP AVDD CSAMP 1.6pF TO CHARGE PIPELINE Φ F3 INP Φ2 F Φ1 F Ω 1000O CSAMP 1.6pF AVDD TO CHARGE PIPELINE Φ3 F INN Φ2 F Φ1 F AVDD 11kO Ω CLKN FIGURE 43. CLOCK INPUTS AVDD (20k PULL-UP ON RESETN ONLY) AVDD Ω 75kO AVDD TO SENSE LOGIC Ω 280O INPUT Ω 75kO FIGURE 44. TRI-LEVEL DIGITAL INPUTS 27 OVDD OVDD Ω 75kO Ω 75kO Ω 18kO AVDD 11kO Ω FIGURE 42. ANALOG INPUTS AVDD Ω 18kO OVDD INPUT 20kΩ Ω 280Ω TO LOGIC FIGURE 45. DIGITAL INPUTS FN6807.2 March 4, 2009 KAD5512P Equivalent Circuits (Continued) OVDD 2mA OR 3mA OVDD DATA DATA D[11:0]P OVDD OVDD OVDD D[11:0]N DATA DATA DATA D[11:0] 2mA OR 3mA FIGURE 47. CMOS OUTPUTS FIGURE 46. LVDS OUTPUTS AVDD VCM 0.535V + – FIGURE 48. VCM_OUT OUTPUT Layout Considerations Split Ground and Power Planes Data converters operating at high sampling frequencies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections. Analog supply and ground planes should be laid out under signal and clock inputs. Locate the digital planes under outputs and logic pins. Grounds should be joined under the chip. Clock Input Considerations Use matched transmission lines to the transformer inputs for the analog input and clock signals. Locate transformers and terminations as close to the chip as possible. Bypass and Filtering Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very close to device pins. Longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. Make sure that connections to ground are direct and low impedance. Avoid forming ground loops. LVDS Outputs Output traces and connections must be designed for 50Ω (100Ω differential) characteristic impedance. Keep traces direct and minimize bends where possible. Avoid crossing ground and power-plane breaks with signal traces. LVCMOS Outputs Exposed Paddle The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for optimal thermal performance. 28 Output traces and connections must be designed for 50Ω characteristic impedance. Unused Inputs Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will not be operated do not require connection to ensure optimal ADC performance. These inputs can be left FN6807.2 March 4, 2009 KAD5512P floating if they are not used. Tri-level inputs (NAPSLP, OUTMODE, OUTFMT, CLKDIV) accept a floating input as a valid state, and therefore should be biased according to the desired functionality. Definitions Analog Input Bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full-scale low-frequency value. This is also referred to as Full Power Bandwidth. Aperture Delay or Sampling Delay is the time required after the rise of the clock input for the sampling switch to open, at which time the signal is held for conversion. Aperture Jitter is the RMS variation in aperture delay for a set of samples. Clock Duty Cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. Power Supply Rejection Ratio (PSRR) is the ratio of the observed magnitude of a spur in the ADC FFT, caused by an AC signal superimposed on the power supply voltage. Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one half the clock frequency, including harmonics but excluding DC. Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one-half the sampling frequency, excluding harmonics and DC. SNR and SINAD are either given in units of dB when the power of the fundamental is used as the reference, or dBFS (dB to full scale) when the converter’s full-scale input power is used as the reference. Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the largest spurious spectral component. The largest spurious spectral component may or may not be a harmonic. Effective Number of Bits (ENOB) is an alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02 Gain Error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage less 2 LSB. It is typically expressed in percent. Integral Non-Linearity (INL) is the maximum deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms of input voltage is VFS/(2N-1) where N is the resolution in bits. Missing Codes are output codes that are skipped and will never appear at the ADC output. These codes cannot be reached with any input value. Most Significant Bit (MSB) is the bit that has the largest value or weight. Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the data. 29 FN6807.2 March 4, 2009 KAD5512P Revision History DATE REVISION 7/30/08 Rev 1 CHANGE Initial Release of Production Datasheet 12/5/08 FN6807.0 Converted to intersil template. Assigned file number FN6807. Rev 0 - first release (as preliminary datasheet) with new file number. 12/23/08 FN6807.1 P1; revised Key Specs P2; added Part Marking column to Order Info P4; moved Thermal Resistance to Thermal Info table and added Theta JA Note 3 per packaging P4-6; revisions throughout spec tables. Removed note from Elec Specs (Nap Mode must be invoked using SPI.) Added notes 9 and 10 to Switching Specs. P9; revised function for Pin 22 OUTMODE, Pin 23 NAPSLP and Pin 70 OUTFMT P11; revised function for Pin 16 NAPSLP P13-15; Performance curves revised throughout P17; User Initiated Reset - revised 2nd sentence of 1st paragraph P19; Nap/Sleep - revised 1st and 2nd sentences of 2nd paragraph P23; Address 0x24: Gain_Fine; added 2 sentences to end of 1st paragraph. Revised Table 8 P22; Serial Peripheral Interface- 1st paragraph; revised 2nd and 4th sentences. P24; removed Figure (PHASE SLIP: CLK÷2 MODE, fCLOCK = 500MHz) Address 0x71: Phase_slip; added sentence to end of paragraph P27; revised Fig 45 P27; Table 16; revised Bits7:4, Addr C0 Throughout; formatted graphics to Intersil standards 2/25/09 FN6807.2 Changed “odd” bits N in Figure 1A - DDR to “even” bits N, Replaced POD L48.7x7E due to changed dimension from “9.80 sq” to “6.80” sq. in land pattern All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 30 FN6807.2 March 4, 2009 KAD5512P Package Outline Drawing L48.7x7E 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 2/09 7.00 PIN 1 INDEX AREA PIN 1 INDEX AREA 4X 5.50 A 6 B 37 6 48 1 36 44X 0.50 Exp. DAP 5.60 Sq. 7.00 (4X) 12 25 0.15 24 13 48X 0.25 48X 0.40 TOP VIEW 4 0.10 M C A B BOTTOM VIEW SEE DETAIL "X" 0.90 Max C 0.10 C 0.08 C SEATING PLANE SIDE VIEW 44X 0.50 6.80 Sq C 0 . 2 REF 5 48X 0.25 5.60 Sq 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" 48X 0.60 TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 31 FN6807.2 March 4, 2009 KAD5512P Package Outline Drawing L72.10x10D 72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 11/08 10.00 A 4X 8.50 PIN 1 INDEX AREA B 55 6 72 1 54 68X 0.50 Exp. DAP 6.00 Sq. 10.00 18 37 (4X) PIN 1 INDEX AREA 6 0.15 36 19 72X 0.24 72X 0.40 TOP VIEW 4 0.10 M C A B BOTTOM VIEW SEE DETAIL "X" 0.90 Max C 0.10 C 0.08 C SEATING PLANE 68X 0.50 SIDE VIEW 72X 0.24 9.80 Sq 6.00 Sq C 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. 72X 0.60 DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 32 FN6807.2 March 4, 2009