16-Bit, 250/200/130 MSPS JESD204B High Speed Serial Output ADC ISLA216S Features The ISLA216S is a series of low-power, high-performance, 16-bit, analog-to-digital converters. Designed with FemtoCharge™ technology on a standard CMOS process, the series supports sampling rates of up to 250MSPS. The ISLA216S is part of a pin-compatible family of 12-, 14-, and 16-bit A/Ds with maximum sample rates ranging from 130 to 500MSPS and shares the same analog core as Intersil's proven ISLA216P series of ADCs. The family minimizes power consumption while providing state-of-the art dynamic performance, offering an optimal performance-vs-power trade-off. • JESD204A/B High Speed Data Interface - JESD204A Compliant - JESD204B Device Subclass 0 Compliant - JESD204B Device Subclass 2 Compatible - JESD204 Output Lanes Run up to 4.375Gbps - Highly Configurable JESD204 Transmitter • Multiple Chip Time Alignment and Deterministic Latency Support (JESD204B Device Subclass 2) • SPI Programmable Debugging Features and Test Patterns • 48-pin QFN 7mmx7mm Package Differentiating the ISLA216S from the ISLA216P is its highly configurable, JESD204B-compliant, high speed serial output link. The link offers data rates up to 4.375Gbps per lane and multiple packing modes. It uses two lanes to transmit the conversion data. The SERDES transmitter also provides deterministic latency and multi-chip time alignment support to satisfy an application's complex synchronization requirements. A serial peripheral interface (SPI) port allows for extensive configurability of the JESD204B transmitter including access to its built-in link and transport-layer test patterns. The SPI port also provides control for numerous additional features including the fine gain and offset adjustments of the two ADC cores as well as the programmable clock divider, enabling 2x and 4x harmonic clocking. The ISLA216S is available in a space-saving 7mmx7mm 48 Ld QFN package. The package features a thermal pad for improved thermal performance and is specified over the full industrial temperature range (-40°C to +85°C). Key Specifications • SNR @ 250/200/130MSPS 75.8/77.2/78.0 dBFS fIN = 30MHz 74.6/75.2/74.8 dBFS fIN = 190MHz • SFDR @ 250/200/130MSPS 87/93/94 dBc fIN = 30MHz 82/81/81 dBc fIN = 190MHz • Total Power Consumption: 887mW @ 250MSPS Applications • • • • • Radar and Satellite Antenna Array Processing Broadband Communications and Microwave Receivers High-Performance Data Acquisition Communications Test Equipment High-Speed Medical Imaging Pin-Compatible Family RESOLUTION SPEED (MSPS) PRODUCT AVAILABILITY ISLA216S25 16 250 Now ISLA216S20 16 200 Now MODEL ISLA216S13 16 130 Now ISLA214S50 14 500 Now ISLA212S50 12 500 Soon ISLA214S25 14 250 Soon ISLA212S25 12 250 Soon FIGURE 1. SERDES DATA EYE AT 4.375Gbps February 2, 2012 FN7996.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. OVDD (PLL) OVDD SYNC AVDD ISLA216S CLKP CLOCK GENERATION CLKN LANE[1:0]P VINP 16-BIT 250MSPS ADC SHA VINN 1.25V VCM + – LANE[1:0]N JESD204 TRANSMITTER VREF OVSS CSB SCLK SDIO SDO RESETN NAPSLP AVSS AVSS (PLL) SPI CONTROL FIGURE 2. BLOCK DIAGRAM Pin Configuration DNC DNC AVDD NAPSLP CLKDIV SDIO SCLK CSB SDO OVDD OVSS OVSS ISLA216S (48 LD QFN) TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 VCM 1 36 OVDD AVDD 2 35 OVSS AVSS 3 34 DNC AVSS 4 33 DNC VINN 5 32 OVSS VINN 6 31 LANE1N VINP 7 30 LANE1P VINP 8 29 OVSS AVSS 9 28 LANE0N AVSS 10 27 LANE0P AVDD 11 DNC 12 2 26 OVSS PAD – Exposed Paddle 13 14 15 16 17 18 19 20 21 22 23 24 RESETN AVDD AVDD CLKP CLKN SYNCP SYNCN DNC OVSS (PLL) OVDD (PLL) OVSS (PLL) OVDD (PLL) 25 OVDD FN7996.0 February 2, 2012 ISLA216S Pin Descriptions PIN NUMBER NAME FUNCTION 2, 11, 14, 15, 46 AVDD 1.8V Analog Supply 12, 20, 33, 34, 47, 48 DNC Do Not Connect 3, 4, 9, 10 AVSS Analog Ground 7, 8 VINP Analog Input, Positive 5, 6 VINN Analog Input, Negative 1 VCM Common Mode Output 44 CLKDIV 16, 17 CLKP, CLKN 45 NAPSLP Power Control (Nap, Sleep modes) 13 RESETN Power On Reset (Active Low) 26, 29, 32, 35, 37, 38 OVSS Output Ground 25, 36, 39 OVDD 1.8V Digital Supply Clock Divider Control Clock Input True, Complement 22, 24 OVDD (PLL) 1.8V Analog Supply for SERDES PLL 21, 23 OVSS (PLL) Analog Ground Supply for SERDES PLL 18, 19 SYNCP, SYNCN 27, 28 LANE0P, LANE0N SERDES Lane 0 30, 31 LANE1P, LANE1N SERDES Lane 1 40 SDO SPI Serial Data Output 41 CSB SPI Chip Select (active low) 42 SCLK SPI Clock 43 SDIO SPI Serial Data Input/Output PAD AVSS Exposed Paddle. Analog Ground (connect to AVSS) JESD204A SYNC Input Ordering Information PART NUMBER (Notes 1, 2) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISLA216S25IR1Z ISLA216S25 IR1Z -40 to +85 48 Ld QFN L48.7x7G ISLA216S20IR1Z ISLA216S20 IR1Z -40 to +85 48 Ld QFN L48.7x7G ISLA216S13IR1Z ISLA216S13 IR1Z -40 to +85 48 Ld QFN L48.7x7G Coming Soon ISLA216S25IR48EV1Z Evaluation Board NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA216S13, ISLA216S20, ISLA216S25. For more information on MSL please see techbrief TB363. 3 FN7996.0 February 2, 2012 ISLA216S Table of Contents Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Switching Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power-On Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Temperature Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Nap/Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 JESD204A Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Initial Lane Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 ADDRESS 0xDF - 0xF3: JESD204 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Address 0xDF-0xEE: JESD204A Parameter INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ADC Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Clock Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Bypass and Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CML Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4 FN7996.0 February 2, 2012 ISLA216S Absolute Maximum Ratings Thermal Information AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Latchup (Tested per JESD-78C;Class 2,Level A) . . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 48 Ld QFN (Notes 3, 4, 5) . . . . . . . . . . . . . . 24 0.4 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C NOTES: 3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 5. For solder stencil layout and reflow guidelines, please see Tech Brief TB389. CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply over the operating temperature range, -40°C to +85°C. ISLA216S25 PARAMETER SYMBOL CONDITIONS MIN (Note 6) TYP 1.95 2.14 ISLA216S20 ISLA216S13 MAX MIN MAX MIN MAX (Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) UNITS DC SPECIFICATIONS Analog Input Full-Scale Analog Input Range VFS Differential 2.22 1.95 2.08 2.22 1.95 2.03 2.22 VP-P Input Resistance RIN Differential 300 300 300 Ω Input Capacitance CIN Differential 10.7 10.7 10.7 pF Full Temp 145 124 68 ppm/°C Full Scale Range Temp. Drift AVTC Input Offset Voltage VOS Gain Error EG 1 1 1 % Common-Mode Output Voltage VCM 0.94 0.94 0.94 V Common Mode Input Current (per pin) ICM 12.0 12.0 12.0 µA/MSPS Inputs Common Mode Voltage 0.9 0.9 0.9 V CLKP, CLKN Swing 1.8 1.8 1.8 V -5.0 ±1 5.0 -5.0 ±1 5.0 -5.0 ±1 5.0 mV Clock Inputs Power Requirements 1.8V Analog Supply Voltage AVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.8 V 1.8V Digital Supply Voltage OVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.8 V 1.8V Analog Supply Current IAVDD 354 378 325 349 283 306 mA 1.8V Digital Supply Current IOVDD 139 152 128 140 109 122 mA 5 FN7996.0 February 2, 2012 ISLA216S Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) ISLA216S25 PARAMETER SYMBOL Power Supply Rejection Ratio (Note 7) PSRR CONDITIONS MIN (Note 6) TYP ISLA216S20 ISLA216S13 MAX MIN MAX MIN MAX (Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) UNITS 30MHz 200mVP-P 38 38 38 dB 1MHz 200mVP-P 44 44 44 dB Total Power Dissipation Normal Mode PD 887 954 815 880 706 770 mW Nap Mode PD 323 367 300 342 267 310 mW Sleep Mode PD CSB at logic high 6 14 6 14 6 14 mW Nap Mode Wakeup Time Sample Clock Running 5 5 5 µs Sleep Mode Wakeup Time Sample Clock Running 1 1 1 ms ±0.14 LSB ±9.0 LSB AC SPECIFICATIONS (Note 8) Differential Nonlinearity DNL Integral Nonlinearity INL Minimum Conversion Rate (Note 9) fS MIN Maximum Conversion Rate fS MAX Signal-to-Noise Ratio (Note 10) SNR Signal-to-Noise and Distortion (Note 10) Effective Number of Bits (Note 10) -0.99 ±0.24 -0.99 ±16.0 ±0.17 ±12.0 100 250 fIN = 30MHz fIN = 105MHz SINAD 6 200 75.5 100 130 77.2 74.3 76.6 75.0 MSPS MSPS 78.0 dBFS 76.8 dBFS fIN = 190MHz 74.6 75.2 74.8 dBFS fIN = 363MHz 72.4 72.5 71.2 dBFS fIN = 495MHz 70.8 70.6 69.6 dBFS fIN = 605MHz 69.3 69.2 67.3 dBFS fIN = 30MHz 75.5 77.1 77.7 dBFS 76.3 dBFS fIN = 105MHz ENOB 100 75.8 72.3 -0.99 71.1 74.9 73.6 76.3 74.2 fIN = 190MHz 73.9 74.1 73.8 dBFS fIN = 363MHz 69.8 69.0 66.0 dBFS fIN = 495MHz 66.5 66.3 65.9 dBFS fIN = 605MHz 64.9 64.1 58.4 dBFS fIN = 30MHz 12.20 12.45 12.59 Bits fIN = 105MHz 11.51 12.14 11.93 12.36 12.03 12.36 Bits fIN = 190MHz 11.95 12.03 11.91 Bits fIN = 363MHz 11.27 11.19 10.66 Bits fIN = 495MHz 10.76 10.72 10.61 Bits fIN = 605MHz 10.52 10.43 9.52 Bits FN7996.0 February 2, 2012 ISLA216S Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) ISLA216S25 PARAMETER SYMBOL Spurious-Free Dynamic Range (Note 10) SFDR Spurious-Free Dynamic Range Excluding H2, H3 (Note 10) CONDITIONS MIN (Note 6) fIN = 30MHz fIN = 105MHz 74 IMD ISLA216S13 MAX MIN MAX MIN MAX (Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) 87 93 84 76 88 76 UNITS 94 dBc 85 dBc fIN = 190MHz 82 81 81 dBc fIN = 363MHz 72 70 66 dBc fIN = 495MHz 67 67 67 dBc fIN = 605MHz 65 64 57 dBc 88 94 100 dBc fIN = 105MHz 89 95 94 dBc fIN = 190MHz 87 91 89 dBc fIN = 363MHz 81 86 84 dBc fIN = 495MHz 79 87 80 dBc fIN = 605MHz 75 83 77 dBc fIN = 70MHz 96 97 96 dBFS fIN = 170MHz 87 86 87 dBFS 10-13 10-13 620 620 SFDRX23 fIN = 30MHz Intermodulation Distortion TYP ISLA216S20 Word Error Rate WER 10-13 Full Power Bandwidth FPBW 620 MHz NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. PSRR is calculated by the equation 20*log10(A/B), where B is the amplitude of a disturber sinusoid on AVDD at the device pins, and A is the amplitude of the spur in the captured data at the frequency of the disturber sinusoid. 8. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to “Power-On Calibration” on page 14 and “User Initiated Reset” on page 15 for more detail. 9. The DLL Range setting must be changed via SPI for ADC core sample rates below 80MSPS. The JESD204 transmitter can support ADC sample rates below 100MSPS, as long as the lane data rate is greater than or equal to 1Gbps. 10. Minimum specification guaranteed when calibrated at +85°C. Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS CMOS INPUTS Input Current High (RESETN) IIH VIN = 1.8V Input Current Low (RESETN) IIL VIN = 0V Input Current High (SDIO, SCL, SDA SCLK) IIH VIN = 1.8V Input Current Low (SDIO, SCL, SDA SCLK) IIL VIN = 0V Input Current High (CSB) IIH VIN = 1.8V Input Current Low (CSB) IIL VIN = 0V Input Voltage High (SDIO, RESETN) VIH Input Voltage Low (SDIO, RESETN) VIL Input Current High (NAPSLP, CLKDIV) (Note 11) IIH 19 Input Current Low (NAPSLP, CLKDIV) IIL --30 7 1 10 µA -12 -7 µA 4 12 µA -600 -400 -300 µA 40 52 70 µA 1 10 µA -25 1.17 V 0.63 V 25 30 µA -25 -19 µA FN7996.0 February 2, 2012 ISLA216S Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL Input Capacitance MIN (Note 6) CONDITIONS TYP CDI MAX (Note 6) UNITS 4 pF LVDS INPUTS (SYNCP, SYNCN) Input Common Mode Range VICM 825 1575 mV Input Differential Swing (peak-to-peak, single-ended) VID 250 450 mV Input Pull-up and Pull-down Resistance RIpu 100 kΩ 1.14 V CML OUTPUTS Output Common Mode Voltage Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL CONDITION MIN (Note 6) TYP MAX (Note 6) UNITS ADC OUTPUT Aperture Delay tA 190 ps RMS Aperture Jitter jA 100 fs 250 µs L 10 cycles tOVR 1 cycles PLL Lock Time 295 µs PLL Bandwidth 2.2 MHz Added Random Jitter 5 ps RMS Added Deterministic Jitter 7 ps P-P 5 ps rms 75 ps Synchronous Clock Divider Reset Recovery Time (Note 12) Latency (ADC Pipeline Delay) Overvoltage Recovery tRSTRT DLL recovery time after Synchronous Reset SERDES Maximum Input Sample Clock Total Jitter to Maintain SERDES BER <1E-12 Integrated from 1kHz to 10MHz offset from carrier LVDS Inputs SYNCP, SYNCN Setup Time (with Respect to the Positive Edge of CLKP) tRSTS AVDD, OVDD = 1.7V to 1.9V, TA = -40°C to +85°C SYNCP, SYNCN Hold Time (with respect to the positive edge of CLKP) tRSTH AVDD, OVDD = 1.7V to 1.9V, TA = -40°C to +85°C 400 150 350 ps CML Outputs Output Rise Time tR 165 ps Output Fall Time tF 145 ps Data Output Duty Cycle 50 % Differential Output Resistance 100 Ω 8 FN7996.0 February 2, 2012 ISLA216S Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL MIN (Note 6) CONDITION MAX (Note 6) TYP Differential Output Voltage (Note 13) 760 UNITS mVP-P SPI INTERFACE (Notes 14, 15) SCLK Period t CLK Write Operation 7 cycles tCLK Read Operation 16 cycles CSB↓ to SCLK↑ Setup Time tS Read or Write 2 cycles CSB↑ after SCLK↑ Hold Time tH Read or Write 5 cycles Data Valid to SCLK↑ Setup Time tDS Read or Write 6 cycles Data Valid after SCLK↑ Hold Time tDH Read or Write 4 cycles Data Valid after SCLK↓ Time tDVR Read 4 cycles NOTES: 11. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending on desired function. 12. The synchronous clock divider reset function is available as a (SPI-programmable) overload on the SYNC input. 13. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak single-ended swing is 1/2 of the differential swing. 14. The SPI interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled proportionally for lower sample rates. ADC sample clock must be running for SPI communication. 15. The SPI may operate asynchronously with respect to the ADC sample clock. Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. -55 SFDR AT 200 MSPS HD2 AND HD3 MAGNITUDE (dBc) SNR (dBFS) AND SFDR (dBc) 95 90 SFDR AT 250 MSPS 85 SFDR AT 130 MSPS 80 75 70 SNR AT 250 MSPS 65 SNR AT 130 MSPS 60 SNR AT 200 MSPS 55 50 0 100 200 300 400 500 INPUT FREQUENCY (MHz) FIGURE 3. SNR AND SFDR vs fIN 9 600 700 HD2 AT 200 MSPS -60 HD2 AT 130 MSPS -65 -70 -75 HD2 AT 250 MSPS -80 -85 -90 -95 HD3 AT 200 MSPS -100 -105 HD3 AT 250 MSPS HD3 AT 130 MSPS 0 100 200 300 400 500 600 700 INPUT FREQUENCY (MHz) FIGURE 4. HD2 AND HD3 vs fIN FN7996.0 February 2, 2012 ISLA216S Typical Performance Curves (Continued) All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued) -40 100 HD2 AND HD3 MAGNITUDE SNR (dBFS) SNR AND SFDR 80 SFDR (dBc) 60 40 20 SNR (dBc) 0 -60 -50 HD3 (dBc) -50 SFDR (dBFS) HD2 (dBc) -60 -70 -80 -90 HD3 (dBFS) -100 -110 -40 -30 -20 INPUT AMPLITUDE (dBFS) -10 HD2 (dBFS) -120 -60 0 90 -10 0 85 HD2 AND HD3 MAGNITUDE (dBc) -75 SFDR 80 75 SNR 70 65 60 100 120 140 160 180 200 220 240 260 -80 HD3 -85 -90 -95 HD2 -100 -105 -110 100 280 120 140 1.0 900 0.8 800 0.6 700 0.4 DNL (LSBs) 1000 600 500 400 -0.6 100 -0.8 180 200 220 SAMPLE RATE (MSPS) FIGURE 9. POWER vs fSAMPLE 10 240 260 280 0 200 160 220 -0.2 -0.4 140 200 0.2 300 120 180 FIGURE 8. HD2 AND HD3 vs fSAMPLE FIGURE 7. SNR AND SFDR vs fSAMPLE 0 100 160 SAMPLE RATE (MSPS) SAMPLE RATE (MSPS) TOTAL POWER (mW) -40 -30 -20 INPUT AMPLITUDE (dBFS) FIGURE 6. HD2 AND HD3 vs AIN FIGURE 5. SNR AND SFDR vs AIN SNR (dBFS) AND SFDR (dBc) -50 240 260 -1.0 0 10000 20000 30000 40000 50000 60000 CODE FIGURE 10. DIFFERENTIAL NONLINEARITY FN7996.0 February 2, 2012 ISLA216S Typical Performance Curves (Continued) All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued) 15 90 SNR (dBFS) AND SFDR (dBc) 10 INL (LSBs) 5 0 -5 -10 -15 -20 0 10000 20000 30000 40000 50000 85 SFDR 80 75 SNR 70 65 60 700 60000 800 900 1000 CODE FIGURE 11. INTEGRAL NONLINEARITY 1300 1400 1500 FIGURE 12. SNR AND SFDR vs VCM 140000 0 AMPLITUDE (dBFS) 120000 100000 80000 60000 40000 AIN = -2.0 dBFS SNR = 75.1 dBFS -20 SFDR = 84 dBc SINAD = 74.7 dBFS -40 -60 -80 6 8 75 0 20 32 4 75 32 2 75 32 0 75 32 8 75 32 6 74 32 4 74 32 2 74 32 0 74 32 8 74 32 6 73 32 4 73 32 2 32 32 73 -120 0 0 73 -100 73 20000 32 NUMBER OF HITS 1100 1200 Vcm (mV) 40 60 80 100 120 FREQUENCY (MHz) ADC CODE FIGURE 14. SINGLE-TONE SPECTRUM @ 105MHz FIGURE 13. NOISE HISTOGRAM 0 AIN = -2.0 dBFS SNR = 74.1 dBFS -20 SFDR = 82 dBc SINAD = 73.4 dBFS AIN = -2.0 dBFS SNR = 71.9 dBFS SFDR = 75 dBc SINAD = 70.5 dBFS -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 -40 -60 -80 -100 -40 -60 -80 -100 -120 0 20 40 60 80 100 FREQUENCY (MHz) FIGURE 15. SINGLE-TONE SPECTRUM @ 190MHz 11 120 -120 0 20 40 60 80 FREQUENCY (MHz) 100 120 FIGURE 16. SINGLE-TONE SPECTRUM @ 363MHz FN7996.0 February 2, 2012 ISLA216S Typical Performance Curves (Continued) All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued) 0 0 IMD = -87 dBFS IMD = -96 dBFS -20 MAGNITUDE (dBFS) MAGNITUDE (dBFS) -20 -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 20 40 60 80 100 120 FREQUENCY (MHz) FIGURE 17. TWO-TONE SPECTRUM (F1 = 70MHz, F2 = 71MHz AT -7dBFS) 0 20 40 60 80 100 FIGURE 18. TWO-TONE SPECTRUM (F1 = 170MHz, F2 = 171MHz AT -7dBFS) FIGURE 19. SERDES DATA EYE at 1.0Gbps FIGURE 20. SERDES DATA EYE at 3.0Gbps FIGURE 21. SERDES DATA EYE at 4.375Gbps FIGURE 22. SERDES BATHTUB at 1.0Gbps 12 120 FREQUENCY (MHz) FN7996.0 February 2, 2012 ISLA216S Typical Performance Curves (Continued) All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued) FIGURE 23. SERDES BATHTUB at 3.0Gbps FIGURE 24. SERDES BATHTUB at 4.375Gbps FIGURE 25. SERDES HISTOGRAM at 1.0Gbps FIGURE 26. SERDES HISTOGRAM at 3.0Gbps FIGURE 27. SERDES HISTOGRAM at 4.375Gbps 13 FN7996.0 February 2, 2012 ISLA216S Theory of Operation A user-initiated reset can subsequently be invoked in the event that the above conditions cannot be met at power-up. Functional Description The ISLA216S is based upon a 16-bit, 250MSPS ADC converter core that utilizes a pipelined successive approximation architecture (see Figure 28). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. Decisions made during the successive approximation operations determine the digital code for each input value. Digital error correction is also applied. Power-On Calibration The ADC core(s) perform a self-calibration at start-up. An internal power-on-reset (POR) circuit detects the supply voltage ramps and initiates the calibration when the analog and digital supply voltages are above a threshold. The following conditions must be adhered to for the power-on calibration to execute successfully: • A frequency-stable conversion clock must be applied to the CLKP/CLKN pins After the power supply has stabilized, the internal POR releases RESETN and an internal pull-up pulls it high, which starts the calibration sequence. If a subsequent user-initiated reset is desired, the RESETN pin should be connected to an open-drain driver with an off-state/high impedance state leakage of less than 0.5mA to assure exit from the reset state so calibration can start. The calibration sequence is initiated on the rising edge of RESETN, as shown in Figure 29. Calibration status can be determined by reading the cal_status bit (LSB) at 0xB6. This bit is ‘0’ during calibration and goes to a logic ‘1’ when calibration is complete. During calibration the JESD204 transmitter PLL is not locked to the ADC sample clock, so the CML outputs will toggle at an undetermined rate. Normal operation is resumed once calibration is complete. At 250MSPS the nominal calibration time is 280ms, while the maximum calibration time is 550ms. • DNC pins must not be connected • SDO has an internal pull-up and should not be driven externally • RESETN is pulled low by the ADC internally during POR. External driving of RESETN is optional. • SPI communications must not be attempted during calibration, with the only exception of performing read operations on the cal_done register at address 0xB6. CLOCK GENERATION INP 2.5-BIT FLASH SHA INN 1.25V + – 2.5-BIT FLASH 6- STAGE 1.5-BIT/ STAGE 3- STAGE 1-BIT/ STAGE 3-BIT FLASH DIGITAL ERROR CORRECTION FIGURE 28. ADC CORE BLOCK DIAGRAM 14 FN7996.0 February 2, 2012 ISLA216S The performance of the ISLA216S changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements. Best performance will be achieved by recalibrating the ADC under the environmental conditions at which it will operate. CLKN CLKP CALIBRATION TIME RESETN CAL_STATUS BIT CALIBRATION BEGINS A supply voltage variation of <100mV will generally result in an SNR change of <0.5dBFS and SFDR change of <3dBc. In situations where the sample rate is not constant, best results will be obtained if the device is calibrated at the highest sample rate. Reducing the sample rate by less than 80MSPS will typically result in an SNR change of <0.5dBFS and an SFDR change of <3dBc. CALIBRATION COMPLETE FIGURE 29. CALIBRATION TIMING User Initiated Reset Figures 30 through 32 show the affect of temperature on SNR and SFDR performance with power on calibration performed at -40°C, +25°C, and +85°C. Each plot shows the variation of SNR/SFDR across temperature after a single power on calibration at -40°C, +25°C and +85°C. Best performance is typically achieved by a user-initiated power on calibration at the operating conditions, as stated earlier. However, it can be seen that performance drift with temperature is not a very strong function of the temperature at which the power on calibration is performed. Recalibration of the ADC can be initiated at any time by driving the RESETN pin low for a minimum of one clock cycle. An open-drain driver with a drive strength in its high impedance state of less than 0.5mA is recommended, as RESETN has an internal high impedance pull-up to OVDD. As is the case during power-on reset, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. Temperature Calibration 90 90 SFDR, 200MSPS SNR (dBFS) AND SFDR (dBc) SNR (dBFS) AND SFDR (dBc) SFDR, 200MSPS 85 SFDR, 250MSPS SFDR, 130MSPS 80 75 SNR, 250MSPS SNR, 130MSPS SNR, 200MSPS 70 65 60 -40 -35 -30 -25 TEMPERATURE (°C) 85 FIGURE 30. TYPICAL SNR AND SFDR PERFORMANCE vs TEMPERATURE, DEVICE CALIBRATED AT -40°C, fIN = 105MHz SFDR, 130MSPS 75 SNR, 250MSPS 70 SNR, 130MSPS SNR, 200MSPS 65 60 -20 SFDR, 250MSPS 80 5 15 25 35 TEMPERATURE (°C) 45 FIGURE 31. TYPICAL SNR AND SFDR PERFORMANCE vs TEMPERATURE, DEVICE CALIBRATED AT +25°C, fIN = 105MHz SNR (dBFS) AND SFDR (dBc) 95 SFDR, 200MSPS 90 85 SFDR, 250MSPS 80 SFDR, 130MSPS 75 SNR, 250MSPS 70 SNR, 130MSPS SNR, 200MSPS 65 60 65 70 75 80 85 TEMPERATURE (°C) FIGURE 32. TYPICAL SNR AND SFDR PERFORMANCE vs TEMPERATURE, DEVICE CALIBRATED AT +85°C, fIN = 105MHz 15 FN7996.0 February 2, 2012 ISLA216S Analog Input A single fully differential input (VINP/VINN) connects to the sample and hold amplifier (SHA) of each unit ADC. The ideal full-scale input voltage is 2.0V, centered at the VCM voltage as shown in Figure 33. ADC VINN 1.8 VINP 1.4 VCM 1.0V 1.0 FIGURE 36. DIFFERENTIAL AMPLIFIER INPUT 0.6 0.2 FIGURE 33. ANALOG INPUT RANGE Best performance is obtained when the analog inputs are driven differentially. The common-mode output voltage, VCM, should be used to properly bias the inputs as shown in Figures 34 through 36. An RF transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (IF) inputs. Two different transformer input schemes are shown in Figures 34 and 35. ADT1-1WT ADT1-1WT 1000pF ADC VCM 0.1µF FIGURE 34. TRANSFORMER INPUT FOR GENERAL PURPOSE APPLICATIONS ADTL1-12 TX-2-5-1 1000pF ADC A differential amplifier, as shown in the simplified block diagram in Figure 36, can be used in applications that require DC-coupling. In this configuration, the amplifier will typically dominate the achievable SNR and distortion performance. Intersil’s new ISL552xx differential amplifier family can also be used in certain AC applications with minimal performance degradation. Contact the factory for more information. When an over range occurs, the data sample output bits are held at full scale (all 0’s or all 1’s), thus allowing the detection of this condition in the receiver device. Clock Input The clock input circuit is a differential pair (see Figure 49). Driving these inputs with a high level (up to 1.8VP-P on each input) sine or square wave will provide the lowest jitter performance. A transformer with 4:1 impedance ratio will provide increased drive levels. The clock input is functional with AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the lowest possible aperture jitter, it is recommended to have high slew rate at the zero crossing of the differential clock input signal. The recommended drive circuit is shown in Figure 37. A duty range of 40% to 60% is acceptable. The clock can be driven single-ended, but this will reduce the edge rate and may impact SNR performance. The clock inputs are internally self-biased to AVDD/2 through a Thevenin equivalent of 10kΩ to facilitate AC coupling. TC4-19G2+ VCM 1000pF CLKP 1000pF FIGURE 35. TRANSMISSION-LINE TRANSFORMER INPUT FOR HIGH IF APPLICATIONS This dual transformer scheme is used to improve common-mode rejection, which keeps the common-mode level of the input matched to VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the ISLA216S is 300Ω. The SHA design uses a switched capacitor input stage (see Figure 48), which creates current spikes when the sampling capacitance is reconnected to the input voltage. This causes a disturbance at the input, which must settle before the next sampling point. Lower source impedance will result in faster settling and improved performance. Therefore a 2:1 or 1:1 transformer and low shunt resistance are recommended for optimal performance. 16 200 0.01µF CLKN 1000pF 1000pF FIGURE 37. RECOMMENDED CLOCK DRIVE A selectable 2x or 4x frequency divider is provided in series with the clock input. The divider can be used in the 2x mode with a sample clock equal to twice the desired sample rate or in 4x mode with a sample clock equal to four times the desired sample rate. Use of the 2x or 4x frequency divider enables the use of the Phase Slip feature, which enables the system to be able to select the phase of the divide by 2 or divide by 4 that causes the ADC to sample the analog input. FN7996.0 February 2, 2012 ISLA216S Voltage Reference TABLE 1. CLKDIV PIN SETTINGS CLKDIV PIN DIVIDE RATIO AVSS 2 Float 1 AVDD 4 A temperature compensated internal voltage reference provides the reference charges used in the successive approximation operations. The full-scale range of each ADC is proportional to the reference voltage. The nominal value of the voltage reference is 1.25V. The clock divider can also be controlled through the SPI port, which overrides the CLKDIV pin setting. See “SPI Physical Interface” on page 22. A delay-locked loop (DLL) generates internal clock signals for various stages within the charge pipeline. If the frequency of the input clock changes, the DLL may take up to 52μs to regain lock at 250MSPS. The lock time is inversely proportional to the sample rate. The DLL has two ranges of operation, slow and fast. The slow range can be used for ADC core sample rates between 40MSPS and 100MSPS, while the default fast range can be used from 80MSPS to the maximum specified sample rate. The lane data rate is related to the ADC core sample rate by a relationship that is defined by the JESD204 transmitter configuration, and has additional frequency constraints; see“JESD204A Transmitter” on page 18 for additional details. Jitter In a sampled data system, clock jitter directly impacts the achievable SNR performance. The theoretical relationship between clock jitter (tJ) and SNR is shown in Equation 1 and is illustrated in Figure 38. 1 SNR = 20 log 10 ⎛ -------------------⎞ ⎝ 2πf t ⎠ IN J (EQ. 1) 100 95 tj = 0.1ps 90 14 BITS SNR (dB) 85 80 tj = 1ps 75 tj = 10ps 60 10 BITS tj = 100ps 55 50 1M 10M 100M INPUT FREQUENCY (Hz) The digital outputs are in CML format, and feature analog and digital characteristics compliant with the JESD204A standard requirements. Power Dissipation The power dissipated by the device is dependent on the ADC sample rate and the number of active lanes in the link. There is a fixed bias current drawn from the analog supply for the ADC, along with a fixed bias current drawn from the digital supply for each active lane. The remaining power dissipation is linearly related to the sample rate. Nap/Sleep Portions of the device may be shut down to save power during times when operation of the ADC is not required. Two power saving modes are available: Nap, and Sleep. Nap mode reduces power dissipation significantly while taking a very short time to return to functionality. Sleep mode reduces power consumption drastically while taking longer to return to functionality. In Nap mode the JESD204 lanes will continue to produce valid encoded data, allowing the link to remain active and thus return to a functional state quickly. The data transmitted over the lanes in nap mode is the last valid ADC sample, repeated until leaving nap mode. The 8b/10b encoder’s running disparity will prevent the potentially long time repetition of this last valid sample from creating DC bias on the lane. In sleep mode the JESD204 lanes will be deactivated to conserve power. Thus, sometime after wake up code group alignment will be required to reestablish the link. The input clock should remain running and at a fixed frequency during Nap or Sleep, and CSB should be high. The JESD204 link will only remain established during nap mode if the input clock continues to remain stable during the nap period. 12 BITS 70 65 Digital Outputs 1G FIGURE 38. SNR vs CLOCK JITTER This relationship shows the SNR that would be achieved if clock jitter were the only non-ideal factor. In reality, achievable SNR is limited by internal factors such as linearity, aperture jitter and thermal noise as well. Internal aperture jitter is the uncertainty in the sampling instant. The internal aperture jitter combines with the input clock jitter in a root-sum-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. The total jitter, combined with other noise sources, then determines the achievable SNR. By default after the device is powered on, the operational state is controlled by the NAPSLP pin as shown in Table 2. Please note that power on calibration occurs at power up time regardless of the state of the NAPSLP pin; immediately following this power on calibration routine the device will enter nap or sleep state if the NAPSLP pin voltage dictates it is to do so. TABLE 2. NAPSLP PIN SETTINGS NAPSLP PIN MODE AVSS Normal Float Nap AVDD Sleep The power-down mode can also be controlled through the SPI port, which overrides the NAPSLP pin setting. Details on this are contained in “Serial Peripheral Interface” on page 22. 17 FN7996.0 February 2, 2012 ISLA216S Data Format . Output data can be presented in three formats: two’s complement(default), Gray code and offset binary. The data format can be controlled through the SPI port by writing to address 0x73. Details on this are contained in “Serial Peripheral Interface” on page 22. Offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the most positive input to 0xFFF (all ones). Two’s complement coding simply complements the MSB of the offset binary representation. When calculating Gray code the MSB is unchanged. The remaining bits are computed as the XOR of the current bit position and the next most significant bit. Figure 39 shows this operation. BINARY 13 12 11 •••• 1 0 •••• GRAY CODE 13 12 •••• 11 1 0 FIGURE 39. BINARY TO GRAY CODE CONVERSION Converting back to offset binary from Gray code must be done recursively, using the result of each bit for the next lower bit as shown in Figure 40. GRAY CODE 13 12 11 •••• 1 0 •••• TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING INPUT VOLTAGE OFFSET BINARY TWO’S COMPLEMENT GRAY CODE –Full Scale 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 –Full Scale 00 0000 0000 0001 10 0000 0000 0001 00 0000 0000 0001 + 1LSB Mid–Scale 10 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000 +Full Scale 11 1111 1111 1110 01 1111 1111 1110 10 0000 0000 0001 – 1LSB +Full Scale 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 Clock Divider Synchronous Reset The function of clock divider synchronous reset is available as a SPI-programmable overloaded function on the SYNCP and SYNCN pins. Given that the clock divider reset and SYNC features have the same electrical and timing requirements, this overloading allows the system to generate only a single well timed signal with respect to the ADC sample clock and select the ADC’s interpretation of the signal as a SPI-programmable option (see SPI register 0x77 description for more information). By default the SYNCP and SYNCN pins will function as the JESD204A SYNC~. The use of clock divider reset function is a requirement in a system that uses the ISLA214S50, ISLA214S35, or CLKDIV = 2 or 4 and also requires time alignment or deterministic latency of multiple devices. Please contact the factory for more details about this feature and its usage. Soft Reset Soft reset is a function intended to be used when the power on reset is to be re-run. An application may decide to issue a soft calibration command after significant temperature change or after a change in the sample rate frequency to optimize performance under the new condition. Soft reset is issued by writing the Soft Reset bit at SPI address 0x00. Soft reset is a self-resetting bit in that will automatically return to 0 once the power on calibration has completed. JESD204A Transmitter Overview •••• BINARY 13 12 11 •••• 1 FIGURE 40. GRAY CODE TO BINARY CONVERSION Mapping of the input voltage to the various data formats is shown in Table 3. 18 0 The conversion data is presented by a JESD204B-compliant SERDES interface. The SERDES lane data rate supports typical speeds up to 4.375Gbps, exceeding the 3.125Gbps maximum specified by the JESD204 rev A standard. A SYNC input is included, which is used for lane initialization as well as time alignment of multiple converter devices. AC coupling of the SERDES lane(s) on the board is required. A block diagram of this SERDES transmitter is shown in Figure 41. For more information about the standardized characteristics and features of a JESD204 interface, please see JESD204 rev A and rev B standards. For application design support, including evaluation kit schematics and layout, reference FPGA project(s), and simulation models for functionality and signal integrity, please contact the factory and/or view application notes at http://www.intersil.com/contacts/. FN7996.0 February 2, 2012 ISLA216S SERDES Block Link Layer Analog Input Sample Data Transport Layer Scrambler 1+x14+x15 Encoder 8/10 Lane 0 SER Logic Sample Clock PLL Multiply Clock Management - Code group Synchronization - Alignment Characters - Initial Lane Synchronization - Etc SYNC Link Layer Lane 1 FIGURE 41. SERDES TRANSMITTER BLOCK DIAGRAM See Table 4 on page 20 for the full list of programmable JESD204 parameters. Via SPI, the JESD204 transmitter is highly configurable, supporting user configuration of the transmitter. Please contact the factory for a full list of downgradeable configurations that are supported. Signal integrity plots, including data eye, BER bathtub curves, and edge histogram plots versus lane data rate can be found in the typical operating curves section. Initial Lane Alignment The link initialization process is started by asserting the SYNC~ signal to the ADC device. This assertion causes the JESD204 transmitter to generate comma characters, which are used by the receiver to accomplish code group synchronization (bit and octet alignment, respectively). Once code group synchronization is detected in the receiver, it de-asserts the SYNC~ signal, causing the JESD204 transmitter to generate the initial lane alignment sequence (ILA). The ILA is comprised of 4 multi-frames of data in a standard format, with the length of each multi-frame determined by the K parameter as programmed into the SPI JESD204A parameter table. The ILA includes standard control character markers that can be used to perform channel bonding in the receiving device if desired. The 2nd multi-frame includes the full JESD204A parameter data, allowing the receiver to auto-detect the lane configuration if desired. After completion of the ILA the JESD204 transmitter begins transmitting ADC sample data. Continuous link and lane alignment monitoring is accomplished via an octet substitution scheme. The last octet in each frame, if identical to the last octet in the previous frame, is replaced with a specific control character. If both sides of the link support lane synchronization, the last octet in each multi-frame, if identical to the last octet in 19 the previous frame, is replaced with a different specific control character. A more complete description of the link initialization sequence, including finite state machine implementation, can be found in the JESD204 rev A standard. LANE DATA RATE The lane data rate for this product family is constrained to be greater than or equal to 1Gbps and less than or equal to 3.125Gbps for guaranteed operation, so as to be consistent with the lane data rate limit of 3.125Gbps set by the JESD204 rev A standard. The lane data rate can typically exceed 4.2Gbps for this product family. SCRAMBLER The bypassable scrambler is compliant with the scrambler defined in the JESD204 rev A standard. This implementation seeds the scrambler with the initial lane alignment sequence, such that the first two octets following the sequence can be properly descrambled if the receiver also passes the lane alignment sequence through its descrambler. Even if the receiver does not implement this detail, the 3rd and subsequent octets can be descrambled to yield ADC data due to the self-synchronizing nature of the scrambler used. MULTI-CHIP TIME ALIGNMENT The JESD204 standard (in various revisions) provides the capability to time align multiple JESD204 ADC devices to a single logic device (FPGA or ASIC). This feature is critical in many applications that cannot tolerate the variable latency of the JESD204 link, and that must process pipeline depth correct data from more than one ADC device. FN7996.0 February 2, 2012 ISLA216S Time alignment of multiple devices provides the capability to align samples from multiple JESD204 ADC devices in the system in a pipeline-depth correct manner, thus enabling the system to analyze the ADC data from multiple devices while eliminating the variable latency of the JESD204 link as a concern. This capability enables configurations of JESD204 ADCs as IQ, interleave, and/or simultaneously-sampled converters. This ADC family uses the asserted to de-asserted SYNC~ transition as the absolute time event with which to generate a known sequence of characters at the JESD204 transmitter of equal pipeline depth between all ADC devices in the system to be time aligned. This is consistent with the JESD204 rev B subclass 2 device definition. Test Patterns The complexity of the JESD204 interface merits much more test pattern capability than less complex parallel interfaces. This device family consequently supports a much wider range of test patterns than previous ADC families. Supported test patterns include both transport and link layer patterns. Transport layer patterns are passed through the transport layer of the JESD204 transmitter, following the same sequence of being packed and sliced into octets as the ADC sample data. Link layer test patterns bypass the transport layer and are injected directly into the 8b/10b encoder, serialized, and sent out of the physical media. Test pattern generation is controlled through SPI register 0xC0. Link layer PRBS patterns are standard PRBS patterns that can be used with built-in standard PRBS checkers in, for example, FPGA SERDES-capable pins. All transport layer test patterns re-initialize their phase when the SYNC~ de-assertion occurs; consequently, a system that provides a well-timed SYNC~ signal with respect to the ADC sample clock can expect transport layer test patterns to have consistent phase with respect to that de-assertion, which can be a significant aid when debugging the system. TABLE 4. JESD204A PARAMETERS PRODUCT ISLA216S25 ISLA216S20 ISLA216S13 NUMBER OF LANES 2 JESD204 PARAMETER ENCODED CF = 0 0 CS = 0 0 F=2 1 HD = 0 0 L=2 1 M=1 0 N = 16 15 N' = 16 15 S=2 1 K >= 9 >= 8 JESD204A PARAMETERS AND FRAME MAP (Notes 16, 17, 18) C0S0[15:8] C0S0[7:0] C0S1[15:8] C0S1[8:0] NOTES: 16. The JESD204A parameters are shown as their actual values, with the JESD204 encoded values (i.e., the values that are programmed into the SPI registers) in the next column over. Typically values that must always be greater than 1 are encoded as value minus 1, and so on. 17. Frame map format decoder: "CxSy[a:b]" = Converter x, Sample y, bits a through b. For example, "C0S0[13:6]" = Converter 0, Sample 0, bits 13 through 6, etc. "T" = Tail bit (information-less bit packed in the transport layer mapping to form octets). 18. The topmost lane in the graphical frame map is Lane0, followed by Lane1. 20 FN7996.0 February 2, 2012 ISLA216S CSB SCLK SDIO R/W W1 W0 A12 A11 A1 A10 A0 D7 D6 D5 D4 D3 D2 D1 D0 D2 D3 D4 D5 D6 D7 FIGURE 42. MSB-FIRST ADDRESSING CSB SCLK SDIO A0 A1 A11 A2 A12 W0 W1 R/W D1 D0 FIGURE 43. LSB-FIRST ADDRESSING tDSW CSB tCLK tHI tDHW tS tH tLO SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 SPI WRITE FIGURE 44. SPI WRITE tDSW CSB tCLK tHI tDHW tH tDVR tS tLO SCLK WRITING A READ COMMAND READING DATA ( 3 WIRE MODE ) SDIO R/W W1 W0 A12 A11 A10 A9 A2 A1 A0 D7 SDO D6 D3 D2 D1 D0 ( 4 WIRE MODE) D7 D3 D2 D1 D0 SPI READ FIGURE 45. SPI READ 21 FN7996.0 February 2, 2012 ISLA216S CSB STALLING CSB SCLK SDIO INSTRUCTION/ADDRESS DATA WORD 1 DATA WORD 2 FIGURE 46. 2-BYTE TRANSFER LAST LEGAL CSB STALLING CSB SCLK SDIO INSTRUCTION/ADDRESS DATA WORD 1 DATA WORD N FIGURE 47. N-BYTE TRANSFER Serial Peripheral Interface A serial peripheral interface (SPI) bus is used to facilitate configuration of the device and to optimize performance. The SPI bus consists of chip select (CSB), serial clock (SCLK) serial data output (SDO), and serial data input/output (SDIO). The maximum SCLK rate is equal to the ADC sample rate (fSAMPLE) divided by 7 for write operations and fSAMPLE divided by 16 for reads. There is no minimum SCLK rate. The following sections describe various registers that are used to configure the SPI or adjust performance or functional parameters. Many registers in the available address space (0x00 to 0xFF) are not defined in this document. Additionally, within a defined register there may be certain bits or bit combinations that are reserved. Undefined registers and undefined values within defined registers are reserved and should not be selected. Setting any reserved register or value may produce indeterminate results. SPI Physical Interface The serial clock pin (SCLK) provides synchronization for the data transfer. By default, all data is presented on the serial data input/output (SDIO) pin in three-wire mode. The state of the SDIO pin is set automatically in the communication protocol (described in the following). A dedicated serial data output pin (SDO) can be activated by setting 0x00[7] high to allow operation in four-wire mode. The SPI port operates in a half duplex master/slave configuration, with the ADC functioning as a slave. Multiple slave devices can interface to a single master in three-wire mode only, since the SDO output of an unaddressed device is asserted in four wire mode. The chip-select bar (CSB) pin determines when a slave device is being addressed. Multiple slave devices can be written to 22 concurrently, but only one slave device can be read from at a given time (again, only in three-wire mode). If multiple slave devices are selected for reading at the same time, the results will be indeterminate. The communication protocol begins with an instruction/address phase. The first rising SCLK edge following a high-to-low transition on CSB determines the beginning of the two-byte instruction/address command; SCLK must be static low before the CSB transition. Data can be presented in MSB-first order or LSB-first order. The default is MSB-first, but this can be changed by setting 0x00[6] high. Figures 42 and 43 show the appropriate bit ordering for the MSB-first and LSB-first modes, respectively. In MSB-first mode, the address is incremented for multi-byte transfers, while in LSB-first mode it’s decremented. In the default mode, the MSB is R/W, which determines if the data is to be read (active high) or written. The next two bits, W1 and W0, determine the number of data bytes to be read or written (see Table 5). The lower 13 bits contain the first address for the data transfer. This relationship is illustrated in Figure 44, and timing values are given in “Switching Specifications” on page 8. After the instruction/address bytes have been read, the appropriate number of data bytes are written to or read from the ADC (based on the R/W bit status). The data transfer will continue as long as CSB remains low and SCLK is active. Stalling of the CSB pin is allowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. For transfers of four bytes or more, CSB is allowed to stall in the middle of the instruction/address bytes or before the first data byte. If CSB transitions to a high state after that point the state machine will reset and terminate the data transfer. FN7996.0 February 2, 2012 ISLA216S TABLE 5. BYTE TRANSFER SELECTION Device Configuration/Control [W1:W0] BYTES TRANSFERRED 00 1 A common SPI map, which can accommodate single-channel or multi-channel devices, is used for all Intersil ADC products. ADDRESS 0X20: OFFSET_COARSE_ADC0 01 2 10 3 11 4 or more Figures 46 and 47 illustrate the timing relationships for 2-byte and N-byte transfers, respectively. The operation for a 3-byte transfer can be inferred from these diagrams. SPI Configuration ADDRESS 0X00: CHIP_PORT_CONFIG ADDRESS 0X21: OFFSET_FINE_ADC0 The input offset of the ADC core can be adjusted in fine and coarse steps. Both adjustments are made via an 8-bit word as detailed in Table 6. The data format is twos complement. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. Bit ordering and SPI reset are controlled by this register. Bit order can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB first) to accommodate various micro controllers. TABLE 6. OFFSET ADJUSTMENTS PARAMETER Bit 7 SDO Active Bit 6 LSB First Setting this bit high configures the SPI to interpret serial data as arriving in LSB to MSB order. Bit 5 Soft Reset 0x20[7:0] COARSE OFFSET 0x21[7:0] FINE OFFSET Steps 255 255 –Full Scale (0x00) -133LSB (-47mV) -5LSB (-1.75mV) Mid–Scale (0x80) 0.0LSB (0.0mV) 0.0LSB +Full Scale (0xFF) +133LSB (+47mV) +5LSB (+1.75mV) Nominal Step Size 1.04LSB (0.37mV) 0.04LSB (0.014mV) Setting this bit high resets all SPI registers to default values. ADDRESS 0X22: GAIN_COARSE_ADC0 Bit 4 Reserved This bit should always be set high. Bits 3:0 These bits should always mirror bits 4:7 to avoid ambiguity in bit ordering. ADDRESS 0X02: BURST_END If a series of sequential registers are to be set, burst mode can improve throughput by eliminating redundant addressing. The burst is ended by pulling the CSB pin high. Setting the burst_end address determines the end of the transfer. During a write operation, the user must be cautious to transmit the correct number of bytes based on the starting and ending addresses. Bits 7:0 Burst End Address This register value determines the ending address of the burst data. ADDRESS 0X23: GAIN_MEDIUM_ADC0 ADDRESS 0X24: GAIN_FINE_ADC0 Gain of the ADC core can be adjusted in coarse, medium and fine steps. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. Multiple Coarse Gain Bits can be set for a total adjustment range of ±4.2%. (‘0011’ ≅ -4.2% and ‘1100’ ≅ +4.2%) It is recommended to use one of the coarse gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the registers at 0x0023 and 0x24. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. Device Information TABLE 7. COARSE GAIN ADJUSTMENT 0x22[3:0] core 0 0x26[3:0] core 1 NOMINAL COARSE GAIN ADJUST (%) ADDRESS 0X09: CHIP_VERSION Bit3 +2.8 The generic die identifier and a revision number, respectively, can be read from these two registers. Bit2 +1.4 Bit1 -2.8 Bit0 -1.4 ADDRESS 0X08: CHIP_ID 23 FN7996.0 February 2, 2012 ISLA216S TABLE 8. MEDIUM AND FINE GAIN ADJUSTMENTS PARAMETER 0x23[7:0] MEDIUM GAIN 0x24[7:0] FINE GAIN Steps 256 256 –Full Scale (0x00) -2% -0.20% Mid–Scale (0x80) 0.00% 0.00% +Full Scale (0xFF) +2% +0.2% Nominal Step Size 0.016% 0.0016% clock signals gets used to cause the sampling event, by “slipping” the sampling event by one input clock period each time phase_slip is asserted. The clkdivrst feature can work in conjunction with phase_slip. After well-timed assertion of the clkdivrst signal (via overloading on the SYNC inputs), the sampling edge position with respect to the incoming clock rate will have been reset, allowing the system to “slip” whatever desired number of incoming clock periods from a known state. ADDRESS 0X72: CLOCK_DIVIDE ADDRESS 0X25: MODES Two distinct reduced power modes can be selected. By default, the tri-level NAPSLP pin can select normal operation, nap or sleep modes (refer to“Nap/Sleep” on page 17). This functionality can be overridden and controlled through the SPI. This register is not changed by a Soft Reset. The ADC has a selectable clock divider that can be set to divide by two or one (no division). By default, the tri-level CLKDIV pin selects the divisor This functionality can be overridden and controlled through the SPI, as shown in Table 10. This register is not changed by a Soft Reset. TABLE 10. CLOCK DIVIDER SELECTION TABLE 9. POWER-DOWN CONTROL VALUE 0x25[2:0] POWER DOWN MODE 000 Pin Control 001 Normal Operation 010 Nap Mode 100 Sleep Mode VALUE 0x72[2:0] CLOCK DIVIDER 000 Pin Control 001 Divide by 1 010 Divide by 2 other Not Allowed ADDRESS 0X26: OFFSET_COARSE_ADC1 ADDRESS 0X73: OUTPUT_MODE_A ADDRESS 0X27: OFFSET_FINE_ADC1 The output_mode_A register controls the logical coding of the sample data. Data can be coded in three possible formats: two’s complement(default), Gray code or offset binary. See Table 11. The input offset of ADC core#1 can be adjusted in fine and coarse steps in the same way that offset for core#0 can be adjusted. Both adjustments are made via an 8-bit word as detailed in Table 6. The data format is two’s complement. This register is not changed by a Soft Reset. TABLE 11. OUTPUT FORMAT CONTROL The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. ADDRESS 0X28: GAIN_COARSE_ADC1 ADDRESS 0X29: GAIN_MEDIUM_ADC1 ADDRESS 0X2A: GAIN_FINE_ADC1 Gain of ADC core #1 can be adjusted in coarse, medium and fine steps in the same way that core #0 can be adjusted. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. Multiple Coarse Gain Bits can be set for a total adjustment range of ±4.2. When using the clock_divide feature, the sample clock edge that the ADC uses to sample the analog input signal can be one of several different edges on the incoming higher frequency sample clock. For example, in clock_divide = 2 mode, every other incoming sample clock edge gets used by the ADC to sample the analog input. The phase_slip feature allows the system to control which edge of the incoming sample 24 0x73[2:0] OUTPUT FORMAT 000 Two’s Complement (Default) 010 Gray Code 100 Offset Binary ADDRESS 0X74: OUTPUT_MODE_B Bit 6 DLL Range This bit sets the DLL operating range to fast (default) or slow. Internal clock signals are generated by a delay-locked loop (DLL), which has a finite operating range. Table 12 shows the allowable sample rate ranges for the slow and fast settings. Global Device Configuration/Control ADDRESS 0X71: PHASE_SLIP VALUE TABLE 12. DLL RANGES DLL RANGE MIN MAX UNIT Slow 40 100 MSPS Fast 80 250 MSPS FN7996.0 February 2, 2012 ISLA216S ADDRESS 0X77: SYNC_FUNCTION ADDRESS 0XC5: USER_PATT3_LSB Bit 0 Clkdivrst ADDRESS 0XC6: USER_PATT3_MSB This bit controls the functionality of the SYNCP, SYNCN pins on this device. By default, this bit equals ‘0’, which means that the functionality of the SYNCP, SYNCN pins is the JESD204 SYNC. Setting this bit equal to ‘1’ modifies the functionality of the SYNCP, SYNCN pins to be clkdivrst, which is a synchronous divider reset on all internal dividers in the device. Usage of this clkdivrst functionality is required to support multi-chip time alignment and deterministic latency for devices that use interleaved product configurations (ISLA214S50 and ISLA214S35), and for any other product configuration that uses clkdiv > 1. In both states, the setup and hold times with respect to the sample clock remain the same. Contact the factory for more details. These registers define the lower and upper eight bits, respectively, of the user-defined pattern 3. ADDRESS 0XB6: CALIBRATION STATUS The LSB at address 0xB6 can be read to determine calibration status. The bit is ‘0’ during calibration and goes to a logic ‘1’ when calibration is complete.This register is unique in that it can be read after POR at calibration, unlike the other registers on chip, which can’t be read until calibration is complete. ADDRESS 0XC7: USER_PATT4_LSB ADDRESS 0XC8: USER_PATT4_MSB These registers define the lower and upper eight bits, respectively, of the user-defined pattern 4. ADDRESS 0XC9: USER_PATT5_LSB ADDRESS 0XCA: USER_PATT5_MSB These registers define the lower and upper eight bits, respectively, of the user-defined pattern 5. ADDRESS 0XCB: USER_PATT6_LSB ADDRESS 0XCC: USER_PATT6_MSB These registers define the lower and upper eight bits, respectively, of the user-defined pattern 6. ADDRESS 0XCD: USER_PATT7_LSB DEVICE TEST The device can produce preset or user defined patterns on the digital outputs to facilitate in-situ testing. A user can pick from preset built-in patterns by writing to the output test mode field [7:4] at 0xC0 or user defined patterns by writing to the user test mode field [2:0] at 0xC0. The user defined patterns should be loaded at address space 0xC1 through 0xD0, see the “SPI Memory Map” on page 27 for more detail. The test mode is enabled asynchronously to the sample clock, therefore several sample clock cycles may elapse before the data is present on the output bus. ADDRESS 0XC0: TEST_IO Bits 7:4 Output Test Mode These bits set the test mode according to the description in “SPI Memory Map” on page 27. Bits 2:0 User Test Mode The three LSBs in this register determine the test pattern in combination with registers 0xC1 through 0xD0. Refer to the “SPI Memory Map” on page 27. ADDRESS 0XC1: USER_PATT1_LSB ADDRESS 0XC2: USER_PATT1_MSB These registers define the lower and upper eight bits, respectively, of the user-defined pattern 1. ADDRESS 0XC3: USER_PATT2_LSB ADDRESS 0XC4: USER_PATT2_MSB These registers define the lower and upper eight bits, respectively, of the user-defined pattern 2 25 ADDRESS 0XCE: USER_PATT7_MSB These registers define the lower and upper eight bits, respectively, of the user-defined pattern 7. ADDRESS 0XCF: USER_PATT8_LSB ADDRESS 0XD0: USER_PATT8_MSB These registers define the lower and upper eight bits, respectively, of the user-defined pattern 8. ADDRESS 0xDF - 0xF3: JESD204 REGISTERS Address 0xDF-0xEE: JESD204A Parameter INTERFACE This set of registers controls the JESD204 transmitter configuration. By programming these parameters, the system can select between efficient and simple packing, select the number of powered up SERDES lanes, choose the ADC resolution transmitted, and so on. Contact the factory for details. 0xE0 through 0xED are the JESD204A parameter registers. These parameters are written to set the transport layer mapping of the JESD204 transmitter in this product family. These registers can be written to shift between efficient and simple packing, to enable or bypass scrambling, and to reduce the number of powered up lanes used in the link. Each speed graded product allows downgrading of the JESD204A link (such as reducing the number of lanes, reducing the converter resolution, etc), but not upgrading. These parameters are communicated on every lane of the link during the 2nd multi-frame of the initial lane alignment sequence, and therefore can be used by a generic JESD204A receiver the supports the given configuration. See the JESD204A specification for additional information on how these registers are used in a JESD204A system, including encoding rules. FN7996.0 February 2, 2012 ISLA216S ADDRESS 0XDF: JESD204_UPDATE_CONFIG_START Bit 0 update_start This self-resetting bit is used to indicate that some or all the JESD204A parameters (addresses 0xE0 through 0xED) are going to be written. Writing a ‘1’ to this bit will hold the JESD204A PLL and transmitter in a reset state while these parameters are written, because these parameters can affect the transmitter’s dynamic behavior (such as modifying the PLL’s frequency multiplication). The bit will automatically reset to a ‘0’ once a ‘1’ is written to address 0xEE Bit[0] “update_config W1TC”. The recommended sequence for modifying the JESD204A transmitter is: Bits 4:0 “S”, JESD204A Number of samples per converter per frame cycle. ADDRESS 0XEA: JESD204_CONFIG_10 Bit 7 “HD”, JESD204A HD indicates if a converter’s sample can be split across multiple lanes in the link (always ‘0’ for this product family). Bits 4:0 “CF”, JESD204A CF is the number of control fames per frame clock (always ‘0’ for this product family). ADDRESS 0XEB: JESD204_CONFIG_11 Bits 7:0 “RES1”, JESD204A reserved for future use. 1. Write a ‘1’ to 0xDF Bit[0] ADDRESS 0XEC: JESD204_CONFIG_12 2. Write some or all modified values to 0xE0 through 0xEC Bits 7:0 “RES2”, JESD204A reserved for future use. 3. Write a ‘1’ to 0xEE Bit[0]. Note: 0xDF Bit[0] and 0xEE Bit[0] will automatically be reset to a ‘0’ once configuration has been applied to the circuitry. ADDRESS 0XED: JESD204_CONFIG_13 ADDRESS 0XE0: JESD204_CONFIG_0 Bits 7:0 “DID”, JESD204A Device ID number. Bits 7:0 “FCHK” JESD204A checksum (unsigned sum MOD 256) of all the other JESD204A parameter register values. This is a read-only register, as the checksum is calculated by the device. ADDRESS 0XE1: JESD204_CONFIG_1 ADDRESS 0XEE: JESD204_UPDATE_CONFIG_COMPLETE Bits 3:0 “BID”, JESD204 Bank ID. Bit 0 update_complete ADDRESS 0XE2: JESD204_CONFIG_2 This self-resetting bit is used to indicate that all the modifications to the JESD204 parameters are complete. Bits 4:0 “LID” JESD204A Lane ID. ADDRESS 0XE3: JESD204_CONFIG_3 ADDRESS 0XEF: JESD204_PLL_MONITOR_RESET Bits 7:0 “F”, JESD204A Number of octets per frame period. Bit 0 “pll_lock_mon_rst”, This self resetting register resets the state of the 0xF0 Bit[0] “latched_pll_lockn” bit. The purpose of this pair of bits is as a debugging feature to the system designer. The “latched_pll_lockn” bit indicates if the JESD204A transmitter PLL inside the device has at any time lost lock since the last ‘1’ was written to the “pll_lock_mon_rst” bit. This can be used to help identify the source of intermittent link lost errors in the system. ADDRESS 0XE5: JESD204_CONFIG_5 ADDRESS 0XF0: JESD204_STATUS Bits 4:0 “K” JESD204A Number of frame periods per multi-frame period. This product family supports the full programmable range of K (decimal 0 through 31), although note that the JESD204A standard dictates a minimum number for this parameter that is configuration dependent. Bit 2 “op_cfg_wrong” indicates if the JESD204A parameters (registers 0xE0 through 0xED) are supported by the JESD204A transmitter (a ‘1’ indicates they are not supported, a ‘0’ indicates they are supported). Bit 7 “SCR”, JESD204A SCR controls if scrambling across the SERDES lane(s) is enabled (‘1’ means enabled). Bits 4:0 “L”, JESD204A L is the number of SERDES lanes in the link. ADDRESS 0XE4: JESD204_CONFIG_4 ADDRESS 0XE6: JESD204_CONFIG_6 Bits 7:0 “M” JESD204A Number of converters per device. ADDRESS 0XE7: JESD204_CONFIG_7 Bits 7:6 “CS”, JESD204A CS is the number of control bits per sample (Always ‘0’ for this product family). Bits 4:0 “N”, JESD204A N is the converter resolution. ADDRESS 0XE8: JESD204_CONFIG_8 Bits 4:0 “N’”, JESD204A N’ is the total number of bits per sample. ADDRESS 0XE9: JESD204_CONFIG_9 26 Bit 1“pll_lockn” indicates if the JESD204A transmitter PLL is currently locked (a ‘1’ indicates it is not locked, a ‘0’ indicates it is locked). Bit 0 “latched_pll_lockn” indicates if the JESD204A transmitter PLL has lost lock since the last assertion of the “pll_lock_mon_rst” (see register 0xEF description for more information). ADDRESS 0XF1: JESD204_SYNC Bit 0 “sync_req” this register provides a SPI-programmable interface that can be used to assert and de-assert the JESD204A SYNC~ functionality. Certain systems may benefit from the elimination of SYNC~ as a separate board-level LVDS signal (and the power, PCB space, and pins it consumes), and these systems can use this register to functionally assert and de-assert SYNC~. FN7996.0 February 2, 2012 ISLA216S For this bit to have any effect, a ‘1’ must have previously been written to the SYNC_FUNCTION (Address 0x77, bit 0). different control character when reoccurrence of octets occurs at the end of a multi-frame. A ‘1’ written to this bit will result in behavior identical to the assertion of SYNC~ (comma character generation), and ‘0’ will result in the behavior identical to the de-assertion of SYNC~ (initial lane alignment sequence followed by converter data). Usage of this SPI SYNC~ capability may compromise the system’s ability to perform multi-chip time alignment, as the SYNC~ asserted to de-asserted transition using this register is not well timed with respect to sample clock. Bit 1 “trans_pat_max_len” There is some ambiguity of the proper length of the JESD204 rev A section 5.1.6.2 required transport layer test pattern. Specifically, that the description perhaps should have “max()” in place of “min()” for the equation defining the length of the pattern. Setting bit 1 in this register to a ‘0’ (also the power-on default) and issuing this test pattern by writing to 0xC0 will cause the pattern to assume a “min()” interpretation of the pattern described in section 5.1.6.2. Setting the bit to a ‘1’ will assume a “max()” interpretation of the described pattern. ADDRESS 0XF2: JESD204_TRANS_PAT_CONFIG Bit 0 “no_mf_lane_sync”, By default, this device family assumes that both sides of the link support lane synchronization. As per the JESD204 rev A standard, in this case continuous frame alignment monitoring via character substitution (section 5.3.3.4) is modified such that a different control character is substituted when the octet reoccurrence happens at the end of a multiframe. This behavior occurs when bit 0 is ‘0’ (the power on default). Writing a ‘1’ to bit 0 will inform the JESD204 transmitter than the receiving device does not support lane synchronization, and therefore the transmitter will no longer substitute this ADDRESS 0XF3: JESD204_CML_POLARITY 0xF3 Bit[2:0]: “TX polarity flip lane x” This register allows the system designer to invert the sense of the SERDES pins on a per lane basis. For example, writing a ‘1’ to Bit[0] causes LANE0N to functionally become LANE0P and LANE0P to become LANE0N. This feature allows the system designer to avoid having to crossover P and N sides of the CML pair on the board to match pin out and layout of the transmitter and receiver. Typically, a trace crossover would require vias, which can degrade the signal integrity of the high-speed SERDES lanes. DUT Info SPI Config/Control SPI Memory Map ADDR. (Hex) PARAMETER NAME BIT 7 (MSB) BIT 6 BIT 5 00 port_config SDO Active LSB First Soft Reset 01 Reserved Reserved BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) DEF. VALUE (HEX) Mirror (bit5) Mirror (bit6) Mirror (bit7) 00h 02 burst_end Burst end address [7:0] 03-07 Reserved Reserved 08 chip_id Chip ID # Read only 09 chip_version Chip Version # Read only 0A-0F Reserved Reserved 27 00h FN7996.0 February 2, 2012 ISLA216S SPI Memory Map (Continued) Device Config/Control Device Config/Control ADDR. (Hex) PARAMETER NAME BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 10-1F Reserved Reserved 20 offset_coarse_adc0 Coarse Offset BIT 2 BIT 1 BIT 0 (LSB) DEF. VALUE (HEX) cal. value 21 offset_fine_adc0 22 gain_coarse_adc0 23 gain_medium_adc0 Medium Gain cal. value 24 gain_fine_adc0 Fine Gain cal. value 25 modes_adc0 26 offset_coarse_adc1 Coarse Offset cal. value 27 offset_fine_adc1 Fine Offset cal. value 28 gain_coarse_adc1 29 gain_medium_adc1 2A gain_fine_adc1 2B modes_adc1 2C-6F Reserved Fine Offset Reserved cal. value Coarse Gain Reserved cal. value 00h NOT reset by Soft Reset Power Down Mode ADC0 [2:0] 000 = Pin Control 001 = Normal Operation 010 = Nap 100 = Sleep Other codes = Reserved Reserved Coarse Gain cal. value Medium Gain cal. value Fine Gain Reserved cal. value 00h NOT reset by Soft Reset Power Down Mode ADC1 [2:0] 000 = Pin Control 001 = Normal Operation 010 = Nap 100 = Sleep Other codes = Reserved Reserved 70 skew_diff 71 phase_slip Differential Skew 72 clock_divide Clock Divide [2:0] 000 = Pin Control 001 = divide by 1 010 = divide by 2 100 = divide by 4 Other codes = Reserved 00h NOT reset by Soft Reset 73 output_mode_A Output Format [2:0] 000 = Two’s Complement (Default) 010 = Gray Code 100 = Offset Binary Other codes = Reserved 00h NOT reset by Soft Reset 74 output_mode_B Reserved 75-76 Reserved 77 SYNC_function 78-B5 Reserved B6 cal_status B7-BF Reserved 80h Next Clock Edge 00h 00h NOT reset by Soft Reset DLL Range 0 = Fast 1 = Slow Default=’0’ Reserved Clkdivrst Reserved Reserved 28 Calibration Done Read Only FN7996.0 February 2, 2012 ISLA216S SPI Memory Map (Continued) ADDR. (Hex) PARAMETER NAME C0 test_io BIT 7 (MSB) BIT 6 BIT 5 BIT 4 Output Test Mode [7:4] BIT 3 JESD Test Device Test <7:4>=Output Test, <3> = JESD Test JESD Test=0 Output Test = 0x0= Output Test Mode Off. During calibration MSB justified constant output 0xCCCC 0x1 = Midscale adjusted by numeric format 0x2 = Plus full scale, adjusted by numeric format 0x3 = Minus full scale adjusted by numeric format 0x4 = Checkboard output - 0xAAAA, 0x5555 0x5 = reserved 0x6 = reserved 0x7 = 0xFFFF, 0x0000 all on pattern 0x8 = User pattern 8 deep, MSB justified with output 0x9 = reserved 0xA, Count-up ramp 0xB, PRBS-9 0xC, PRBS-15 0xD, PRBS-23 0xE, PRBS-31 0xF = reserved JESD Test=1 Output Test = 0x0 =Link Layer Repeat K28.5+Lane Alignment Sequence 0x1, Link Layer Repeat K28.5 0x2, Link Layer Repeat D21.5 0x3, Link Layer Repeat K28.7 0x4, Link Layer PRBS-7 0x5, Link Layer PRBS-23 0x6, Link Layer All Zeros 0x7, Link Layer All Ones 0x8-0xE, reserved 0xF, JESD204A section 5.1.6.2 Transport Layer Test Pattern BIT 2 BIT 1 BIT 0 (LSB) DEF. VALUE (HEX) User Test Mode [2:0] User Test Mode (Single ADC products only) 0 = user pattern 1 only 1 = cycle pattern 1 through 2 2 = cycle pattern 1 through 3 3 = cycle pattern 1 through 4 4 = cycle pattern 1 through 5 5 = cycle pattern 1 through 6 6 = cycle pattern 1 through 7 7 = cycle pattern 1 through 8 User Test Mode (Dual and interleaved ADC products only) 0 = cycle pattern 1 through 2 1 = cycle pattern 1 through 4 2 = cycle pattern 1 through 6 3 = cycle pattern 1 through 8 4 -7 = NA 00h C1 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h C2 user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 00h C3 user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h C4 user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 00h C5 user_patt3_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h C6 user_patt3_msb B15 B14 B13 B12 B11 B10 B9 B8 00h C7 user_patt4_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h C8 user_patt4_msb B15 B14 B13 B12 B11 B10 B9 B8 00h C9 user_patt5_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h CA user_patt5_msb B15 B14 B13 B12 B11 B10 B9 B8 00h CB user_patt6_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h CC user_patt6_msb B15 B14 B13 B12 B11 B10 B9 B8 00h CD user_patt7_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h CE user_patt7_msb B15 B14 B13 B12 B11 B10 B9 B8 00h CF user_patt8_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h D0 user_patt8_msb B15 B14 B13 B12 B11 B10 B9 B8 00h D1-DE Reserved Reserved 29 FN7996.0 February 2, 2012 ISLA216S ADDR. (Hex) PARAMETER NAME DF JESD204_update_config_start E0 JESD204_config_0 E1 JESD204_config_1 E2 JESD204_config_2 E3 JESD204_config_3 E4 JESD204_config_4 E5 JESD204_config_5 E6 JESD204_config_6 E7 JESD204_config_7 E8 JESD204_config_8 BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) DEF. VALUE (HEX) update_ start 00h DID (Device ID Number) 00h BID (Bank ID Number) LID (Lane ID Number) SCR L (Number of Lanes per Device) F (Number of Octets per Frame) K (Number of frames per multi-frame) M (Number of Converters per Device) CS (Number of Control bits per Sample) N (Converter Resolution in bits) N’ (Total number of bits per Sample) S (Number of Samples per Converter per Frame) See Description for Default Settings JESD204 Interface SPI Memory Map (Continued) E9 JESD204_config_9 EA JESD204_config_10 EB JESD204_config_11 RES1 EC JESD204_config_12 RES2 ED JESD204_config_13 FCHK (Checksum) EE JESD204_update_config_compl ete update_ complete 00h EF JESD204_PLL_monitor_reset pll_lock_ mon_rst 00h F0 JESD204_status latched_ pll_lockn 00h F1 JESD204_sync F2 JESD204_trans_pat_config F3 JESD204_CML_polarity F4-FF Reserved HD CF (Number of Control Words per Frame per Link) op_confg_ pll_lockn wrong sync_req trans_pat_ no_mf_ max_len lane_sync lane_2_ polarity lane_1_ polarity lane_0_ polarity 00h Reserved 30 FN7996.0 February 2, 2012 ISLA216S Equivalent Circuits AVDD AVDD TO CHARGE PIPELINE INP 600 E3 11k CSAMP 4pF AVDD 18k TO CHARGE PIPELINE INN E2 E1 CLKP AVDD E2 E1 TO CLOCK-PHASE GENERATION AVDD CSAMP 4pF E3 AVDD 18k 11k CLKN FIGURE 48. ANALOG INPUTS AVDD FIGURE 49. CLOCK INPUTS AVDD (20k PULL-UP ON RESETN ONLY) AVDD 75k AVDD OVDD TO SENSE LOGIC 75k 280 INPUT OVDD OVDD 20k INPUT 75k TO LOGIC 280 75k FIGURE 51. DIGITAL INPUTS FIGURE 50. TRI-LEVEL DIGITAL INPUTS OVDD 50 OVDD 50 LANE[2:0]P AVDD OVDD VCM LANE[2:0]N 1.0V DATA + – DATA 16mA FIGURE 52. CML OUTPUTS 31 FIGURE 53. VCM_OUT OUTPUT FN7996.0 February 2, 2012 ISLA216S ADC Evaluation Platform Intersil offers ADC Evaluation platforms which can be used to evaluate any of Intersil’s high speed ADC products. Each platform consists of a FPGA based data capture motherboard and a family of ADC daughtercards. The USB interface and evaluation platform control software allow a user to quickly evaluate the ADC’s performance at a user’s specific application frequency requirements. More information is available at http://www.intersil.com/converters/adc_eval_platform/ Layout Considerations Split Ground and Power Planes Data converters operating at high sampling frequencies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections. Analog supply and ground planes should be laid out under signal and clock inputs. Locate the digital planes under outputs and logic pins. Grounds should be joined under the chip. Clock Input Considerations Use matched transmission lines to the transformer inputs for the analog input and clock signals. Locate transformers and terminations as close to the chip as possible. Exposed Paddle The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for optimal thermal performance. Bypass and Filtering Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very close to device pins, as longer traces between the ceramic bypass capacitors and the device pins will increase inductance, which can result in diminished dynamic performance. Best practices bypassing is especially important on the AVDD and OVDD(PLL) power supply pins. Whenever possible, each supply pin should have its own 0.1uF bypass capacitor. Make sure that connections to ground are direct and low impedance. Avoid forming ground loops. CML Outputs Output traces and connections must be designed for 50Ω (100Ω differential) characteristic impedance. Keep traces direct and short, and minimize bends and vias where possible. Avoid crossing ground and power-plane breaks with signal traces. Keep good clearance (at least 5 trace widths) between the SERDES traces and other signals. Given the speed of these outputs and 32 importance of maintaining an open eye to achieve low BER, signal integrity simulations are recommended, especially when the data lane rate exceeds 3Gbps and/or the trace or cable length between the ADC and the reciever gets larger than 20cm. Unused Inputs Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will not be operated do not require connection to ensure optimal ADC performance. These inputs can be left floating if they are not used. Tri-level inputs (NAPSLP) accept a floating input as a valid state, and therefore should be biased according to the desired functionality. Definitions Analog Input Bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full-scale low-frequency value. This is also referred to as Full Power Bandwidth. Aperture Delay or Sampling Delay is the time required after the rise of the clock input for the sampling switch to open, at which time the signal is held for conversion. Aperture Jitter is the RMS variation in aperture delay for a set of samples. Clock Duty Cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) is an alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02 Gain Error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage less than 2 LSB. It is typically expressed in percent. I2E The Intersil Interleave Engine. This highly configurable circuitry performs estimates of offset, gain, and sample time skew mismatches between the core converters, and updates analog adjustments for each to minimize interleave spurs. Integral Non-Linearity (INL) is the maximum deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms of input voltage is VFS/(2N - 1) where N is the resolution in bits. FN7996.0 February 2, 2012 ISLA216S Missing Codes are output codes that are skipped and will never appear at the ADC output. These codes cannot be reached with any input value. Most Significant Bit (MSB) is the bit that has the largest value or weight. Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the data. Power Supply Rejection Ratio (PSRR) is the ratio of the observed magnitude of a spur in the ADC FFT, caused by an AC signal superimposed on the power supply voltage. Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one-half the sampling frequency, excluding harmonics and DC. SNR and SINAD are either given in units of dB when the power of the fundamental is used as the reference, or dBFS (dB to full scale) when the converter’s full-scale input power is used as the reference. Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the largest spurious spectral component. The largest spurious spectral component may or may not be a harmonic. Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one half the clock frequency, including harmonics but excluding DC. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION February 2, 2012 FN7996.0 CHANGE Initial Release Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISLA216S13, ISLA216S20, ISLA216S25. To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 33 FN7996.0 February 2, 2012 ISLA216S Package Outline Drawing L48.7x7G 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 1/10 7.00 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 4X 5.5 A B 37 48 36 1 7.00 44X 0.50 (4X) EXP. DAP 5.70 SQ. 12 25 0.15 24 13 48X 0.40 48x 0.20 4 TOP VIEW BOTTOM VIEW SEE DETAIL "X" 1.00 MAX 0.10 C C 0.08 C SEATING PLANE ( 44X 0 . 5 ) 6 .80 SQ SIDE VIEW 5.70 SQ C 0 . 2 REF 5 ( 48X 0 . 20 ) 0 . 00 MIN. 0 . 05 MAX. ( 48X 0 . 60 ) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.015mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 34 FN7996.0 February 2, 2012