Si4952DY-DS

SPICE Device Model Si4952DY
Vishay Siliconix
Dual N-Channel 25V (D-S) MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 69159
S-72051Rev. A, 08-Oct-07
www.vishay.com
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SPICE Device Model Si4952DY
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Simulated
Data
Measured
Data
VGS(th)
VDS = VGS, ID = 250 µA
1.5
ID(on)
VDS ≥ 5 V, VGS = 10 V
241
VGS = 10 V, ID = 7 A
0.019
0.019
VGS = 4.5 V, ID = 6.3 A
0.023
0.023
Unit
Static
Gate Threshold Voltage
On-State Drain Current
a
Drain-Source On-State Resistancea
rDS(on)
V
A
Ω
Forward Transconductancea
gfs
VDS = 10 V, ID = 7 A
19
23
S
Forward Voltagea
VSD
IF = 5.6 A
0.83
0.80
V
701
680
120
120
36
55
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS = 13 V, VGS = 0 V, f = 1 MHz
VDS = 13 V, VGS = 10 V, ID = 7 A
VDS = 13 V, VGS = 4.5 V, ID = 7 A
10.6
12
5.2
5.5
2
2
1.5
1.5
pF
nC
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
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Document Number: 69159
S-72051Rev. A, 08-Oct-07
SPICE Device Model Si4952DY
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 69159
S-72051Rev. A, 08-Oct-07
www.vishay.com
3
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Document Number: 91000
Revision: 18-Jul-08
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