INTERSIL ISL95311

ISL95311
®
Digitally Controlled Potentiometer (XDCP™)
Data Sheet
May 6, 2005
Terminal Voltage 0V to 13.2V, 128 Taps I2C
Interface
Features
The Intersil ISL95311 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by an I2C interface.
• I2C serial interface
The potentiometer is implemented by a resistor array
composed of 127 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The wiper of the
potentiometer has an associated volatile Wiper Counter
Register (WR) and a non-volatile Initial Value Register (IVR)
that can be directly written to and read by the user. The
contents of the WR controls the position of the wiper on the
resistor array through the switches. At power-up, the device
recalls the contents of the IVR to the corresponding WR.
The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications, including:
FN8084.0
• Non-volatile solid-state potentiometer
• DCP terminal voltage, 0V to +13.2V
• 128 wiper tap points - 0.8% resolution
- Wiper position stored in nonvolatile memory and
recalled on power-up
• 127 resistive elements
- Temperature compensated
- Low wiper resistance 70Ω typical @ 3.3V
• Low power CMOS
- Standby current, 2µA @ VCC = +3.6V
• High reliability
- Endurance, 200,000 data changes per bit
- Register data retention 50 years @ T ≤ 75°C
• RTOTAL values = 10kΩ, 50kΩ
• 10-lead MSOP package
- Pb-free plus anneal available (RoHS compliant)
• LCD contrast control
• Parameter and bias adjustments
Pinout
• Industrial and automotive control
ISL95311
(10-LD MSOP)
TOP VIEW
• Mechanical pot replacement
Ordering Information
RESISTANCE
OPTION
(Ω)
TEMP
RANGE
(°C)
ISL95311WIU10Z
(See Note)
10K
-40 to +85
ISL95311UIU10Z
(See Note)
50K
PART NUMBER
-40 to +85
PACKAGE
10-Ld MSOP
(Pb-Free)
SCL
SDA
1
10
GND
2
9
V+
VCC
3
8
RL
A1
4
7
RW
A0
5
6
RH
10-Ld MSOP
(Pb-Free)
Add “-TK” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pbfree material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS compliant
and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL95311
Block Diagram
SDA
SCL
V+
VCC
7-BIT
WIPER
REGISTER
(VOLATILE)
RH
127
126
SDA
125
RH
SCL
A1
CONTROL
AND
MEMORY
7-BIT
NONVOLATILE
MEMORY
RW
A0
124
ONE
OF
128
TRANSFER
GATES
RESISTOR
ARRAY
DECODER
RL
2
STORE AND
RECALL
CONTROL
CIRCUITRY
GND
SIMPLE BLOCK DIAGRAM
A1
A0
1
0
RL
RW
SLAVE
ADDRESS
DECODE
DETAILED BLOCK DIAGRAM
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1
SDA
Data I/O for I2C serial interface; it has an open drain output and may be wire-or’d with other open
drain active low outputs
2
GND
Ground
3
VCC
Positive logic supply voltage
4
A1
Address select pin used to set the slave address for the I2C serial interface
5
A0
Address select pin used to set the slave address for the I2C serial interface
6
RH
A fixed terminal for one end of the potentiometer resistor
7
RW
The wiper terminal which is equivalent to the movable terminal of a potentiometer
8
RL
A fixed terminal for one end of the potentiometer resistor
9
V+
Positive bias voltage for the potentiometer wiper control
10
SCL
2
Clock input for the I2C serial interface
FN8084.0
May 6, 2005
ISL95311
Absolute Maximum Ratings
Recommended Operating Conditions
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on SDA, SCL, A0, A1
with respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Voltage on V+ (referenced to GND) . . . . . . . . . . . . . . . . . . . . +13.2V
ΔV = |V(RH)–V(RL)| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+
RH, RL, RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+
Lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . . 300°C
IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Power rating of DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mW
Temperature Range (Industrial) . . . . . . . . . . . . . . . . .-40°C to +85°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 13.2V
Wiper current of DCP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Analog Specifications Over recommended operating conditions unless otherwise stated.
SYMBOL
RTOTAL
PARAMETER
RH to RL resistance
TEST CONDITIONS
UNIT
kΩ
U option
50
kΩ
RH terminal voltage
VRL = 0V
RW
Wiper resistance
V+ = 12.0V, wiper current = V+ / RTOTAL
-20
+20
%
0
V+
V
200
Ω
70
Potentiometer Capacitance
Leakage on DCP pins
MAX
10
VRH
ILkgDCP
TYP
(Note 1)
W option
RH to RL resistance tolerance
CH/CL/CW
(Note 13)
MIN
10/10/
25
Voltage at pin from GND to V+
pF
0.1
1
µA
-1
1
LSB
(Note 2)
W option
-0.75
0.75
U option
-0.5
0.5
LSB
(Note 2)
W option
0
1
7
U option
0
0.5
2
W option
-7
-1
0
U option
-2
-1
0
VOLTAGE DIVIDER MODE (0V @ RL; V+ @ RH; measured at RW, unloaded)
INL
(Note 6)
Integral non-linearity
DNL
(Note 5)
Differential non-linearity
ZSerror
(Note 3)
Zero-scale error
FSerror
(Note 4)
Full-scale error
TCV
(Note 7, 13)
Ratiometric Temperature Coefficient
DCP register set to 40 hex
±4
LSB
(Note 2)
LSB
(Note 2)
ppm/°C
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)
RINL
(Note 11)
Integral non-linearity
DCP register set between 20 hex and 5F hex;
monotonic over all tap positions
RDNL
(Note 10)
Differential non-linearity
Roffset
(Note 9)
Offset
TCR
Resistance Temperature Coefficient
(Note 12, 13)
3
-1
1
MI
(Note 8)
W option
-0.75
0.75
U option
-0.5
0.5
MI
(Note 8)
DCP Register set to 00 hex, W option
0
1
7
MI
(Note 8)
DCP Register set to 00 hex, U option
0
0.5
2
MI
(Note 8)
DCP register set between 20 hex and 7F hex
±45
ppm/°C
FN8084.0
May 6, 2005
ISL95311
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNIT
ICC1
VCC supply current, volatile write/read fSCL = 400kHz; SDA = Open; (for I2C, active,
read, and volatile write states only)
1
mA
ICC2
VCC supply current, nonvolatile write
fSCL = 400kHz; SDA = Open; (for I2C, active,
nonvolatile write states only)
3
mA
VCC current, standby
VCC = +5.5V, I2C interface in standby state
5
µA
VCC = +3.6V, I2C interface in standby state
2
µA
V+ bias current
V+ = 13.2V, VCC = +5.5V
1
µA
Leakage current, at pins SDA, SCL,
A0, and A1 pins
Voltage at pin from GND to VCC
10
µA
tDCP
(Note 13)
DCP wiper response time
SCL falling edge of last bit of DCP data byte to
wiper change
1
µs
Vpor
(Note 13)
Power-on recall voltage
Minimum VCC at which memory recall occurs
2.6
V
VccRamp
(Note 10)
VCC ramp rate
tD
(Note 13)
Power-up delay
ISB
IV+
ILkgDig
-10
1.8
0.2
V/ms
3
VCC above Vpor, to DCP initial value register
recall completed, and I2C Interface in standby
state
ms
EEPROM SPECS
EEPROM endurance
EEPROM retention
Temperature ≤ 75°C
200,000
Cycles
50
Years
SERIAL INTERFACE SPECS
VIL
A0, A1, SDA, and SCL input buffer
LOW voltage
-0.3
0.3*
VCC
V
VIH
A0, A1, SDA, and SCL input buffer
HIGH voltage
0.7*
VCC
VCC+
0.3
V
SDA and SCL input buffer hysteresis
0.05*
VCC
Hysteresis
VOL
SDA output buffer LOW voltage,
sinking 4mA
Cpin
fSCL
0
V
0.4
V
A0, A1, SDA, and SCL pin
capacitance
10
pF
SCL frequency
400
kHz
tIN
Pulse width suppression time at SDA
and SCL inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
SCL falling edge to SDA output data
valid
SCL falling edge crossing 30% of VCC, until SDA
exits the 30% to 70% of VCC window
900
ns
tBUF
Time the bus must be free before the
start of a new transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC during
the following START condition
1300
ns
tLOW
Clock LOW time
Measured at the 30% of VCC crossing
1300
ns
tHIGH
Clock HIGH time
Measured at the 70% of VCC crossing
600
ns
tSU:STA
START condition setup time
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
600
ns
tHD:STA
START condition hold time
From SDA falling edge crossing 30% of VCC to
SCL falling edge crossing 70% of VCC
600
ns
4
FN8084.0
May 6, 2005
ISL95311
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TYP
(Note 1)
TEST CONDITIONS
MIN
100
ns
MAX
UNIT
tSU:DAT
Input data setup time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of VCC
tHD:DAT
Input data hold time
From SCL rising edge crossing 30% of VCC to
SDA entering the 30% to 70% of VCC window
0
ns
tSU:STO
STOP condition setup time
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VCC
600
ns
tHD:STO
STOP condition setup time
From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC
600
ns
Output data hold time
From SCL falling edge crossing 30% of VCC, until
SDA enters the 30% to 70% of VCC window
0
ns
tR
SDA and SCL rise time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
ns
tF
SDA and SCL fall time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb
Capacitive loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
SDA and SCL bus pull-up resistor off- Maximum is determined by tR and tF,
chip
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ.
tDH
tWP
(Notes 14)
1
Non-volatile write cycle time
kΩ
12
20
ms
tSU:A
A0, A1 setup time
Before START condition
600
ns
tHD:A
A0, A1 hold time
After STOP condition
600
ns
SDA vs SCL Timing
tHIGH
tF
SCL
tLOW
tR
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
SDA
(INPUT TIMING)
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
A0, A1 Pin Timing
STOP
START
SCL
CLK 1
SDA IN
tSU:A
tHD:A
A0, A1
5
FN8084.0
May 6, 2005
ISL95311
NOTES:
1. Typical values are for TA = 25°C and 3.3V supply voltage.
2. LSB: [V(RW)127 – V(RW)0] / 127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = V(RW)0 / LSB.
4. FS error = [V(RW)127 – V+] / LSB.
5. DNL = [V(RW)i – V(RW)i-1] / LSB-1, for i = 1 to 127. i is the DCP register setting.
6. INL = V(RW)i – (i • LSB – V(RW)0) for i = 1 to 127.
Max ( V ( RW ) i ) – Min ( V ( RW ) i )
10 6
7. TC V = ---------------------------------------------------------------------------------------------- × ----------------[ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 125°C
for i = 16 to 120 decimal, T = -40°C to 85°C. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper
voltage over the temperature range.
8. MI = |R127 – R0| / 127. R127 and R0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively.
9. Roffset = R0 / MI, when measuring between RW and RL.
Roffset = R127 / MI, when measuring between RW and RH.
10. RDNL = (Ri – Ri-1) / MI, for i = 16 to 127.
11. RINL = [Ri – (MI • i) – R0] / MI, for i = 16 to 127.
6
[ Max ( Ri ) – Min ( Ri ) ]
10
12. TC R = ---------------------------------------------------------------- × ----------------[ Max ( Ri ) + Min ( Ri ) ] ⁄ 2 125°C
for i = 16 to 127, T = -40°C to 85°C. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the
temperature range.
13. This parameter is not 100% tested.
14. tWP is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a
valid STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile
write cycle.
Pin Descriptions
DEVICE ADDRESS (A1–A0)
Potentiometer Pins
RH and RL
RL and RH are referenced to the relative position of the
wiper and not the voltage potential on the terminals. With
WR set to 127, the wiper will be closest to RH, and with the
WR set to 00, the wiper is closest to RL.
RW
RW is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for the
I2C interface. It receives device address, operation code,
wiper register address and data from a I2C external master
device at the rising edge of the serial clock SCL, and it shifts
out data after each falling edge of the serial clock SCL.
SDA requires an external pull-up resistor, since it’s an open
drain input/output.
SERIAL CLOCK (SCL)
This input is the serial clock of the I2C serial interface.
SCL requires an external pull-up resistor, since it’s an open
drain input.
6
The Address inputs are used to set the least significant 2 bits
of the 8-bit I2C interface slave address. A match in the slave
address serial data stream must be made with the Address
input pins in order to initiate communication with the
ISL95311. A maximum of 4 ISL95311 devices may occupy
the I2C serial bus.
Principles of Operation
The ISL95311 is an integrated circuit incorporating one DCP
with their associated register, non-volatile memory, and a
I2C serial interface providing direct communication between
a host and the potentiometers and memory. The resistor
array is comprised of 127 individual resistors connected in
series. At either end of the array and between each resistor
is an electronic switch between that point and the wiper.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.
FN8084.0
May 6, 2005
ISL95311
On applying power to the ISL95311, the VCC supply should
have a monotonic ramp to the specified operating voltage. It
is important that once VCC reaches 1V that it increases to at
least 2.5V in less than 7.5ms (0.2V/ms). The ramp rate
before and after these thresholds is not important.
VCC must be applied prior to, or simultaneously, with V+.
Under no condition should V+ be applied without VCC. While
the sequence of applying V+ and VCC to the ISL95311 does
not affect the proper recall of the wiper position, applying V+
before VCC powers the electronic switches of the DCP
before the electronic switch control signals are applied. This
can result in multiple electronic switches being turned on,
which could load the power supply and cause brief,
unexpected potentiometer wiper settings.
To prevent unknown wiper positions on the ISL95311 on
power down, it is recommended that V+ turn off before or
simultaneously with VCC. If V+ remains on after VCC turns
off, the wiper position can remain unchanged from its
previous setting or it can go to an undefined state.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin is connected to
intermediate nodes, and is equivalent to the wiper terminal
of a mechanical potentiometer. The position of the wiper
terminal within the DCP is controlled by a 7-bit volatile Wiper
Register (WR). When the WR contains all zeroes (00h), the
wiper terminal (RW) is closest to its “Low” terminal (RL).
When the WR contains all ones (7Fh), the wiper terminal
(RW) is closest to its “High” terminal (RH). As the value of the
WR increases from all zeroes (00h) to all ones (7Fh), the
wiper moves monotonically from the position closest to RL to
the position closest to RH. At the same time, the resistance
between RW and RL increases monotonically, while the
resistance between RH and RW decreases monotonically.
The volatile WR, and the non-volatile IVR of a DCP are
accessed with the same address.
The Access Control Register (ACR) determines which word
at address 00h is accessed (IVR or WR). The volatile ACR
must be set as follows:
When the ACR is all zeroes, which is the default at powerup:
• A read operation to address 0 outputs the value of the
non-volatile IVR.
• A write operation to address 0 writes the identical values
to the WR and IVR of the DCP.
• When the ACR is 80h:
• A read operation to address 0 outputs the value of the
volatile WR.
• A write operation to address 0 only writes to the
volatile WR.
It is not possible to write to an IVR without writing the same
value to its WR.
00h and 80h are the only values that should be written to
address 2. All other values are reserved and must not be
written to address 2.
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
2
-
ACR
1
0
Reserved
IVR
WR
WR: Wiper Register, IVR: Initial value Register.
The ISL95311 is pre-programmed with 40h in the IVR.
I2C Serial Interface
While the ISL95311 is being powered up, the WR is reset to
20h (64 decimal), which locates the RW at the center
between RL and RH. Soon after the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the ISL95311 reads the value stored on a nonvolatile Initial Value Register (IVR) and loads it into the WR.
The ISL95311 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL95311
operates as a slave device in all applications.
The WR and IVR can be read from or written to directly using
the I2C serial interface as described in the following
sections.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Memory Description
Protocol Conventions
The ISL95311 contains 1 non-volatile byte know as the Initial
Value Register (IVR). It is accessed by the I2C interface
operations with Address 00h. The IVR contains the value
which is loaded into the Volatile Wiper Register (WR) at
power-up.
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 1). On power-up of the ISL95311 the SDA pin is in the
input mode.
7
FN8084.0
May 6, 2005
ISL95311
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL95311 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 1). A START condition is ignored during the power-up
sequence and during internal non-volatile write cycles.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 1). A STOP condition at the end of
a read operation, or at the end of a write operation to volatile
bytes only places the device in its standby mode. A STOP
condition during a write operation to a non-volatile byte,
initiates an internal non-volatile write cycle. The device
enters its standby state when the internal non-volatile write
cycle is completed.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 2).
The ISL95311 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL95311 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 01010 as the five MSBs,
and the following two bits matching the logic values present
at pins A1, and A0. The LSB is in the Read/Write bit. Its
value is “1” for a Read operation, and “0” for a Write
operation. (See Table 2.)
The byte at address 02h determines if the Data Byte is to be
written to volatile and/or non-volatile memory. (See “Memory
Description” on page 7.)
Data Protection
A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile
and non-volatile registers. During a Write sequence, the
Data Byte is loaded into an internal shift register as it is
received. If the Address Byte is 0 or 2, the Data Byte is
transferred to the Wiper Register (WR) or to the Access
Control Register respectively, at the falling edge of the SCL
pulse that loads the last bit (LSB) of the Data Byte. If the
Address Byte is 0, and the Access Control Register is all
zeros (default), then the STOP condition initiates the internal
write cycle to non-volatile memory.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (See Figure 4). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL95311 responds with an ACK; then
the ISL95311 transmits the Data Byte. The master then
terminates the read operation (issuing a STOP condition)
following the last bit of the Data Byte (See Figure 4).
The byte at address 02h determines if the Data Bytes being
read are from volatile or non-volatile memory. (See “Memory
Description”.)
TABLE 2. IDENTIFICATION BYTE FORMAT
Logic values at pins A1, and A0 respectively
0
1
0
1
0
(MSB)
A1
A0
R/W
(LSB)
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition (See Figure 3). After each of the three
bytes, the ISL95311 responds with an ACK. At this time, if
the Data Byte is to be written only to volatile registers, then
the device enters its standby state. If the Data Byte is to be
written also to non-volatile memory, the ISL95311 begins its
internal write cycle to non-volatile memory. During the
internal non-volatile write cycle, the device ignores
transitions at the SDA and SCL pins, and the SDA output is
at a high impedance state. When the internal non-volatile
write cycle is completed, the ISL95311 enters its standby
state.
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ISL95311
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 1. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
S
T
A
R
T
IDENTIFICATION
BYTE
ADDRESS
BYTE
0 1 0 1 0 A1 A0 0
SIGNALS FROM
THE ISL95311
S
T
O
P
DATA
BYTE
0
0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
FIGURE 3. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
IDENTIFICATION
BYTE WITH
R/W=0
ADDRESS
BYTE
0 1 0 1 0 A1 A0 0
0 0 0 0 0 0
A
C
K
SIGNALS FROM
THE SLAVE
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W=1
A
C
K
S
T
O
P
A
C
K
0 1 0 1 0 A1 A0 1
0
A
C
K
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 4. READ SEQUENCE
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ISL95311
Communicating with the ISL95311
Register Description: IVR and WR
There are 3 register addresses in the ISL95311, of which two
can be used. Address 00h and address 02h are used to
control the device. Address 01h is reserved and should not
be used. Address 00h contains the nonvolatile Initial Value
Register (IVR), and the volatile Wiper Register (WR).
Address 02h contains only a volatile word and is used as a
pointer to either the IVR or WR. See Table 1.
The ISL95311 has a single potentiometer. The wiper of the
potentiometer is controlled directly by the WR. Writes and
reads can be made directly to this register to control and
monitor the wiper position without any nonvolatile memory
changes. This is done by setting address 02h to data 80h,
then writing the data.
The nonvolatile IVR stores the power-up value of the wiper.
On power-up, the contents of the IVR are transferred to the
WR.
Register Descriptions: Access Control
The Access Control Register (ACR) is volatile and is at
address 02h. It is 8-bits, and only the MSB is significant, all
other bits should be zero (0). The ACR controls which word
is accessed at register 00h as follows:
To write to the IVR, first address 02h is set to data 00h, then
the data is written. Writing a new value to the IVR register
will set a new power-up position for the wiper. Also, writing to
this register will load the same value into the WR as the IVR.
So, if a new value is loaded into the IVR, not only will the
non-volatile IVR change, but the WR will also contain the
same value after the write, and the wiper position will
change. Reading from the IVR will not change the WR, if its
contents are different.
00h = Nonvolatile IVR
80h = Volatile WR
All other bits of the ACR should be written to as zeros. Only
the MSB can be either 0 or 1. Power-up default for this
address is 00h.
Example 1
Writing a new value (77h) to the IVR:
Write to ACR first
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
0
0
0
0
0
0
0
0
A
0
0
0
A
0
0
0
0
0
0
0
0
A
0
1
1
1
0
1
1
1
A
0
1
0
A
Then, write to IVR
0
1
0
1
0
(note that the WR will also reflect this new value since both registers get written to at the same time)
Example 2
Reading from the WR:
Write to the ACR first (to index the WR)
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
A
0
0
0
0
0
Then, Set the WR address
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
0
0
0
0
1
A
x
x
x
x
x
x
x
x
Read from the WR
0
1
0
1
0
notes: A=acknowledge, x = data bit read
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ISL95311
Packaging Information
10 Lead MSOP, Package Code
0.0106 [0.27]
0.0067 [0.17]
10
9
8
7
4
6
0.1970 [5.00]
0.1890 [4.80]
1
2
3
4
(S)
5
0.0197 [0.50] BSC
SECTION A-A
0.0374 [0.95]
0.1220 [3.10]
0.1142 [2.90]
2
0.0295 [0.75]
0.0433 [1.10] MAX.
0.1220 [3.10]
0.0098 [0.25]
GAUGE PLANE
0.1142 [2.90]
A
0.1220 [3.10]
0.0059 [0.15]
0.0020 [0.05]
0.1142 [2.90]
(S)
3
3
0°-6°
A
0.0276 [0.70]
0.0157 [0.40]
0.0039 [0.10]
MAX.
(S)
NOTES:
1. Package dimensions conform to JEDEC specification MO-187BA.
2.
2 Does not include mold flash, protrusion
or gate burrs, mold flash protrusions
or gate burrs shall not exceed 0.15 mm per side.
3.
3
Does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.15 mm per side.
4.
4
Does not include dambar protrusion. Allowable dambar protrusion shall be 0.8 mm.
5. Lead span/stand-off height/coplanarity are considered as special characteristics.
6. Controlling dimensions in inches [mm].
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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