ISL22349 ® Quad Digitally Controlled Potentiometers (XDCP™) Data Sheet September 15, 2006 Low Noise, Low Power, I2C® Bus, 128 Taps, Wiper Only Features The ISL22349 integrates four digitally controlled potentiometers (DCP) and non-volatile memory on a monolithic CMOS integrated circuit. • 128 resistor taps The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power up the device recalls the contents of the two DCP’s IVR to the corresponding WRs. FN6331.2 • Four potentiometers in one package • I2C serial interface - Three address pins, up to eight devices/bus • Non-volatile storage of wiper position • Wiper resistance: 70Ω typical • Shutdown mode • Shutdown current 6.5µA max • Power supply: 2.7V to 5.5V • 50kΩ or 10kΩ total resistance The DCPs can be used as a voltage divider in a wide variety of applications including control, parameter adjustments, AC measurement and signal processing. • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T < +55°C Pinout • 14 Ld TSSOP ISL22349 (14 LD TSSOP) TOP VIEW • Pb-free plus anneal product (RoHS compliant) RW3 1 14 RW0 A2 2 13 SHDN SCL 3 12 VCC SDA 4 11 NC GND 5 10 A1 RW2 6 9 A0 RW1 7 8 NC Ordering Information PART NUMBER PART MARKING RESISTANCE OPTION (kΩ) TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL22349UFV14Z (Notes 1, 2) 22349 UFVZ 50 -40 to +125 14 Ld TSSOP (Pb-Free) M14.173 ISL22349WFV14Z (Notes 1, 2) 22349 WFVZ 10 -40 to +125 14 Ld TSSOP (Pb-Free) M14.173 NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add “-TK” suffix for 1,000 Tape and Reel option 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL22349 Block Diagram VCC VCC WR3 SCL SDA I2C INTERFACE A0 A1 POWER-UP INTERFACE, CONTROL AND STATUS LOGIC RW3 VCC WR2 RW2 A2 VCC WR1 NONVOLATILE REGISTERS SHDN RW1 VCC WR0 RW0 GND Pin Descriptions TSSOP PIN SYMBOL 1 RW3 2 A2 3 SCL Open drain I2C interface clock input 4 SDA Open drain serial data I/O for the I2C interface 5 GND Device ground pin and the RL connection for each DCP 6 RW2 “Wiper” terminal of DCP2 7 RW1 “Wiper” terminal of DCP1 8 NC 9 A0 Device address input for the I2C interface 10 A1 Device address input for the I2C interface 11 NC 12 VCC 13 SHDN Shutdown active low input 14 RW0 “Wiper” terminal of DCP0 2 DESCRIPTION “Wiper” terminal of DCP3 Device address input for the I2C interface Power supply pin and the RH connection for each DCP FN6331.2 September 15, 2006 ISL22349 Absolute Maximum Ratings Thermal Information Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to VCC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV Thermal Resistance (Typical, Note 3) θJA (°C/W) 14 Ld TSSOP package . . . . . . . . . . . . . . . . . . . . . . +100 Maximum Junction Temperature (Plastic Package) .................................... +50°C to +150°C Recommended Operating Conditions Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VCC Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -0.8V for all pins. Analog Specifications SYMBOL RTOTAL Over recommended operating conditions unless otherwise stated. PARAMETER End-to-End Resistance TEST CONDITIONS MIN TYP (NOTE 5) MAX UNIT W option 10 kΩ U option 50 kΩ End-to-End Resistance Tolerance W and U option End-to-End Temperature Coefficient W option ±50 ppm/°C (Note 13) U option ±80 ppm/°C (Note 13) VCC = 3.3V @ +25°C, wiper current = VCC/RTOTAL 70 Ω 25 pF RW (Note 13) Wiper Resistance CW (Note 13) Wiper Capacitance -20 +20 % VOLTAGE DIVIDER MODE (measured at RWi, unloaded; i = 0, 1, 2, or 3) INL (Note 10) Integral Non-linearity Monotonic over all tap positions -1 1 LSB (Note 6) DNL (Note 9) Differential Non-linearity Monotonic over all tap positions -0.5 0.5 LSB (Note 6) ZSerror (Note 7) Zero-scale Error W option 0 1 5 U option 0 0.5 2 LSB (Note 6) FSerror (Note 8) Full-scale Error W option -5 -1 0 U option -2 -1 0 VMATCH (Note 11) DCP to DCP Matching Any two DCPs at the same tap position -2 TCV (Note 12) Ratiometric Temperature Coefficient DCP register set to 40 hex 3 2 ±4 LSB (Note 6) LSB (Note 6) ppm/°C FN6331.2 September 15, 2006 ISL22349 Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL ICC1 ICC2 ISB ISD PARAMETER TEST CONDITIONS MIN TYP (NOTE 5) MAX UNIT VCC Supply Current (volatile write/read) VCC = +3.6V, 10k DCP, fSCL = 400kHz; (for I2C active, read and write states) 2.5 mA VCC Supply Current (volatile write/read, non-volatile read) VCC = +3.6V, 50k DCP, fSCL = 400kHz; (for I2C active, read and write states) 0.65 mA VCC Supply Current (non-volatile write/read) VCC = +5.5V, 10k DCP, fSCL = 400kHz; (for I2C active, read and write states) 4.0 mA VCC Supply Current (non-volatile write/read) VCC = +5.5V, 50k DCP, fSCL = 400kHz; (for I2C active, read and write states) 3.0 mA VCC Current (standby) VCC = +5.5V, 10k DCP, I2C interface in standby state 2.4 mA VCC = +3.6V, 10k DCP, I2C interface in standby state 525 µA VCC = +5.5V, 50k DCP, I2C interface in standby state 1.6 mA VCC = +3.6V, 50k DCP, I2C interface in standby state 350 µA VCC = +5.5V @ +85°C, I2C interface in standby state 5 µA VCC = +5.5V @ +125°C, I2C interface in standby state 6.5 µA VCC = +3.6V @ +85°C, I2C interface in standby state 4 µA VCC = +3.6V @ +125°C, I2C interface in standby state 5.5 µA 1 µA VCC Current (shutdown) Leakage Current, at Pins A0, A1, A2, SHDN, SDA, and SCL Voltage at pin from GND to VCC tWRT (Note 13) DCP Wiper Response Time SCL falling edge of last bit of DCP data byte to wiper new position 1.5 µs tShdnRec (Note 13) DCP Recall Time from Shutdown Mode From rising edge of SHDN signal to wiper stored position and RH connection 1.5 µs SCL falling edge of last bit of ACR data byte to wiper stored position and RH connection 1.5 µs ILkgDig Vpor Power-on Recall Voltage VccRamp VCC Ramp Rate tD Power-up Delay Minimum VCC at which memory recall occurs -1 2.0 2.6 0.2 V V/ms 3 Vcc above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state ms EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 14) Non-volatile Write Cycle Time 4 Temperature T < +55°C 1,000,000 Cycles 50 Years 12 20 ms FN6331.2 September 15, 2006 ISL22349 Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP (NOTE 5) MAX UNIT SERIAL INTERFACE SPECS VIL A2, A1, A0, SHDN, SDA, and SCL Input Buffer LOW Voltage -0.3 0.3*VCC V VIH A2, A1, A0, SHDN, SDA, and SCL Input Buffer HIGH Voltage 0.7*VCC VCC+0.3 V Hysteresis VOL Cpin (Note 13) fSCL SDA and SCL Input Buffer Hysteresis 0.05* VCC SDA Output Buffer LOW Voltage, Sinking 4mA V 0 A2, A1, A0, SHDN, SDA, and SCL Pin Capacitance 0.4 10 V pF SCL Frequency 400 kHz tsp Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is and SCL Inputs suppressed 50 ns tAA SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until Valid SDA exits the 30% to 70% of VCC window 900 ns tBUF Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP Start of a New Transmission condition, to SDA crossing 70% of VCC during the following START condition 1300 ns tLOW Clock LOW Time Measured at the 30% of VCC crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VCC crossing 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge; both crossing 70% of VCC 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC 100 ns tHD:DAT Input Data Hold Time From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window 0 ns tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC 600 ns tHD:STO STOP Condition Hold Time for Read, or Volatile Only Write From SDA rising edge to SCL falling edge; both crossing 70% of VCC 1300 ns Output Data Hold Time From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window 0 ns tR SDA and SCL Rise Time From 30% to 70% of VCC 20 + 0.1 * Cb 250 ns tF SDA and SCL Fall Time From 70% to 30% of VCC 20 + 0.1 * Cb 250 ns Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF Rpu SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2~2.5kΩ For Cb = 40pF, max is about 15~20kΩ 1 kΩ A2, A1 and A0 Setup Time Before START condition 600 ns tDH tSU:A 5 FN6331.2 September 15, 2006 ISL22349 Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL tHD:A PARAMETER TEST CONDITIONS A2, A1 and A0 Hold Time TYP (NOTE 5) MIN After STOP condition MAX UNIT 600 ns NOTES: 5. Typical values are for TA = +25°C and 3.3V supply voltage. 6. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 7. ZS error = V(RW)0/LSB. 8. FS error = [V(RW)127 – VCC]/LSB. 9. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 10. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127. 11. VMATCH = [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. Max ( V ( RW ) i ) – Min ( V ( RW ) i ) 10 6 12. TC V = ---------------------------------------------------------------------------------------------- × ----------------- for i = 16 to 112 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 165°C minimum value of the resistance over the temperature range. 13. This parameter is not 100% tested. 14. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile write cycle. SDA vs SCL Timing tF tHIGH SCL tLOW tsp tR tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STA SDA (INPUT TIMING) tAA tDH tBUF SDA (OUTPUT TIMING) A0, A1, and A2 Pin Timing STOP START SCL CLK 1 SDA tSU:A tHD:A A0, A1, OR A2 6 FN6331.2 September 15, 2006 ISL22349 Typical Performance Curves VCC 1.4 100 Vcc = 3.3V, T = 125ºC 1.2 T =125ºC 80 1 70 60 50 40 VCC 0.8 Isb (µA) WIPER RESISITANCE (Ω) 90 0.6 30 0.4 Vcc = 3.3V, T = -40ºC Vcc = 3.3V, T = 20ºC 20 T =25ºC 0.2 10 0 0 0 20 40 60 80 100 2.7 120 3.2 3.7 4.2 5.2 Vcc, V TAP POSITION (DECIMAL) FIGURE 2. STANDBY ICC vs VCC FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10kΩ (W) 0.2 0.2 Vcc = 2.7V T = 25ºC T = 25ºC Vcc = 2.7V 0.1 INL (LSB) 0.1 DNL (LSB) 4.7 0 0 -0.1 -0.1 Vcc = 5.5V Vcc = 5.5V -0.2 -0.2 0 20 40 60 80 100 0 120 20 40 FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) 120 10k -0.30 0.90 Vcc = 2.7V 0.70 Vcc = 2.7V Vcc = 5.5V 0.30 0.10 -20 0 20 40 60 80 TEMPERATURE (ºC) FIGURE 5. ZSerror vs TEMPERATURE 7 50k Vcc = 5.5V -0.60 -0.90 10k -1.20 50k -0.10 FSerror (LSB) ZSerror (LSB) 100 FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) 1.10 -0.30 -40 80 0.00 1.30 0.50 60 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) 100 120 -1.50 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (ºC) FIGURE 6. FSerror vs TEMPERATURE FN6331.2 September 15, 2006 ISL22349 (Continued) 1.00 105 50k Vcc = 2.7V 90 0.50 0.00 -0.50 Vcc = 5.5V -1.00 -40 10k 75 TCv (ppm/°C) END TO END RTOTAL CHANGE (%) Typical Performance Curves 10k 60 45 30 50k 15 0 -20 0 20 40 60 80 100 120 TEMPERATURE (ºC) FIGURE 7. END TO END RTOTAL % CHANGE vs TEMPERATURE FIGURE 9. MIDSCALE GLITCH, CODE 3Fh TO 40h 16 36 56 76 96 TAP POSITION (DECIM AL) FIGURE 8. TC FOR VOLTAGE DIVIDER MODE IN ppm FIGURE 10. LARGE SIGNAL SETTLING TIME Pin Descriptions Potentiometers Pins RWi (i = 0, 1, 2 or 3) RWi is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. RW SHDN The SHDN pin forces the resistor to end-to-end open circuit condition and shorts all RWi to GND. When SHDN is returned to logic high, the previous latch settings put RWi at the same resistance setting prior to shutdown. This pin is logically OR’d with SHDN bit in ACR register. I2C interface is still available in shutdown mode and all registers are accessible. This pin must remain HIGH for normal operation. 8 FIGURE 11. DCP CONNECTION IN SHUTDOWN MODE FN6331.2 September 15, 2006 ISL22349 Bus Interface Pins Serial Data Input/Output (SDA) The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, operation code, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. SDA requires an external pull-up resistor, since it is an open drain input/output. Serial Clock (SCL) This is the serial clock input of the I2C serial interface. SCL requires an external pull-up resistor, since it is an open drain input. Device Address (A2 - A0) The address inputs are used to set the least significant 3 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input pins in order to initiate communication with the ISL22349. A maximum of 8 ISL22349 devices may occupy the I2C serial bus. Principles of Operation The ISL22349 is an integrated circuit incorporating four DCPs with their associated registers, non-volatile memory and an I2C serial interface providing direct communication between a host and the potentiometers and memory. The resistor arrays are comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVRi will be maintained in the non-volatile memory. When power is restored, the contents of the IVRi are recalled and loaded into the corresponding WRi to set the wipers to the initial value. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer and internally connected to Vcc and GND. The RW pin of each DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by volatile Wiper Register (WR). Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR[6:0] = 00h), its wiper terminal (RW) is closest to GND. When the WR register of a DCP contains all ones (WR[6:0] = 7Fh), its wiper terminal (RW) is closest to VCC. As the value of the WR increases from all zeroes (0) to all 9 ones (127 decimal), the wiper moves monotonically from the position closest to GND to the closest to VCC. While the ISL22349 is being powered up, all four WRs are reset to 40h (64 decimal), which locates RW roughly at the center between GND and VCC. After the power supply voltage becomes large enough for reliable non-volatile memory reading, all WRs will be reload with the value stored in corresponding non-volatile Initial Value Registers (IVRs). The WRs can be read or written to directly using the I2C serial interface as described in the following sections. The I2C interface Address Byte has to be set to 00h, 01h, 02h or 03h to access the WR of DCP0, DCP1, DCP2 or DCP3 respectively. Memory Description The ISL22349 contains seven non-volatile and five volatile 8-bit registers. The memory map of ISL22349 is on Table 1. The four non-volatile registers (IVRi) at address 0, 1, 2 and 3, contain initial wiper value and volatile registers (WRi) contain current wiper position. In addition, three non-volatile General Purpose registers from address 4 to address 6 are available. TABLE 1. MEMORY MAP ADDRESS NON-VOLATILE VOLATILE 8 — ACR 7 Reserved 6 5 4 General Purpose General Purpose General Purpose Not Available Not Available Not Available 3 2 1 0 IVR3 IVR2 IVR1 IVR0 WR3 WR2 WR1 WR0 The non-volatile IVRi and volatile WRi registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described below in Table 2. The VOL bit at access control register (ACR[7]) determines whether the access is to wiper registers WRi or initial value registers IVRi. TABLE 2. ACCESS CONTROL REGISTER (ACR) VOL SHDN WIP 0 0 0 0 0 If VOL bit is 0, the non-volatile IVRi registers are accessible. If VOL bit is 1, only the volatile WRi are accessible. Note, value is written to IVRi register also is written to the corresponding WRi. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shutdown mode. This bit is logically OR’d with SHDN pin. When this bit is 0, DCPs are in Shutdown mode. Default value of SHDN bit is 1. FN6331.2 September 15, 2006 ISL22349 The WIP bit (ACR[5]) is read only bit. It indicates that non-volatile write operation is in progress. It is impossible to write to the WRi or ACR while WIP bit is 1. I2C Serial Interface The ISL22349 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL22349 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Protocol Conventions Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 12). On power-up of the ISL22349 the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL22349 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met. A START condition is ignored during the power-up of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 12). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 13). The ISL22349 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL22349 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 1010b as the four MSBs, and the following three bits matching the logic values present at pins A2, A1, and A0. The LSB is the Read/Write bit. Its value is “1” for a Read operation, and “0” for a Write operation (See Table 3). TABLE 3. IDENTIFICATION BYTE FORMAT Logic values at pins A2, A1, and A0 respectively 1 0 1 0 A2 A1 (MSB) A0 R/W (LSB) SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 12. VALID DATA CHANGES, START AND STOP CONDITIONS SCL FROM MASTER 1 8 SDA OUTPUT FROM TRANSMITTER 9 HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER 10 FN6331.2 September 15, 2006 ISL22349 WRITE S T A R T SIGNALS FROM THE MASTER SIGNAL AT SDA IDENTIFICATION BYTE ADDRESS BYTE 1 0 1 0 A2 A1 A0 0 SIGNALS FROM THE SLAVE S T O P DATA BYTE 0 0 0 0 A C K A C K A C K FIGURE 14. BYTE WRITE SEQUENCE SIGNALS FROM THE MASTER S T A R T SIGNAL AT SDA IDENTIFICATION BYTE WITH R/W = 0 ADDRESS BYTE 1 0 1 0 A2 A1 A0 0 A C K S A T C O K P A C K 1 0 1 0 A2 A1 A0 1 0 0 0 0 A C K SIGNALS FROM THE SLAVE S T A IDENTIFICATION R BYTE WITH T R/W = 1 A C K A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 15. READ SEQUENCE Write Operation Read Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL22349 responds with an ACK. At this time, the device enters its standby state (See Figure 14). Device can receive more than one byte of data by auto incrementing the address after each received byte. Note after reaching the address 08h, the internal pointer “rolls over” to address 00h. The non-volatile write cycle starts after STOP condition is determined and it requires up to 20ms delay for the next non-volatile write. Thus, non-volatile registers must be written individually. A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 15). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL22349 responds with an ACK. Then the ISL22349 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a ACK and a STOP condition) following the last bit of the last Data Byte (See Figure 15). The Data Bytes are from the registers indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 08h, the pointer “rolls over” to 00h, and the device continues to output data for each ACK received. In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again. 11 FN6331.2 September 15, 2006 ISL22349 Thin Shrink Small Outline Plastic Packages (TSSOP) M14.173 N INDEX AREA E 0.25(0.010) M E1 2 SYMBOL 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M 0.25 0.010 SEATING PLANE L A D -C- α e A1 b A2 c 0.10(0.004) 0.10(0.004) M C A M B S MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: MAX α 14 0o 14 7 8o Rev. 2 4/06 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN6331.2 September 15, 2006