U CT NT PROD E T E CEME L OBSO DED REPLA enter at EN rt C COMM nical Suppo il.com/tsc s NO RE Data h Sheet r c e e ww.int t ou r T contac TERSIL or w IN 1-888- HI-200/883 ® September 2004 FN6059.1 Dual SPST CMOS Analog Switch Features The HI-200/883 is a monolithic device comprising two independently selectable SPST switchers which feature fast switching speeds (240ns typical) combined with low power dissipation (15mW typical @ +25°C) • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. Each switch provides low “ON” resistance operation for input signal voltages up to the supply rails and for signal currents up to 25mA continuous. Rugged DI construction eliminates latch-up and substrate SCR failure modes. • Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . .±15V All devices provide break-before-make switching and are TTL and CMOS compatible for maximum application versatility. HI-200/883 is an ideal component for use in high frequency analog switching. Typical applications include signal path switching, sample and hold circuits, digital filters, and op amp gain switching networks. • Analog Current Range (Continuous) . . . . . . . . . . . . 25mA HI-200/883 is available in a 14 pin Ceramic DIP package and a 10 pin Metal Can (TO-100) package. • High Frequency Analog Switching • Low “On” Release . . . . . . . . . . . . . . . . . . . . . . .100Ω Max • TTL/CMOS Compatible . . . . . . . . . . . . . . 2.4V (Logic “1”) • Turn-On Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns • No Latch-Up • Replaces DG200 Applications • Sample and Hold Circuits • Digital Filters Functional Diagram V+ • Op Amp Gain Switching Networks VREF INPUT Pinouts HI1-200/883 (CERDIP) TOP VIEW SOURCE LOGIC INPUT GATE REFERENCE, LEVEL SHIFTER, AND DRIVER SWITCH CELL GATE DRAIN OUTPUT V- A2 1 14 A1 NC 2 13 NC GND 3 12 V+ NC 4 11 NC IN2 5 10 IN1 OUT2 6 9 OUT1 V- 7 8 VREF HI2-200/883 (METAL CAN) TOP VIEW V+ 10 A1 1 9 IN1 2 8 OUT1 GND 3 7 VREF A2 IN2 4 6 5 V- OUT2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI-200/883 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . .40V ±VSUPPLY to Ground (V+, V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V Analog Input Voltage, (+VS ) . . . . . . . . . . . . . . . . . . +VSUPPLY +2V Analog Input Voltage, (-VS ) . . . . . . . . . . . . . . . . . . . . -VSUPPLY -2V Digital Input Voltage, (+VA) . . . . . . . . . . . . . . . . . . . +VSUPPLY +4V Digital Input Voltage, (-VA). . . . . . . . . . . . . . . . . . . . . -VSUPPLY -4V Peak Current (S or D) (Pulse at 1ms, 10% Duty Cycle Max). . . . . . . . . . . . . . . . . . 40mA Continuous Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . ≤275°C Thermal Resistance θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 80 24 Metal Can Package . . . . . . . . . . . . . . . 160 75 Package Power Dissipation at +75oC Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . 0.76W/oC Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.62W/oC Package Power Dissipation Derating Factor above +75oC Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . 10.08mW/oC Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . 8.24mW/oC Recommended Operating Conditions Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC Operating Supply Voltage Range (±VSUPPLY) . . . . . . . . . . . . . . ±15V Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY Logic Low Level (VAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 0.8V Logic High Level (VAH) . . . . . . . . . . . . . . . . . . . . 2.4V to +VSUPPLY CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VREF = OPEN, GND = 0V, Unless Otherwise Specified. D.C. PARAMETERS Switch “ON” Resistance SYMBOL rDS CONDITIONS VA = 0.8V, VS = 10V, ID = -1mA, All Unused Channels VA = 0.8V VA = 0.8V, VS = -10V, ID = 1mA, All Unused Channels VA = 0.8V Source “OFF” Leakage Current IS(OFF) VS = +14V, VD = -14V, VA = 2.4V, All Unused Channels VA = 2.4V, VD = +14V, VS = -14V VS = -14V, VD = +14V, VA = 2.4V, All Unused Channels VA = 2.4V, VD = -14V, VS = +14V Drain “OFF” Leakage Current ID(OFF) VD = -14V, VS = +14V, VA = 2.4V, All Unused Channels VA = 2.4V, VD = +14V, VS = -14V VD = +14V, VS = -14V, VA = 2.4V, All Unused Channels VA = 2.4V, VD = -14V, VS = +14V Channel “ON” Leakage Current ID(ON) VD = VS = +14V, VA = 0.8V, All Unused Channels VA = 0.8V, VD = VS = -14V VD = VS = -14V, VA = 0.8V, All Unused Channels VA = 0.8V, VD = VS = +14V Low Level Input Current IAL High Level Input Current IAH Supply Current +ICC TEMPERATURE (oC) MIN MAX UNITS 1 25 - 70 Ω 2, 3 -55 to 125 - 100 Ω 1 25 - 70 Ω 2, 3 -55 to 125 - 100 Ω 1 25 -5 5 nA 2, 3 -55 to 125 -500 500 nA 1 25 -5 5 nA 2, 3 -55 to 125 -500 500 nA 1 25 -5 5 nA 2, 3 -55 to 125 -500 500 nA 1 25 -5 5 nA 2, 3 -55 to 125 -500 500 nA 1 25 -5 5 nA 2, 3 -55 to 125 -500 500 nA 1 25 -5 5 nA 2, 3 -55 to 125 -500 500 nA VAL = 0.8V All Channels VA = 2.4V 1 25 -1.0 1.0 µA 2, 3 -55 to 125 -1.0 1.0 µA VAH = 2.4V All Channels VAH = 4.0V 1 25 -1.0 1.0 µA 2, 3 -55 to 125 -1.0 1.0 µA 1 25 - 2.0 µA 2, 3 -55 to 125 - 2.0 µA 1 25 - 2.0 mA 2, 3 -55 to 125 - 2.0 mA All Channels VA = 0V All Channels VA = 3V 2 GROUP A SUBGROUPS HI-200/883 TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VREF = OPEN, GND = 0V, Unless Otherwise Specified. D.C. PARAMETERS Supply Current SYMBOL -ICC CONDITIONS GROUP A SUBGROUPS TEMPERATURE (oC) MIN MAX UNITS 1 25 -2.0 - µA 2, 3 -55 to 125 -2.0 - µA 1 25 -2.0 - µA 2, 3 -55 to 125 -2.0 - µA All Channels VA = 0V All Channels VA = 3V TABLE 2. A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VREF = OPEN, GND = 0V, Unless Otherwise Specified. PARAMETERS SYMBOL Turn “ON” Time tON Turn “OFF” Time tOFF GROUP A SUBGROUPS CONDITIONS CL = 35pF, RL = 1kΩ CL = 33pF, RL = 1kΩ TEMPERATURE (oC) MIN MAX UNITS 9 25 - 500 ns 10, 11 55 to 125 - 800 ns 9 25 - 500 ns 10, 11 55 to 125 - 650 ns TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (NOTE 1) Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VREF = OPEN, GND = 0V PARAMETERS SYMBOL Address Capacitance CA NOTE TEMPERATURE (oC) MIN MAX UNITS f = 1MHz, VAL = 0V 1 25 - 20 pF CONDITIONS Switches Input Capacitance CS (OFF) f = 1MHz, VAH = 5V, Measured Source to GND 1 25 - 20 pF Switch Output Capacitance CD (OFF) f = 1MHz, VAH = 5V, Measured Output to Ground 1 25 - 20 pF CD (ON) f = 1MHz, VAL = 0V, Measured Output to Ground 1 25 - 30 pF Drain to Source Capacitance CDS f = 1MHz, VAH = 5V 1 25 - 2.0 pF Off Isolation VISO f = 200kHz, VA = 2.4, RL = 1K, VGEN = 1VP-P, CL = 10pF 1 25 55 - dB Cross Talk VCT f = 200kHz, VA = 2.\4, RL = 1K, VGEN = 1VP-P, CL = 10pF 1 25 60 - dB f = 200kHz, VA = 0 to 4V, CL = 0.01µF 1 25 -10 10 mV Charge Transfer Error VCTE NOTE: 1. Parameters listed in Table 2 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-in) Final Electrical Test Parameters SUBGROUPS (Tables 1 and 2) 1 1 (Note 2), 2, 3, 9, 10, 11 Group A Test Requirements 1, 2, 3, 9, 10, 11 Groups C & D Endpoints 1 NOTE: 2. PDA applies to Subgroup 1 only. 3 HI-200/883 Test Circuits +VCC +VCC S D VS D S VD ID VIN IIN VIN -VCC GND GND -VCC FIGURE 2. ID (OFF) FIGURE 1. INPUT LEAKAGE CURRENT +VCC +VCC S VS S VD IS D ID(ON) VIN VIN GND -VCC GND V -VCC FIGURE 4. ID (ON) FIGURE 3. IS (OFF) +VCC I1 D S VIN GND I2 -VCC FIGURE 5. SUPPLY CURRENTS 4 FIGURE 6. CHARGE TRANSFER ERROR HI-200/883 Test Circuits (Continued) +VCC S D VIN VD GND -VCC FIGURE 7. RDS FIGURE 8. OFF CHANNEL ISOLATION FIGURE 9. CROSSTALK BETWEEN CHANNELS 5 HI-200/883 Switching Waveforms FIGURE 10. FIGURE 11. FIGURE 12. 6 HI-200/883 Burn-In Circuits FIGURE 13. HI-200/883 CERAMIC DIP FIGURE 14. HI-200/883 METAL CAN (TO-99) NOTES: 3. R1 = R2 = 10kΩ 4. C1 = C2 = 0.01µF (per socket) or 0.1µF (per row) 5. D1 = D2 = IN4002 or equivalent 6. |(V+) - (V-)| = 30V 7 HI-200/883 Schematic Diagrams TTL/CMOS REFERENCE CIRCUIT VREF CELL V+ R6 300 R2 5K QP2 QP1 QP3 VREF QN4 QP4 MP13 QP5 TO P2 QN1 R3 24.2K D3 QN2 MN14 R4 5.4K VLL R5 7.9K GND MN15 MN16 MN17 V- R7 100K GND SWITCH CELL A’ N11 V+ INPUT P11 N12 OUTPUT N13 V- P12 A’ 8 HI-200/883 Schematic Diagrams (Continued) DIGITAL INPUT BUFFER AND LEVEL SHIFTER V+ P3 P1 V+ P5 P4 N11 N1 P6 D1 P7 P8 N12 P10 P9 TO VLL R1 INPUT TO VREF N8 D2 200Ω N6 N9 P11 OUTPUT N13 N10 N7 P2 VA V- P12 N2 N5 N4 N3 VV- Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±±15V, VAH = 2.4V, VAL = 0.8V and VREF = Open 80 100 V+ = +10V V- = -10V VIN = 0V 60 ON RESISTANCE (Ω) ON RESISTANCE (Ω) 70 50 40 30 20 V+ = +12.5V V- = -12.5V 50 V+ = +15V V- = -15V 10 0 -50 -25 0 25 50 75 100 TEMPERATURE (oC) FIGURE 15. ON RESISTANCE vs TEMPERATURE 9 125 0 -15 -10 -5 0 5 ANALOG SIGNAL LEVEL (V) 10 FIGURE 16. ON RESISTANCE vs ANALOG SIGNAL LEVEL AND POWER SUPPLY VOLTAGE 15 HI-200/883 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±±15V, VAH = 2.4V, VAL = 0.8V and VREF = Open (Continued) 100 90 80 SWITCH CURRENT (mA) CURRENT (nA) IS(OFF) / ID(OFF) 10 ID(ON) 1.0 70 60 50 40 30 20 10 0.1 0 25 50 75 100 0 125 1 TEMPERATURE (oC) 2 3 4 5 6 7 VOLTAGE ACROSS SWITCH (±V) FIGURE 17. LEAKAGE CURRENT vs TEMPERATURE FIGURE 18. SWITCH CURRENT vs VOLTAGE 140 OFF ISOLATION (dB) 120 100 80 RL = 1kΩ 60 40 20 0 100Hz 1kHz 10kHz 100kHz 1MHz FREQUENCY (Hz) FIGURE 19. OFF ISOLATION vs FREQUENCY All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 HI-200/883 Die Characteristics DIE DIMENSIONS: DIE ATTACH: 54 mils x 79mils x 19 mils Material: Gold/Silicon Eutectic Alloy Temperature: Ceramic DIP - 460°C (Max) Temperature: Metal Can - 420°C (Max) METALLIZATION: Type: Aluminum Thickness: 16kÅ ±2kÅ WORST CASE CURRENT DENSITY: 2 x 105 A/cm2 at 25mA GLASSIVATION: Type: Nitride over Silox Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1kÅ Metallization Mask Layout HI-200 GND A2 2 IN 2 OUT 2 1 10 9 3 4 5 V- 11 V+ A1 6 VREF 8 IN 1 7 OUT 1