AUDO-NG/Future Family Overview January 2010 TC1797 4 MB 3 MB 180 MHz TC1768 133 MHz TC1767 2 MB 1.5 MB 80/133 MHz TC1766 80 MHz TC1796 150 MHz TC1766 80 MHz TC1736 80 MHz TC1762 66/80 MHz Bare QFP QFP BGA Die 144 176 416 1 MB AUDO NEXT GENERATION AUDO FUTURE 16.02.2010 Copyright © Infineon Technologies 2009. All rights reserved. Page 1 Feature Overview TC1797 TC1767 TC1736 TC1768 TC version 1.3.1 1.3.1 1.3.1 1.3.1 Frequency 150 / 180 MHz 80 / 133 MHz 80 MHz 133 MHz Program Flash 3 / 4 MB 2 MB 1 MB 3 MB Data Flash (w/e cycles) 64 KB (30k) 64 KB (30k) 32 KB (30k) 64 KB (up to 30k) Σ (w/o PCP, with Cache) 176 KB 104 KB 48 KB 136 KB PMI 40 KB 24 KB 8 KB 16 KB DMI 128 KB 72 KB 36 KB 112 KB Overlay 8 KB 8 KB 4 KB 8 KB PCP (max. frequency) 180MHz 80 / 133MHz - 133 MHz DMA Channels 16 8 8 16 ADC Σ Analog Inputs 48 36 24 32 ADC Channels 44 2 x 16 2 2 x 16 FADC Channels 1x4 1x4 1 - Σ Timed IO Up to 118 Up to 80 Up to 53 tbd GPTA® 2 GPTA® 1 GPTA® 1 GPTA® 2 GPTA® LTC 1 LTC 1 LTC - - Flexray 2 channels - - 2 channels CAN 4 / 128 2 / 64 2 / 64 3 / 64 SSC / ASC 2/2 2/2 2/2 2/2 MLI / MSC 2/2 1/1 1/1 -/- SENT - - - - EBU 32-bit - - - Package P/PG-BGA-416 PG-QFP-176 PG-QFP-144 Bare Die Temperatur (Tambient ) packaged - 40°C to +125°C - 40°C to +125°C - 40°C to +125°C - Core Flash SRAM Timer Interfaces Max. Temperatur (Tjunction) Bare Die 16.02.2010 Copyright © Infineon Technologies 2009. All rights reserved. 150°C Page 2 160°C w/ funct. Limitations TC1797 High End Powertrain Microcontroller TC1797 Core Flash SRAM TC version 1.3.1 Frequency 150 / 180 MHz Program Flash 3 / 4 MB Data Flash (w/e cycles) 64 KB (30k) Σ (w/o PCP, with cache) 176 KB PMI 40 KB DMI 128 KB Overlay 8 KB PCP (max. frequency) 180MHz DMA Channels 16 ADC Σ Analog Inputs 48 ADC Channels 44 FADC Channels 1x4 Σ Timed IO Up to 118 GPTA® 2 GPTA® LTC 1 LTC Flexray 2 channels CAN 4 / 128 SSC / ASC 2/2 MLI / MSC 2/2 SENT - EBU 32-bit Timer Interfaces Package P/PG-BGA-416 Temperatur (Tambient ) packaged - 40°C to +125°C 16.02.2010 Copyright © Infineon Technologies 2009. All rights reserved. Schedule n Qualified samples available Page 3 TC1767 Mid-range Powertrain Microcontroller TC1767 Core Flash SRAM TC version 1.3.1 Frequency 80 / 133 MHz Program Flash 2 MB Data Flash (w/e cycles) 64 KB (30k) Σ (w/o PCP, with Cache) 104 KB PMI 24 KB DMI 72 KB Overlay 8 KB PCP (max. frequency) 80 / 133MHz DMA Channels 8 ADC Σ Analog Inputs 36 ADC Channels 2 x 16 FADC Channels 1x4 Σ Timed IO Up to 80 GPTA® 1 GPTA® LTC 1 LTC Flexray - CAN 2 / 64 SSC / ASC 2/2 MLI / MSC 1/1 SENT - EBU - Timer Interfaces Package PG-QFP-176 Temperatur (Tambient ) packaged - 40°C to +125°C Max. Temperatur (Tjunction) Bare Die - 16.02.2010 Copyright © Infineon Technologies 2009. All rights reserved. Schedule n Qualified samples available Page 4 TC1736 Low End Powertrain Microcontroller TC1736 Core Flash SRAM TC version 1.3.1 Frequency 80 MHz Program Flash 1 MB Data Flash (w/e cycles) 32 KB (30k) Σ (w/o PCP, with Cache) 48 KB PMI 8 KB DMI 36 KB Overlay 4 KB PCP (max. frequency) - DMA Channels 8 ADC Σ Analog Inputs 24 ADC Channels 1 x 16, 1x 4 FADC Channels 4 Σ Timed IO Up to 53 GPTA® 1 GPTA® LTC - Flexray - CAN 2 / 64 SSC / ASC 2/2 MLI / MSC 1/1 SENT - EBU - Timer Interfaces Package PG-QFP-144 Temperatur (Tambient ) packaged - 40°C to +125°C Max. Temperatur (Tjunction) Bare Die - 16.02.2010 Copyright © Infineon Technologies 2009. All rights reserved. Schedule n Samples available Page 5 TC1768 Transmission Microcontroller TC1768 Core Flash SRAM TC version 1.3.1 Frequency 133 MHz Program Flash 3 MB Data Flash (w/e cycles) 64 KB (30k) Σ (w/o PCP, Cache) 136 KB PMI 16 KB DMI 112 KB Overlay 8 KB PCP (max. frequency) 133 MHz DMA Channels 16 ADC Σ Analog Inputs 32 ADC Channels 2 x 16 FADC Channels - Σ Timed IO tbd GPTA® 2 GPTA® LTC - Flexray 2 channels CAN 3 / 64 SSC / ASC 2/2 MLI / MSC -/- SENT - EBU - Timer Interfaces Package Bare Die Temperatur (Tambient ) packaged - Max. Temperatur (Tjunction) Bare Die 150°C 16.02.2010 Schedule n ES: Jan 10 n QS: Q4 2010 160°C w/ funct. Limitations Copyright © Infineon Technologies 2009. All rights reserved. Page 6