Migration guide for TriCore™ based Microcontrollers

T riCo re™ Fa mi ly
A P 3218 7
Migration guide for TriCore™ based Microcontrollers
A pp lic atio n No te
V1.0 2011-10
M icro co nt ro llers
Edition 2011-10
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
LEGAL DISCLAIMER
THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE
IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE
REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR
QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION
NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. INFINEON
TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND
(INCLUDING WITHOUT LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL
PROPERTY RIGHTS OF ANY THIRD PARTY) WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN
THIS APPLICATION NOTE.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the
failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life
support devices or systems are intended to be implanted in the human body or to support and/or maintain and
su stain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.
AP32187
Migration guide for TriCore™ based Microcontrollers
Dev ice1
Rev ision History: V1.0, 2011-10
Previous Version: none
Page
Subjects (maj or changes since last revision)
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
Application Note
3
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
Table of Contents
Table of Contents
1
Preface..................................................................................................................................... 5
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.3
2.3.1
2.3.2
2.3.3
AUDO NG to AUDO FUTURE .................................................................................................... 6
Migration Paths.......................................................................................................................... 6
TC1166 / TC1766 vs. TC1167 / TC1767...................................................................................... 6
Feature Comparison .................................................................................................................. 6
Design Compatibility.................................................................................................................. 7
Features, Peripherals & Software Compatibility............................................................................ 8
TC1796 vs. TC1197 / TC1797 .................................................................................................... 9
Feature Comparison .................................................................................................................. 9
Design Compatibility................................................................................................................ 10
Features, Peripherals & Software Compatibility.......................................................................... 12
3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
3.4.3
3.5
3.5.1
3.5.2
3.5.3
AUDO FUTURE to AUDO MAX ............................................................................................... 13
Migration Paths........................................................................................................................ 13
TC1736 vs. TC1724N / TC1724F.............................................................................................. 13
Feature Comparison ................................................................................................................ 13
Design Compatibility................................................................................................................ 14
Features, Peripherals & Software Compatibility.......................................................................... 15
TC1167 / TC1767 vs. TC1728N................................................................................................ 16
Feature Comparison ................................................................................................................ 16
Design Compatibility................................................................................................................ 17
Features, Peripherals & Software Compatibility.......................................................................... 18
TC1167 / TC1767 vs. TC1782N / TC1782F............................................................................... 19
Feature Comparison ................................................................................................................ 19
Design Compatibility................................................................................................................ 20
Features, Peripherals & Software Compatibility.......................................................................... 21
TC1197 / TC1797 vs. TC1793N / TC1793F............................................................................... 22
Feature Comparison ................................................................................................................ 22
Design Compatibility................................................................................................................ 23
Features, Peripherals & Software Compatibility.......................................................................... 23
4
4.1
4.2
4.3
AUDO MAX............................................................................................................................. 25
Placement options................................................................................................................... 25
TC1728  TC1782.................................................................................................................. 25
TC1791  TC1798.................................................................................................................. 26
Application Note
4
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
Preface
1
Preface
The AUDO Family with TriCore™ is a unified, superscalar, 32-bit microcontroller architecture optimized for
embedded real-time applications. Compatibility, scalability, and maximum re-use within the family result in a
broad portfolio of TriCore™-based products and features, addressing advanced performance in automotive
power train, safety and industrial applications.
Based on the industry leading TriCore™ high performance microcontroller core running at up to 300MHz, the
AUDO Family offers the best of three worlds: Reduced Instruction Set Computer (RISC), Complex Instruction
Set Computer (CISC) and Digital Signal Processing (DSP) functionality.
While Infineon strives to continuously improve the TriCore™ based microcontrollers we respect the efforts our
customers put into the product development both in terms of software and hardware. Infineon therefore provides
a broad product portfolio of devices within one family, allowing engineers to choose the right combination of
features meeting their requirements. In addition Infineon provides a migration path to allow an easy transition to
the next device generation.
Software that has been developed on existing controllers can generally be reused on a new core. All members
of the AUDO family are binary compatible and share the same development tools. Since in most cases the
software requires changes to accomplish for newly introduced or improved peripherals, it is recommended to
rebuild the code in order to take full advantage from improvements in the core revision.
Infineon offers microcontrollers for both the automotive as well as the industrial environment. The naming
convention was slightly changed with the AUDO MAX family in order to reflect the availability of FlexRay.
 TC11xx, TC17xxN Industrial and Multimarket devices
 TC17xx, TC17xxF Automotive devices
While several devices are electrically compatible, they are specified and tested differently, e.g. regarding the
temperature range. In addition the automotive devices are qualified according to AEC-Q100.
Based on the technology node the TriCore™ microcontrollers are grouped into families where the individual
devices share a common basic structure including the core revision, the bus structure as well as the peripheral
feature set. The following table shows the devices per family for industrial and automotive applications.
The tables in the following paragraphs only give the base variants in each family. Please note that there might
be several variants offered that differ in terms of frequency, memory sizes and/or temperature range.
Table 1
TriCore™ based microcontrollers
TC1762
AUDO NG
TC1164
TC1166
AUDO FUTURE
AUDO MAX
TC1766
TC1796
TC1736
TC1167
TC1197
TC1724N (no FlexRay)
TC1728N
TC1782N
TC1784N
TC1793N
TC1798N
TC1767
TC1797
TC1724F (with FlexRay)
TC1728N
TC1782F
TC1784F
TC1793F
TC1798F
Typically devices from a newer family implement a lot of improvements both in terms of the core as well as in
the peripherals. This document can only list the major items that changed between families.
Attention: For further details please refer to the Data Sheets and User Manuals, respectively. In case of
any inconsistency Data Sheet and User Manual take precedence.
Application Note
5
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO NG to AUDO FUTURE
2
AUDO NG to AUDO FUTURE
2.1
Migration Paths
The following migration possibilities exist:
AUDO NG
TC1166 / TC1766
TC1796
AUDO FUTURE
TC1167 / TC1767
TC1197 / TC1797
QFP-176, performance upgrade
BGA-416, performance upgrade
2.2
TC1166 / TC1766 vs. TC1167 / TC1767
2.2.1
Feature Comparison
Core
Flash
SRAM
PCP
DMA
ADC
Timer
Interfaces
TC1166 & TC1766
1.3
80 MHz
1.5 MB
32 KB
88 KB
24 KB
56 KB
8 KB
80 MHz
12 KB
8 KB
8
32
TC Version
Frequency (max.)
Program Flash
Data Flash
 (w/o PCP, Cache)
PMI
DMI
Overlay
Frequency (max.)
Code Memory
Parameter Memory
Channels
 Analog Inputs
ADC Modules x Channels 1 x 32
FADC Channels
2
80
 Timed IO (max.)
GPTA
LTC
CAN nodes / objects
SSC / ASC
MLI / MSC
1
2 / 64
2 /2
2 /1
LQFP 176
-40 °C ... +85 °C
Package
Temperature (ambient)
Application Note
6
TC1167 & TC1767
1.3.1
133 MHz
1.0 MB (TC1767: 2.0 MB)
64 KB
96 KB
24 KB
72 KB
8 KB
133 MHz
16 KB
8 KB
8
32
2 x 16
4
80
1
1
2 / 64
2 /2
1 /1
LQFP 176
-40 °C ... +85 (125) °C
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO NG to AUDO FUTURE
2.2.2
Design Compatibility
Since the basic electrical parameters as well as the positions of most pins remained unchanged, a combined
layout for the AUDO NG and AUDO FUTURE devices is feasible.
Care must be given to changes due to added or changed functionality in the newer devices.
The power supply requirements are almost identical; in general a PSU designed for the TC1166 can be used
without changes. Due to improvements in the core design, the maximum required supply current is identical,
even with the TC1167 running at a significantly higher clock rate.
The TC1167 implements a 5V ADC which can also be used with 3.3V. Still the electrical parameters of the
external ADC circuitry should be checked.
The following tables list the changes and additions starting with pin1.
Table 2
Changed/Removed Functionality
Pin
1...8
13...19
20
TC1166 & TC1766
OCDS2
OCDS2
IO (P5.15)
TC1167 & TC1767
OCDS2 removed
OCDS2 removed
V DDP
21
NC
V DD
22
V SSAF
V SS
54
V DDM 3.3V max.
V DDM 5.0V max.
86..88, 90
89
IO & HWCFG[3:0]
NC
HWCFG[3:0] removed
V DD
91
IO (P1.0)
V DDP
92
IO (P1.1)
V SS
145...148
IO (P0.0...0.3)
166, 167, 173, 174
IO (P0.4...0.7)
145...152, 166...169, IO & SWCFG[15:0]
173...176
Table 3
IO (P0.0...0.3) & HWCFG0...3
IO (P0.4...0.7) & HWCFG4...7
SWCFG[15:0] removed
Added Functionality
Pin
9
111...115
116...119
128...138
142...144
156...159
71...73, 76...80, 93,
107..110, 116, 119,
156...159, 161...163,
165
Application Note
TC1166 & TC1766
TRCLK for OCDS2
JTAG only
JTAG only
SSC/ASC only
ASC/CAN only
MSC0 only
TC1167 & TC1767
additional IO (P5.15, pin 20 of TC1x66)
additional DAP
additional IO
additional timed IO (GPTA0)
additional timed IO (GPTA0)
additional IO & timed IO (GPTA0)
additional timed IO (LTCA2)
7
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO NG to AUDO FUTURE
2.2.3
Features, Peripherals & Software Compatibility
For the TC1167 the same tool chains can be used as for the AUDO NG devices.
The core revision was updated from 1.3 to 1.3.1. Aside of the increase in maximum speed the access to data
and code including branch prediction has been improved. In combination with the increased clock rate the
performance increase can be in the range of 60-70 %.
The clock rate of the PCP has been increased from 80MHz to 133MHz and the code memory increased. For
PCP frequencies exceeding 80 MHz, 2:1 mode vs. the FPI bus has to be enabled.
The TC1167 provides an improved memory system providing faster access times as well as more flexibility. The
SRAM in the DMI can be used as data RAM as well as data cache. For both PMI and DMI the split between
RAM and CACHE can be software configured. The TC1167 and TC1767 provide more data flash and the
TC1767 a bigger amount of program flash.
OCDS2 (Program Trace) is no more supported - please use the Emulation device.
Below is a description of the more important changes in the peripherals.
The TC1167 implements two independent 5V ADC modules. These can also be used with 3.3V and additionally
use an alternative reference voltage applied at channel 0.
The General Purpose Timer Array (GPTA v5) in the TC1167 provides an additional block of 32 Local Timer
Cells. The output multiplexer allows a much more flexible routing to I/O lines, output lines, clock inputs, other
on-chip peripherals and other GPTA cells. The local and global bypass features of the LTC have been improved
allowing a group of Local Timer Cells (LTCs) to drive a specific output pin or to perform coherent cell update.
The PLL has been changed to allow easier reprogramming.
The reset system now offers an additional system reset. For several reset sources (e.g. WDT, ESRx, and SW)
the type of reset generated can be configured.
The CAN register mapping has been changed in order to become common for all existing and future of AUDO
Future derivatives.
The serial interfaces ASC/SSC implement some bug fixes and improvements in configuration flexibility.
For the SSC interfaces the flexibility of the IO routing has been significantly enhanced.
Application Note
8
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO NG to AUDO FUTURE
2.3
TC1796 vs. TC1197 / TC1797
2.3.1
Feature Comparison
Core
Flash
SRAM
PCP
DMA
ADC
Timer
Interfaces
TC Version
Frequency (max.)
Program Flash
Data Flash
 (w/o PCP, Cache)
PMI
DMI
DMU
Overlay
Frequency (max.)
Code Memory
Parameter Memory
Channels
 Analog Inputs
ADC Modules / Channels
FADC Channels
 Timed IO (max.)
GPTA
LTC
FlexRay
CAN nodes / objects
SSC / ASC
MLI / MSC
EBU
Package
Temperature (ambient)
Application Note
9
TC1796
1.3
150 MHz
2.0 MB
128 KB
208 KB
TC1197 & TC1797
1.3.1
180 MHz
2.0 MB / 4.0 MB
64 KB
176 KB
64 KB
64 KB
80 KB
75 MHz
32 KB
16KB
16
44
2 x 16
4
112
40 KB
128 KB
8 KB
180 MHz
32 KB
16KB
16
44
3 x 16
4
112
2
1 (64 cells)
4 / 128
2 /2
2 /2
1
BGA-416
-40 °C ... +125 °C
2
1 (32 cells)
1 (TC1797 only)
4 / 128
2 /2
2 /2
1
BGA-416
-40 °C ... +125 °C
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO NG to AUDO FUTURE
2.3.2
Design Compatibility
Since the basic electrical parameters as well as the positions of most balls remained unchanged, a combined
layout for the AUDO NG and AUDO FUTURE devices is feasible.
Care must be given to changes due to added or changed functionality in the newer devices.
The power supply requirements are almost identical; in general a PSU designed for the TC1796 can be used
without changes. Due to improvements in the core design, the maximum required supply current for the TC1197
is actually lower, even with the TC1197 running at a significantly higher clock rate.
The TC1197 implements three 5V ADCs which can also be used with 3.3V. Still the electrical parameters of the
external ADC circuitry should be checked.
Figure 1
Ball out changes on TC1797 compared to TC1796
1
A
N.C.
2
P2.9
3
4
5
6
P2.13 P2.1 5 P0.1 4 P0. 5
7
P0. 2
8
P0. 1
N.C.
VDDP
VSS
A
VSS
VDD
B
TRST
TM S
(t op view)
VDDP VDDP XT 2 AL XT1 AL
F
F3
G
VDDE VDDE VDDE VDDE
BU
BU
BU
BU
H
P1 1.3 P1 2.6 P1 2.7 P1 1.0
J
P1 1.7 P1 1.4 P1 1.1 P1 1.2
K
P6.4
P6.8
L
26
TC1797 Pinning
P6.14 P6.10
VDDP
P9. 9 ESR1 ESR0
25
D
F
P8.6
P9. 3
24
TCK
P6.9
P8.5
23
VDD
P6.6
P8.7
22
C
P6.12 P6.11
K
P5.6
VDDF
P5.13 P5.1 4
P9. 1
L3
21
P9 .13
E
VSS
P5.7
20
P9 .14
D
P8.2
19
VDD
P0.1 5 P0.1 3 P0.1 1 VDDP VSS
P8.3
18
VDDF
P5.12 P5.1 5
P9. 0
L3
TDO
P2.2
P8.4
17
VSS
P2.11 P2.1 2 P0.1 2 P0.1 0 P0. 8
P2.3
P8.1
P5.2
16
VDD
P2.8
P2.4
J
P5.1
15
VSS
P2.5
H
14
VDDP
C
P6.5
P3 .1
13
N.C.
P2.10 P2.1 4 P0.9
P6.7
P3 .5
12
P9. 2 P9. 10
P2.7
V DDF
P8.0
VDD
L3
P0. 0 P3. 14
11
TEST
VDDP
MODE
P2.6
P6.15 P6.13
10
PO
RST
B
G
9
P0. 6
P0. 4
P0. 3 P3. 15
P0. 7
P3 .6
P3 .3
P3 .0
P5.0
P5.3
P3. 7 P3. 10
P3 .9
P3 .4
P3.2
P5.5
VDD
P3 .8 P3 .12 P3 .13 P3 .11 VDDP
VSS
P1.15 P1.14 P1.13 P1.1 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P5.4
P5.9
P5.1 0 P5.1 1 P9. 6
P9. 8 P9. 11
VSS
VDD
P5.8
P9. 7 P9. 12 VDDP
VSS
VSS
VSS
VSS
P9.4
P9. 5
VSS
P111
1.
VDD
O SC3
VSS VDD
O SC OSC
TDI
E
F
VSS
VSS
P1 1.5 P1 1.6
L
VDDE
P110 . P1 1.9 P1 1.8
BU
M
M
P1.10
P1.9
P1.8
P1.5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N
P1.3
P1.7
P1.6
P1.4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P1 1.
13
P
P1.2
P1.1
P1.0
P1.1 2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R
SBRA
M
P7.1
P7.0
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P1 1.
14
P11.
15
P11.
12
N
VDD
P1 2.1 P1 2.2 P1 2.0
P
VSS
VSS
P1 2.3 P1 2.5 P1 2.4
R
T
U
T
P7.6
P7.5
P7.4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDE
P1 3.1 P1 3.3 P1 3.0
BU
U
AN23
P7.7
P7.3
P7.2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P1 3.6 P1 3.9 P1 3.5 P1 3.2
V
AN22 AN21 AN19 AN16
VDD
P1 3.
P1 3.8 P1 3.4
V
13
W
Y
Changed/Removed Functionality
AN20 AN17 AN13 VDDM
VSS
P1 3.7
W
P13.
14
P13.
10
Y
AA
12
VDDE
P1 4.2
BU
Additional Functionality
AN18 AN14 AN10 VSSM
P1 4.0
P13.
AA
AN15 AN11
AN5
AN2
P1 4.3 P1 4.6 P1 4.1
P13.
11
AB
AN12
AN3
AN7
VDD
P13.
15
AB
AC
AD
AN8
AN6
AN9
AN4
AN1
AN32 AN38 AN42
VAGN
VDDA
AN26 AN2 4
D1
F
AN34 AN40 AN35
VARE
VARE
AN27 AN2 5
F1
F2
AE
AN0
AN33 AN36 AN41
VARE
VFAG VDDM
AN28 AN30
F0
ND
F
AF
N.C.
AN37 AN39 AN43
VAGN
VFAR VSSM
AN29 AN31
D0
EF
F
1
2
3
4
5
6
7
8
9
VSS
P4 .0
VDD
P4 .2
P4 .4
P4 .5
P4.8
P4.12 P10.5 VDDP
VSS
VDDE
BU
VSS
VDD
N. C.
VDDE
BU
P4 .11 P4.15 P10.2 VDDP P15. 5 P16. 1 P15 .3 P15 .2 P15 .1 P16 .2
P4 .1
P4 .3
P4 .7
P4 .6
P4 .9
P4 .10 P4 .14 P10.3 P10.1 VDDP P16. 0 P15. 6
P4 .13 P10.4 P10.0 VDDP P15. 4 P15. 7 P16 .3
P15 .
12
10
11
12
19
13
14
15
16
17
18
P15 .
11
P1 4.5 P1 4.4
P1 4.
P1 4.9 P1 4.7
AC
N.C.
P1 4.
15
P14.
11
P1 4.8
AD
P14.
13
P14.
10
AE
VSS
12
P15 .0
N.C.
N.C.
P1 4.
14
P15 .8 P15 .9
P1 5.
10
P1 5.
13
P1 5.
14
P15.
15
N.C.
22
23
24
25
26
20
21
AF
The following tables list the changes and additions clockwise starting with the top left corner.
Application Note
10
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO NG to AUDO FUTURE
Table 4
Changed/Removed Functionality
Ball
A21
B21
C21
D21
G23
TC1796
P10.0
P10.1
P10.2
P10.3
NC
TC1197 & TC1797
P9.9
P9.10
P9.11
P9.12
V DDPF
G24
TSTRES
V DDPF3
J24...R26,
J23, K23, N23
(24 balls)
AC13, AC14, AD13,
AD14, AE13,
AF11...13
AD9
A[23:0]
(aligned or non-aligned address mode)
address pins are shifted by two LSBs
(aligned address mode only)
additional IO (P11.x / P12.x)
LTCA2 IN/OUT 0...7
(LTCA2 has only 32 cells)
V SSAF
V AREF2
R1
V DDSBRAM
NC
P4
K10...U12 (17 balls)
SYSCLK
TR[15:0], TRCLK
EXTCLK0
V SS (OCDS2 removed)
Table 5
LTCA2 IN/OUT 32..39
Additional Functionality
Ball
A5, B5, C5, C6, D5,
D6
A6...9, B6...8, C8
A13...17, B13, B14,
B16, B17, C14,
C16...18, D17
C26
D26
D25, E24, E25, F24
T24...AE26,
U23, AA23
(32 balls)
AD17...22,
AE17...21, AF17...25
TC1796
IO
TC1197 & TC1797
additional FlexRay (TC1797 only)
IO
IO
additional timed IO (GPTA0/1)
additional timed IO (GPTA0/1)
BRKIN
BRKOUT
JTAG only
D[31:0]
additional IO (P9.13)
additional IO (P9.14)
additional DAP
additional IO (P13.x / P14.x)
additional timed IO (GPTA0/1)
EBU control
additional IO (P15.x / P16.x)
AC15, AD15, AE14,
AE15, AF14, AF15
SSC0
additional IO (P10.x)
T2, T3, R3
P3
N3
M1...3, L1...4
H3
IO
IO
IO/MLI
IO/MLI
NC
additional AD2EMUX0/1
additional EXTCLK1
additional SLSO10
additional timed IO (GPTA0/1)
V DDFL3
E1, E2, F1, F2, G1,
G2
IO/ASC/CAN
additional FlexRay (TC1797 only)
Application Note
11
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO NG to AUDO FUTURE
2.3.3
Features, Peripherals & Software Compatibility
For the TC1197 the same tool chains can be used as for the AUDO NG devices.
The core revision was updated from 1.3 to 1.3.1. Aside of the increase in maximum speed the access to data
and code including branch prediction has been improved. In conjunction with the increased clock rate the
performance increase can be in the range of 30-50 %.
The clock rate of the PCP has been increased from 75MHz to 180MHz and the code memory increased. For
PCP frequencies exceeding 90 MHz, 2:1 mode vs. the FPI bus has to be enabled.
The TC1197 provides an improved memory system providing faster access times as well as more flexibility. The
SRAM in the DMI can be used as data RAM as well as data cache. For both PMI and DMI the split between
RAM and CACHE can be software configured. The TC1197 and TC1797 provide 64KB of data flash
(TC1796: 128KB) and there are devices available with up to 4MB of program flash.
OCDS2 (Program Trace) is no more supported please use the Emulation device.
Below is a description of the more important changes in the peripherals.
The TC1197 implements three independent 5V ADC modules. These can also be used with 3.3V and
additionally use an alternative reference voltage applied at channel 0.
The number of cells in the LTCA block of the General Purpose Timer Arrays (GPTA v5) has been downsized to
32 Local Timer Cells. The output multiplexer allows a much more flexible routing to I/O lines, output lines, clock
inputs, other on-chip peripherals and other GPTA cells. The local and global bypass features of the LTC have
been improved allowing a group of Local Timer Cells (LTCs) to drive a specific output pin or to perform coherent
cell update.
The PLL has been changed to allow easier reprogramming.
The reset system now offers an additional system reset. For several reset sources (e.g. WDT, ESRx, and SW)
the type of reset generated can be configured.
While the TC1197 provides the same number of CAN nodes and message objects, the CAN register mapping
has been changed in order to become common for all existing and future of AUDO FUTURE derivatives.
The serial interfaces ASC/SSC implement some bug fixes and improvements in configuration flexibility.
For the SSC interfaces the flexibility of the IO routing has been significantly enhanced.
Application Note
12
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO FUTURE to AUDO MAX
3
AUDO FUTURE to AUDO MAX
Attention: The AUDO MAX family of devices is not yet fully released. Therefore all information given in
the following paragraphs should be considered preliminary!
3.1
Migration Paths
The following migration possibilities exist:
AUDO FUTURE
TC1736
TC1167 / TC1767
TC1197 / TC1797
AUDO MAX
TC1724N / TC1724F
TC1728N
TC1782N / TC1782F
TC1793N / TC1793F
QFP-144, cost improvement ¹)
QFP-176, cost improvement
QFP-176, performance upgrade
BGA-416, performance upgrade
¹)...limited feature compatibility, not pin compatible
3.2
TC1736 vs. TC1724N / TC1724F
3.2.1
Feature Comparison
Core
Flash
SRAM
PCP
DMA
ADC
Timer
Interfaces
Package
Temperature (ambient)
Application Note
TC Version
Frequency (max.)
Program Flash
Data Flash
 (w/o PCP, Cache)
PMI
DMI
Overlay
Frequency (max.)
Code Memory
Parameter Memory
Channels
TC1736
1.3.1
80 MHz
1.0 MB
32 KB
48 KB
8 KB
36 KB
4 KB
8
24
 Analog Inputs
ADC Modules x Channels 2 / 32
FADC Channels
2
53
 Timed IO (max.)
GPTA
GPT12
CCU6
FlexRay
CAN nodes / objects
SSC / ASC
MLI / MSC
1
2 / 64
2 /2
1 /1
LQFP 144
-40 °C ... +125 °C
13
TC1724N & TC1724F
1.3.1
133 MHz
1.5 MB
64 KB
152 KB
24 KB
120 KB
8 KB
133 MHz
24 KB
8 KB
16
28
2 / 40
2
77
1
2
1
1 (TC1724F only)
3 / 64
4 /2
1 /1
LQFP 144 (ePAD)
-40 °C ... +125 °C
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO FUTURE to AUDO MAX
3.2.2
Design Compatibility
While the TC1724 is the predecessor of the TC1736 in terms of the applications targeted it has not been
designed to be a pin compatible replacement. So the following description is given to assist cu stomers that are
already familiar with the TC1736 to create or change a design for the TC1724.
The new AUDO MAX family of devices requires a core supply of 1.3V vs. 1.5V for the AUDO FUTURE devices.
The new TC1724 has an integrated voltage regulator (EVR), which can be used to create a single supply
design. The device features an internal supply watchdog end there is no need for external power sequencing.
For the single supply scheme special care must be given to the power dissipation of the total device. If the EVR
is supplied with 5V the system frequency is limited to 80MHz. In order to reach the full 133MHZ, an additional
external pass device for the 3.3V rail has to be added.
If the 5V is not required the EVR can be fed with 3.3V and there is no need for an external pass device.
The power supply currents at a clock of 80MHz are very similar to the TC1736. If the TC1724 is run at 133MHz
the currents for the core supply are higher. Since the ADC and the FADC at the TC1724 use a common supply,
the current required is the sum of the individual currents at the TC1736.
A PSU originally designed for the TC1736 has to be checked accordingly.
The TC1724 uses an LQFP package with exposed pad to reduce the thermal resistance. Utilizing the exposed
pad is important namely if the internal voltage regulator is used.
The number of power supply pins has been significantly reduced, allowing now for 95 digital IO pins vs. 70 at
the TC1736. If the TC1724 is used in a layout originally designed for the TC1736 care must be given to not pull
these IO pins low which would shorten the respective power supply.
Application Note
14
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO FUTURE to AUDO MAX
3.2.3
Features, Peripherals & Software Compatibility
For the TC1724 the same tool chains can be used as for the AUDO FUTURE devices, namely since the core
revision and the memory configuration remains the same.
The TC1724 provides significantly more SRAM for data – 152KB vs. 48KB.
In addition both the SRAM in DMI and PMI can be ECC protected.
The TC1724 has an additional PCP (Peripheral Co Processor) which can run at the full 133MHz and has 24KB
of local code memory and 8KB parameter memory.
The number of DMA channels has been increased to 16 in two DMA blocks.
The TC1728 provides several measures targeted at safety and security applications. Amongst others these
measures include error detection on the local bus, a bus monitor unit (BMU) a memory checker module and a
Flexible CRC Engine (FCE).
The Flexible CRC Engine (FCE) provides a parallel implementation of one or more Cyclic Redundancy Code
(CRC) algorithms. The standard CRC polynomial implemented in the FCE module is the IEEE 802.3 Ethernet
CRC32. The FCE is meant to be used as a hardware acceleration engine for software applications or operating
systems services using CRC signatures.
Below is a description of the more important differences regarding the peripheral modules.
The TC1724 can use a peripheral clock of 110MHz instead of 80MHz, allowing several peripherals like CAN,
ASC, SSC, MSC, MLI and the timers to achieve higher data rates and timer resolution. Please note that the
core and bus clock have to have a ratio of 1:1 or 1:2, so if the peripheral clock of 110MHz is used the core clock
is also limited to 110MHz.
The TC1724 includes four high-speed synchronous serial interfaces (SSC) instead of two.
The TC1724F incorporates an E-Ray IP-module with two channels performing communication according to the
FlexRay™ 1) protocol specification v2.1.
The MultiCAN module implemented provides three independent CAN nodes instead of two. The number of
available message objects is 64.
In addition to the GPTA the TC1724 incorporates several additional timer units: one Capture Compare Units
CCU6 and two general purpose timer units (GPT12).
The CCU6 provide two independent timers (T12, T13), which can be used for PWM generation, especially for
AC-motor control or power conversion stages. Additionally special control modes for block commutation and
multi-phase machines are supported.
The GPT12E unit represents a very flexible multifunctional timer/counter structure which may be used for many
different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse
generation, or pulse multiplication. Its functionality includes enhanced incremental interface modes and clock
prescaler support.
The two ADC modules now provide 40 input channels whereof max. 28 are available on input pins. All ADC
input channels now include broken wire detection. The maximum ADC clock has been increased from 10MHz to
18MHz.
The FADC provides a significantly shorter conversion time namely if the increased peripheral clock of 110MHz
is used.
Application Note
15
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO FUTURE to AUDO MAX
3.3
TC1167 / TC1767 vs. TC1728N
3.3.1
Feature Comparison
Core
Flash
SRAM
PCP
DMA
ADC
Timer
Interfaces
Power Supply
Package
Temperature (ambient)
Application Note
TC Version
Frequency (max.)
Program Flash
Data Flash
 (w/o PCP, Cache)
PMI
DMI
Overlay
Frequency (max.)
Code Memory
Parameter Memory
Channels
 Analog Inputs
ADC Modules / Channels
FADC Channels
 Timed IO (max.)
GPTA
LTCA / cells
GPT12
CCU6
FlexRay
CAN nodes / objects
SSC / ASC
MLI / MSC
TC1167 & TC1767
1.3.1
133 MHz
1.0 MB (TC1767: 2.0 MB)
64 KB
96 KB
TC1728N
1.3.1
133 MHz
1.5 MB
64 KB
152 KB
24 KB
72 KB
8 KB
133 MHz
16 KB
8 KB
8
32
24 KB
120 KB
8 KB
133 MHz
24 KB
8 KB
16
36
2 / 32
4
80
2 / 40
2
93
1
1 / 32
2 / 64
2 /2
1 /1
3 supplies
LQFP 176
-40 °C ... +85 (125) °C
1
2
1
3 / 64
4 /2
1 /1
single supply EVR
LQFP 176 (ePAD)
-40 °C ... +125 °C
16
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO FUTURE to AUDO MAX
3.3.2
Design Compatibility
The biggest changes affecting the hardware design are the supply concept and the use of an LQFP-176 with
exposed pad.
The new AUDO MAX family of devices requires a core supply of 1.3V vs. 1.5V for the AUDO FUTURE devices.
The new TC1728 has an integrated voltage regulator (EVR), which can be used to create a single supply
design. The device features an internal supply watchdog end there is no need for external power sequencing.
For the single supply scheme special care must be given to the power dissipation of the total device. If the EVR
is supplied with 5V the system frequency is limited to 80MHz. In order to reach the full 133MHZ, an additional
external pass device for the 3.3V rail has to be added.
If the 5V is not required the EVR can be fed with 3.3V and there is no need for an external pass device.
Overall the power supply currents are very similar to the TC1167. Since the ADC and the FADC at the TC1728
use a common supply, the current required is the sum of the individual currents at the TC1167.
Together with the changed core voltage this has to be taken into account if a PSU designed for the TC1167
should be re-used.
The TC1728 uses an LQFP package with exposed pad to reduce the thermal resistance. Utilizing the exposed
pad is important namely if the internal voltage regulator is used.
The number of supply pins has been reduced to gain on IO capability. If the TC1728 is used in a layout
designed for the TC1167 care must be given to not pull these IO pins low which would shorten the respective
power supply.
Due to a number of peripheral modules being added it is impractical to list all pins with changed functionality.
Therefore the table below only lists pins which changed from being power supply to IO.
Table 6
Changed Functionality from power supply to IO
Pin
11
TC1167 & TC1767
V DDP
TC1728N
IO (P9.7) &, GPTA, CCU6
12
V SS
IO (P9.8) & GPTA, CCU6
23...26
V DDAF V DDMF VSSMF V FAREF
IO (P10.0...P10.3) & SSC
82...85
V SS VDDMF VSSMF VFAREF
IO (P8.5...P8.8) & GPTA, CCU6
89
V DD
IO (P8.9) & GPTA, SSC
99
V DD
IO (P1.4) & GPTA, CCU6
100
V DDP
IO (P8.12) & GPTA
123...125
V DD VDDP VSS
IO (P8.x) & GPTA, CCU6, SSC
139...141
V DDP VSS V DDFL3
IO (P8.x) & GPTA, CCU6, GPT, SSC
170...172
V DD VDDP VSS
IO (P9.4...P9.2) & GPTA, CCU6
Application Note
17
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO FUTURE to AUDO MAX
3.3.3
Features, Peripherals & Software Compatibility
For the TC1728 the same tool chains can be used as for the AUDO FUTURE devices, namely since the core
revision and the memory configuration remains the same.
The TC1728 provides significantly more SRAM for data – 120KB vs. 72KB.
In addition both the SRAM in DMI and PMI can be ECC protected.
The PCP has access to 24KB of code memory instead of 16KB.
The number of DMA channels has been increased to 16 in two DMA blocks.
The TC1728 provides several measures targeted at safety and security applications. These measures e.g.
include error detection on the local bus, a bus monitor unit (BMU) a memory checker module and a Flexible
CRC Engine (FCE).
The FCE is meant to be used as a hardware acceleration engine for software applications or operating systems
services using CRC signatures.
Below is a description of the more important changes in the peripherals.
The TC1728 can use a peripheral clock of 110MHz instead of 80MHz, allowing several peripherals like CAN,
ASC, SSC, MSC, MLI and the timers to achieve higher data rates and timer resolution. Please note that the
core and bus clock have to have a ration of 1:1 or 1:2, so if the peripheral clock of 110MHz is used the core
clock is also limited to 110MHz.
The TC1728 includes four high-speed synchronous serial interfaces (SSC) instead of two.
The MultiCAN module implemented provides three independent CAN nodes instead of two. The number of
available message objects is 64.
The separate block of 32 local timer cells (LTCA) has been removed from the GPTA.
The TC1728 incorporate several additional timer units: one Capture Compare Units CCU6 and two general
purpose timer units (GPT12).
The CCU6 provide two independent timers (T12, T13), which can be used for PWM generation, especially for
AC-motor control or power conversion stages. Additionally special control modes for block commutation and
multi-phase machines are supported.
The GPT12E unit represents a very flexible multifunctional timer/counter structure which may be used for many
different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse
generation, or pulse multiplication. Its functionality includes enhanced incremental interface modes and clock
prescaler support.
The two ADC modules now provide 40 input channels whereof max. 36 are available on input pins. All ADC
input channels now include broken wire detection. The maximum ADC clock has been increased from 10MHz to
18MHz.
The FADC has two differential inputs instead of four and provides a significantly shorter conversion time namely
if the increased peripheral clock of 110MHz is used.
Application Note
18
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO FUTURE to AUDO MAX
3.4
TC1167 / TC1767 vs. TC1782N / TC1782F
3.4.1
Feature Comparison
Core
Flash
SRAM
PCP
DMA
ADC
Timer
Interfaces
Package
Temperature (ambient)
Application Note
TC Version
Frequency (max.)
Program Flash
Data Flash
 (w/o PCP, Cache)
PMI
DMI
Overlay
Frequency (max.)
Code Memory
Parameter Memory
Channels
 Analog Inputs
ADC Modules / Channels
FADC Channels
 Timed IO (max.)
GPTA
LTCA / cells
FlexRay
CAN nodes / objects
SSC / ASC
MLI / MSC
TC1167 & TC1767
1.3.1
133 MHz
1.0 MB (TC1767: 2.0 MB)
64 KB
96 KB
TC1782N & TC1782F
1.3.1
180 MHz
2.5 MB
128 KB
176 KB
24 KB
72 KB
8 KB
133 MHz
16 KB
8 KB
8
36
40 KB
128 KB
8 KB
180 MHz
32 KB
16 KB
16
36
2 x 16
4
80
2 x 16
4
80
1
1 / 32
2 / 64
2 /2
1 /1
LQFP 176
-40 °C ... +85 (125) °C
1
1 / 32
1 (TC1782F only)
3 / 128
3 /2
1 /1
LQFP 176 (ePAD)
-40 °C ... +125 °C
19
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO FUTURE to AUDO MAX
3.4.2
Design Compatibility
The TC1782 provides very good pin compatibility to the TC1167 with two major differences:


core supply voltage of 1.3V instead of 1.5V
two swapped supply pins (V DD <=> V DDP )
Table 7
Sw apped supply pins
TC1167 & TC1767
TC1782N & TC1782F
Due to the increased operating frequency the power supply current for the core (1.3V) is significantly higher.
The other power supply currents are similar to the TC1167.
The TC1782 uses an LQFP package with exposed pad to reduce the thermal resistance. Utilizing the exposed
pad is strongly recommended.
Table 8
Changed/Removed Functionality
Pin
89
TC1167 & TC1767
V DDP
TC1782N & TC1782F
V DD
91
V DD
V DDP
146
151
152
175
176
LTCA2 Input 1
GPTA0 Output 66
GPTA0 Output 67
GPTA0 Output 70
GPTA0 Output 71
MSC0 Serial Data Input 1
FlexRay (TC1782F only)
FlexRay (TC1782F only)
MSC0 Clock Output Positive C
MSC0 Serial Data Output Positive C
Table 9
Added Functionality
Pin
1...8
9, 13...16, 19
86, 87
149, 150
Application Note
TC1167 & TC1767
timed IO
timed IO
timed IO
timed IO
TC1782N & TC1782F
additional SSC2
additional FlexRay (TC1782F only)
additional CAN
additional FlexRay (TC1782F only)
20
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO FUTURE to AUDO MAX
3.4.3
Features, Peripherals & Software Compatibility
For the TC1782 the same tool chains can be used as for the TC1167, namely since the core revision and the
memory configuration remains the same.
The maximum clock rate of the PCP has been increased from 133MHz to 180MHz. For PCP frequencies
exceeding 90MHz, 2:1 mode vs. the FPI bus has to be enabled.
The TC1782 provides 40KB scratch pad RAM instead of 24KB and significantly more SRAM for data – 128KB
vs. 72KB.
In addition both the SRAM in DMI and PMI can be ECC protected.
The PCP has access to 32KB of code memory and 16KB of parameter memory.
Following is a description of the more important changes in the peripherals.
The TC1782 can use a peripheral clock of 90MHz instead of 80MHz, allowing several peripherals like CAN,
ASC, SSC, MSC, MLI to achieve higher data rates.
The TC1782 includes four high-speed synchronous serial interfaces (SSC) instead of two.
The TC1782F incorporates an E-Ray IP-module with two channels performing communication according to the
FlexRay™ 1) protocol specification v2.1.
The MultiCAN module implemented provides three independent CAN nodes instead of two with a maximum of
128 message objects.
The maximum ADC clock has been increased from 10MHz to 18MHz.
The FADC can make use of the increase peripheral clock of 90MHz instead of 80MHz in order to achieve
shorter conversion cycles.
Application Note
21
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO FUTURE to AUDO MAX
3.5
TC1197 / TC1797 vs. TC1793N / TC1793F
3.5.1
Feature Comparison
Core
Flash
SRAM
PCP
DMA
ADC
Timer
Interfaces
Package
Temperature (ambient)
Application Note
TC Version
Frequency (max.)
Program Flash
Data Flash
 (w/o PCP, Cache)
PMI
DMI
Overlay
Frequency (max.)
Code Memory
Parameter Memory
Channels
 Analog Inputs
ADC Modules / Channels
FADC Channels
 Timed IO (max.)
GPTA
LTCA / cells
GPT12
CCU6
FlexRay
CAN nodes / objects
SSC / ASC
MLI / MSC
EBU
TC1197 & TC1797
1.3.1
180 MHz
2.0 MB / 4.0 MB
64 KB
176 KB
TC1793N & TC1793F
1.6
270 MHz
4.0 MB
192 KB
288 KB
40 KB
128 KB
8 KB
180 MHz
32 KB
16KB
16
44
3 x 16
4
112
48 KB
144 KB
8 KB
200 MHz
32 KB
16KB
24
44
3 x 16
4
112
2
1 / 32
1 (TC1797 only)
2 / 128
2 /2
2 /2
1
BGA-416
-40 °C ... +125 °C
2
1 / 64
2
2
1 (TC1793F only)
4 / 128
4 /2
2 /2
1
BGA-416
-40 °C ... +125 °C
22
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO FUTURE to AUDO MAX
3.5.2
Design Compatibility
The TC1793 has been designed to be 100% pin compatible to the TC1797.
(Care must be taken regarding the configuration of the port pins since the TC1793 provides improved/additional
peripheral modules.)
The only major difference is the core voltage which has been reduced from 1.5V to 1.3V. In most cases this
could be solved by using a different fixed voltage variant of the respective power supply (e.g. changing from
TLE 7368E to TLE 7368-3E) or by changing the setting of the output voltage in case of an adjustable regulator.
While the typical values of the supply currents are in the same region as with the TC1797 care must be taken if
the TC1793 is run at frequencies above 200MHz. Here the core supply currents can be significantly higher.
3.5.3
Features, Peripherals & Software Compatibility
The most significant change is the new core revision of the TC1793: TC 1.6 vs. TC1.3.1. Together with the
change of the core bus (LMB) to a cross bar (SRI) this results in significant improvements in performance.
The latest revisions of the TriCore tool chains support this new core revision, older tool chains can still be used
as the new core revision is binary backwards compatible. Code compiled for TC1.3.1 can be run on the TC1.6
without modification.
The maximum clock rate of the PCP has been slightly increased from 180MHz to 200MHz. There are only a
limited number of clock ratios between CPU, PCP, Flash and the busse s allowed. Please refer to the respective
chapter in the user’s manual.
The TC1793 provides bigger caches as well as an additional block of 128KB of local SRAM for data or code.
The size of the data flash has been increased from 64KB to 192KB.
All memories including flash and SRAM can be ECC secured and the memory protection has been further
improved implementing 16 data and 8 code ranges.
The number of DMA channels has been increased to 24.
The external bus unit (EBU) provides an improved feature set namely in terms of the memory types supported,
e.g. support for SDRAM and DDRAM. The internal connection to the SRI cross bar allow for significantly higher
data rates to the external memories or peripherals.
The TC1793 integrates several measures targeted at safety and security applications. These measures e.g.
include a safe DMA controller (SDMA), a bus monitor unit (BMU), a memory checker module, a Flexible CRC
Engine (FCE) and a secure hardware extension (SHE).
The FCE is meant to be used as a hardware acceleration engine for software applications or operating systems
services using CRC signatures.
Application Note
23
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO FUTURE to AUDO MAX
Following is a description of the more important changes in the peripherals.
In principle the TC1793 can use a peripheral clock of 100MHz instead of 90MHz, for faster data transfers and
peripheral clocks. Due to the integer ratios of the clocks this would only be possible if the core is run at 200MHz
(or in case of the 200MHz device). In the configuration with the core at 270MHz the peripheral bus runs at
90MHz.
The TC1793 includes four high-speed synchronous serial interfaces (SSC) instead of two. The data
transmission over these interfaces can be assured by using the four new SSC guardian modules. These SSCG
monitor the data on both the internal bus as well as the actual pin therefore securing the integrity of the data
transmitted.
The TC1793F incorporates an E-Ray IP-module with two channels performing communication according to the
FlexRay™ 1) protocol specification v2.1.
The MultiCAN module implemented provides four independent CAN nodes instead of two.
The TC1793 provides an interface for ‘Single Edge Nibble Transmission (SENT)’ which is used to connect
sensors mainly in the automotive application area.
The number of local timer cells in the LTCA has been increased to 64 as it was in the TC1796.
The TC1793 incorporate several additional timer units: two Capture Compare Units CCU6 and two general
purpose timer units (GPT12).
The CCU6 provide two independent timers (T12, T13), which can be used for PWM generation, especially for
AC-motor control or power conversion stages. Additionally special control modes for block commutation and
multi-phase machines are supported.
The GPT12E unit represents a very flexible multifunctional timer/counter structure which may be used for many
different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse
generation, or pulse multiplication. Its functionality includes enhanced incremental interface modes and clock
prescaler support.
The maximum ADC clock has been increased from 10MHz to 18MHz (20MHz for theADC2).
All ADC input channels now include broken wire detection.
The FADC can achieve a slightly shorter conversion time if the increased peripheral clock of 100MHz is used.
Application Note
24
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO MAX
4
AUDO MAX
4.1
Placement options
The devices of the AUDO MAX family are offered with several memory sizes and clock frequencies to allow
scalability on the system level.
In addition there are two possibilities for PCB placement options providing even higher scalability:
Table 10
Placement options
PG-LQFP-176
PG-LFBGA-292 / -516
4.2
TC1728
TC1791
TC1782
TC1798
TC1728  TC1782
As described above the TC1728 and TC1782 are both compatible with the TC1767 from the AUDO FUTURE
generation. Consequently it is also possible to design a PCB board which can accommodate both devices.
The most important point to take into account is the fact that the TC1782 has significantly more supply pins
compared to the TC1728. On the TC1728 these pins are used for the ports P8, P9 and P10 and alternate
functions.
The supply pins which on the TC1728 provide the input voltage for the EVR are ground on the TC1782. In a
combined layout it is recommended to leave these pins unconnected.
The analog inputs AN16...31 are overlaid with port P11 on the TC1728 providing additional IO.
Due to the differences in a number of peripheral modules it is impractical to list all pins with different
functionality. Therefore the table below only lists pins which changed from being power supply to IO.
Table 11
Changed Functionality from power supply to IO
Pin
84, 91, 99, 123, 170
TC1728N
IO (P8.7, P8.10, P1.4, P8.4, P9.4) &
peripherals
11, 83, 89, 100, 124, IO (P9.7, P8.6, P8.9, P8.12, P8.3, P8.2,
139, 171
P9.3) & peripherals
107
V 5 (EVR supply)
TC1782N & TC1782F
V DD
22, 70, 155
V 5 (EVR supply)
V SS
12, 82, 85, 92, 125,
140, 172
23, 24, 25, 26
IO (P9.8, P8.5, P8.8, P8.11, P8.13, P8.1,
P9.2) & peripherals
IO (P10.0..10.3) & SSC
V SS
27
V PDG (EVR pass gate)
V FAGND
32...48
141
IO (P11.x) & AN31...16
IO (P8.0) & peripherals
AN31...16
V DDFL3
Application Note
25
V DDP
IO (P1.4)
V DDAF , V DDMF , VSSMF , V FAREF
V1.0, 2011-10
AP32187
Migration guide for TriCore™ based Microcontrollers
AUDO MAX
4.3
TC1791  TC1798
The high end members of the AUDO MAX family have been designed with special focus on compatibility and
scalability. While the TC1793 is pin compatible to the TC1797 from the AUDO FUTURE family, the TC1791 and
TC1798 provide the scalability within the family.
The inner ball rings of the TC1798 are fully compatible both in terms electrical parameters as well as
functionalities to the TC1791, so a design created for the TC1798 can also accommodate the TC1791. Software
written in a modular way can exploit this as well.
The additional balls of the TC1798 provide the following additional functionality:
Table 12
TC1798 additional IO capabilities
Functionality
EBU
P11,12, 15, 16, 18
Px
ADC3
FADC
Figure 2
Description
external bus unit for memories & peripherals
additional IO ports
additional IO pins in the available ports
additional fourth ADC with 16 inputs
4 dedicated FADC inputs
AUDO MAX high end scalability
Application Note
26
V1.0, 2011-10
www. i nf i n eo n. c om
Published by Infineon Technologies AG