[AKD4117-B] AKD4117-B AK4117 Evaluation Board Rev.1 GENERAL DESCRIPTION AKD4117-B is the evaluation board for AK4117, 192kHz digital audio receiver. This board has BNC connector to interface with other digital audio equipment. Ordering guide AKD4117-B --- Evaluation board for AK4117 (Control software is included in this package.) FUNCTION Digital interface -S/PDIF : 1 input (BNC) - Serial audio data I/F : 1 output (for DIR data output. 10-pin port) -U bit : -Serial control data I/F 1 input/output port (10-pin port) 5V GND REG Control 3.3V BNC RX0 AK4117 RX1 Serial Data out (From DIR) Figure 1. AKD4117-B Block Diagram <KM077202> 2015/11 -1- [AKD4117-B] Evaluation Board Manual Operating sequence (1) Set up the power supply lines. [+ 5V] (Red) = 5V [GND] (Black) = 0V (2) Set up the evaluation mode and jumper pins. (Refer to the following item.) (3) Connect cables. (Refer to the following item.) (4) Power on. The AK4117 should be reset once bringing PDN(SW2) “L” upon power-up. Evaluation modes (1) Evaluation for DIR BNC connector S/PDIF AK4117 (DIR) MCLK BICK LRCK SDTO PORT2 (10pin Header) MCLK BICK LRCK SDTO DAC AKD4117-B The DIR generates MCLK, BICK, LRCK and SDATA from the received data through BNC connector . The AKD4117-B can be connected with the AKM’s DAC evaluation board via 10-line cable. a. Set-up of Bi-phase Input RX0 and RX1 should not select BNC at the same time. a-1. Set-up of evaluation board Input JP RX0 JP2 (BNC) RX1 Short Short JP4 Table 1. Set-up of RX0 and RX1 a-2. Set-up of AK4117 input path IPS bit Input data 0 RX0 1 RX1 Default Table 2. Recovery Data Select <KM077202> 2015/11 -2- [AKD4117-B] b. Set-up of clock input and output SDTO DAUX NC GND BICK LRCK GND 10 GND 1 GND PORT2 DIR MCLK The signal level outputted/inputted from PORT2 is 3.3V. 5 6 Figure 2. PORT2 pin layout b-1. MCKO1/MCKO2 The AK4117 has a master clock output pin, MCKO. In PLL mode, PCKS1-0 bits select the MCKO frequency as shown in Table 3. When MCKO=512fs, MCKO goes to “L” when fs=96kHz and 192kHz. When MCKO=256fs, MCKO goes to “L” when fs=192kHz. When LP bit is set to “1”, the AK4117 is in low power mode (default). In low power mode, PLL lock range is up to 48kHz and the MCKO frequency is fixed to 256fs. In the X’tal mode, XCKS1-0 bits select the ratio of the X’tal frequency to fs (sampling frequency). The DIV bit selects the ratio (x1 or x1/2) of the MCKO frequency to the X’tal frequency (Table 4). LP 0 1 PCKS1 0 0 1 1 x PCKS0 0 1 0 1 x MCKO 512fs 256fs 128fs N/A 256fs fs [kHz] 32 48 32 96 32 192 N/A 32 48 Default Table 3. Master Clock Frequency Select (PLL mode: Clock operation mode 0, 2(UNLCK=0)) XCKS1 XCKS0 X’tal or EXT 0 0 1 1 0 1 0 1 128fs 256fs 512fs 1024fs MCKO DIV=0 128fs 256fs 512fs 1024fs DIV=1 64fs 128fs 256fs 512fs fs [kHz] EXTCLK [MHz] X’tal [MHz] 2.048 4.096 8.192 11.2896 12.288 24.576 16 32 64 88.2 96 192 8 16 32 44.1 48 96 N/A 8 16 N/A N/A 48 N/A N/A 8 N/A N/A N/A Default Table 4. Master Clock Frequency Select (X’tal mode: Clock operation mode 1, 2(UNLCK=1), 3) <KM077202> 2015/11 -3- [AKD4117-B] c. Set-up of Audio format Please set up DIF2-0 bit. Mode 0 1 2 3 4 5 6 7 DIF2 bit 0 0 0 0 1 1 1 1 DIF1 bit 0 0 1 1 0 0 1 1 DIF0 bit 0 1 0 1 0 1 0 1 DAUX SDTO 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S LRCK I/O H/L O H/L O H/L O H/L O H/L O L/H O Default Reserved Table 5. Audio format d. Set-up of CM1 and CM0 The operation mode of PLL is selected by CM1 and CM0. It can be selected by CM1-0 bits. CM1 bit CM0 bit (UNLOCK) PLL 0 0 - ON 0 1 - OFF 1 0 0 1 1 1 - X'tal ON Clock source SDTO source PLL(RX) RX ON X'tal DAUX ON ON PLL(RX) RX ON ON X'tal DAUX ON ON X'tal DAUX (Note 1) Default ON: Oscillation (Power-up), OFF: STOP (Power-Down) Note 1. When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF. Table 6. Clock Operation Mode Select <KM077202> 2015/11 -4- [AKD4117-B] ■ U output U(user data) can be monitored by TP1: U. ■ Serial control GND GND CCLK CSN GND GND CDTI 1 CDTO 2 NC PORT6 uP I/F GND The AK4117 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT6 (uP-I/F) with PC by 10-line flat cable packed with the AKD4117-B. Take care of the direction of connector. There is a mark at pin#1. The pin layout of PORT6 is as Figure 3. 10 9 Figure 3. PORT6 pin layout This evaluation board encloses control software. A software operation procedure is included in an evaluation board manual. <KM077202> 2015/11 -5- [AKD4117-B] Toggle switch set-up SW2 Reset switch for AK4117. Set to “H” during normal operation. Bring to “L” once after the power is supplied. PDN LED indication LE1 LE2 Bright when INT0 pin goes to “H”. Bright when INT1 pin goes to “H”. INT0 INT1 Set-up of XTL1 and XTL0 SW3_6 XTL1 0 0 1 1 SW3_5 X’tal Frequency XTL0 X’tal #1 0 11.2896MHz 1 12.288MHz 0 24.576MHz 1 (Use channel status) Table 7. Reference X’tal frequency Default Jumper set up. No. Jumper Name 2 RX0 4 RX1 Function Set-up of RX0 input circuit. BNC : BNC (default) Set-up of RX1 input circuit. <KM077202> 2015/11 -6- [AKD4117-B] Control Soft Manual ■ Evaluation Board and Control Soft Settings 1.Set an evaluation board properly. 2.Connect the evaluation board to an IBM PC/AT compatible PC by a 10wire flat cable. Be aware of the direction of the 10pin header. 3.Start up the control program following the process above. 4.The operation screen is shown below. Figure 4. Window of Control Soft <KM077202> 2015/11 -7- [AKD4117-B] ■ Operation Overview Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs. Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching tab window. Refer to the “■ Dialog Boxes” for details of each dialog box setting. 1.[ Port Reset ] : For when connecting to USB I/F board (AKDUSBIF-B) Click this button after the control soft starts up when connecting USB I/F board (AKDUSBIF-B). 2.[ Write Default ] : Register Initializing When the device is reset by a hardware reset, use this button to initialize the registers. 3.[ All Write ] : Executing write commands for all registers displayed. 4.[ All Read ] : Executing read commands for all registers displayed. 5.[ Save ] : Saving current register settings to a file. 6.[ Load ] : Executing data write from a saved file. 7.[ All Req Write ] : “All Req Write” dialog box is popped up. 8.[ Data R/W ] : “Data R/W” dialog box is popped up. 9.[ Sequence ] : “Sequence” dialog box is popped up. 10.[ Sequence(File) ] : “Sequence(File)” dialog box is popped up. 11.[ Read ] : Reading current register settings and display on to the Register area (on the right of the main window). This is different from [All Read] button, it does not reflect to a register map, only displaying hexadecimal. <KM077202> 2015/11 -8- [AKD4117-B] ■ Tab Functions 1. [REG]: Register Map This tab is for a register writing and reading. Each bit on the register map is a push-button switch. Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red). Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray) Grayout registers are Read Only registers. They can not be controlled. The registers which is not defined in the datasheet are indicated as “---”. Figure 5. Window of [ REG] <KM077202> 2015/11 -9- [AKD4117-B] [Write]: Data Writing Dialog It is for when changing two or more bits on the same address at the same time. Click [Write] button located on the right of the each corresponded address for a pop-up dialog box. When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”. Click [OK] to write setting value to the registers, or click [Cancel] to cancel this setting. Figure 6. Window of [ Register Set ] [Read]: Data Read Click [Read] button located on the right of the each corresponded address to execute register reading. After register reading, the display will be updated regarding to the register status. Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red). Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray) Please be aware that button statuses will be changed by Read command. <KM077202> 2015/11 - 10 - [AKD4117-B] ■ Dialog Boxes 1. [All Req Write]: All Req Write dialog box Click [All Reg Write] button in the main window to open register setting files. Register setting files saved by [SAVE] button can be applied. Figure 7. Window of [ All Reg Write ] [Open (left)] [Write] [Write All] : Selecting a register setting file (*.akr). : Executing register writing. : Executing all register writings. Writings are executed in descending order. [Help] : Help window is popped up. [Save] : Saving the register setting file assignment. The file name is “*.mar”. [Open (right)] : Opening a saved register setting file assignment “*. mar”. [Close] : Closing the dialog box and finish the process. ～ Operating Suggestions ～ (1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be stored in the same folder. (2) When register settings are changed by [Save] button in the main window, re-read the file to reflect new register settings. <KM077202> 2015/11 - 11 - [AKD4117-B] 2. [Data R/W]: Data R/W Dialog Box Click the [Data R/W] button in the main window for data read/write dialog box. Data write is available to specified address. Figure 8. Window of [ Data R/W ] [ Address ] Box [ Data ] Box [ Mask ] Box [ Write ] [ Read ] [ Close ] : Input data address in hexadecimal numbers for data writing. : Input data in hexadecimal numbers. : Input mask data in hexadecimal numbers. This is “AND” processed input data. : Writing to the address specified by “Address” box.(Note 2) : Reading from the address specified by “Address” box.(Note 2) The result will be shown in the Read Data Box in hexadecimal numbers. : Closing the dialog box and finish the process. Data writing can be cancelled by this button instead of [Write] button. Note 2. The register map will be updated after executing [Write] or [Read] commands. <KM077202> 2015/11 - 12 - [AKD4117-B] 3. [Sequence]: Sequence Dialog Box Click [Sequence] button to open register sequence setting dialog box. Register sequence can be set in this dialog box. Figure 9. Window of [Sequence ] ～ Sequence Setting ～ Set register sequence by following process bellow. (1)Select a command Use [Select] pull-down box to choose commands. Corresponding boxes will be valid. < Select Pull-down menu > · No_use : Not using this address · Register : Register writing · Reg(Mask) : Register writing (Masked) · Interval : Taking an interval · Stop : Pausing the sequence · End : Finishing the sequence <KM077202> 2015/11 - 13 - [AKD4117-B] (2)Input sequence [ Address ] : Data address [ Data ] : Writing data [ Mask ] : Mask [Data] box data is ANDed with [Mask] box data. This is the actual writing data. When Mask = 0x00, current setting is hold. When Mask = 0xFF, the 8bit data which is set in the [Data] box is written. When Mask =0x0F, lower 4bit data which is set in the [Data] box is written. Upper 4bit is hold to current setting. [ Interval ] : Interval time Valid boxes for each process command are shown bellow. · No_use · Register · Reg(Mask) · Interval · Stop · End : None : [Address], [Data], [Interval] : [Address], [Data], [Mask], [Interval] : [Interval] : None : None Control Buttons The function of Control Button is shown bellow. [Start] [Help] [Save] [Open] [Close] : Executing the sequence : Opening a help window : Saving sequence settings as a file. The file name is “*.aks”. : Opening a sequence setting file “*.aks”. : Closing the dialog box and finish the process. Stop of the sequence When “Stop” is selected in the sequence, processing is paused and it starts again when [Start] button is clicked. Restarting step number is shown in the “Start Step” box. When finishing the process until the end of sequence, “Start Step” will return to “1”. The sequence can be started from any step by writing the step number to the “Start Step” box. Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning. <KM077202> 2015/11 - 14 - [AKD4117-B] 4. [Sequence(File)]: Sequence Setting File Dialog Box Click [Sequence(File)] button to open sequence setting file dialog box. Those files saved in the “Sequence setting dialog” can be applied in this dialog. Figure 10. Window of [ Sequence(File) ] [Open (left)] [Start] [Start All] : Opening a sequence setting file (*.aks). : Executing the sequence setting. : Executing all sequence settings. Sequences are executed in descending order. [Help] [Save] [Open(right)] [Close] : Pop up the help window. : Saving sequence setting file assignment. The file name is “*.mas”. : Opening a saved sequence setting file assignment “*. mas”. : Closing the dialog box and finish the process. ～ Operating Suggestions ～ (1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should be stored in the same folder. (2) When “Stop” is selected in the sequence the process will be paused and a pop-up message will appear. Click “OK” to continue the process. Figure 11. Window of [ Sequence Pause ] <KM077202> 2015/11 - 15 - [AKD4117-B] Revision History Date (YY/MM/DD) 04/12/21 Manual Revision KM077200 Board Revision 0 Reason Page First edition - 10/12/21 KM077201 0 Change 15/11/12 KM077202 1 Change Contents 7-15 “Control Soft Manual” was changed. 19 <KM077202> Circuit diagram was changed. PORT1: “Mount” -> “No Mount” 2015/11 - 16 - [AKD4117-B] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. 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This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. <KM077202> 2015/11 - 17 - 5 4 3 2 1 33 34 35 INT0 36 INT1 37 CDTO 38 CDTI 39 CCLK 40 CSN 41 42 43 44 45 46 47 48 CN5 D D CN6 CN7 32 49 31 U7 50 R61 30 1 51 C19 10u AVSS 24 13k 29 C20 0.1u + 52 AVDD R 2 AVDD PDN RX1 INT0 23 PDN 28 C 3 53 22 C 27 4 54 NC INT1 RX0 CSN 21 26 5 55 20 25 56 RX0 6 R62 1k C21 RX1 JP19 JMP CCLK DVSS CDTI 19 24 C22 0.1u 7 18 23 C23 8 2 58 + 10u 57 DVDD 5p CDTO XTO UOUT 17 X1 11.2896MHz 1 C24 59 XTI 22 9 16 5p B 21 10 60 LRCK NC 15 B 20 11 61 BICK MCKO SDTO DAUX 14 U 12 62 19 13 18 63 AK4117 17 64 LRCK A 16 SDTO 15 14 BICK 13 12 11 10 MCKO 9 8 7 DVDD 6 5 PDN 4 3 2 1 DAUX PDN A Title AKD4117 CN8 - 18- Size A3 Date: 5 4 3 2 Document Number Rev SUB Tuesday, September 29, 2015 1 Sheet 1 1 of 1 5 4 3 2 1 CN4 PORT1 6 D3V 5 5 L1 4 3 2 1 GND VCC GND OUT 1 C7 (NM) C2 C3 C4 C5 0.1u0.1u0.1u 0.1u 0.1u 1 6 For U3, U4 D3V 0.1u C6 49 10u 2 VD 50 C8 + 2 For U1, U2, U5 D3V R1 10u 51 JP2 OPT XLR BNC 470 D 1 3 5 2 4 6 AVDD AVDD 52 D 53 54 +5V T2 R4 1 OUT C11 47u IN 55 3 VD RX0 short 57 J2 2 3 4 5 T3 1 OUT + 3 C14 47u C13 RX1 1 R5 0.1u 75 1 2 2 + IN RX0 58 JP4 1 2 59 1 2 short GND R6 DVDD 56 2 + 2 short 1 AVDD GND R3 60 C15 47u 61 62 R8 C C D3V 63 short 64 CN1 1 2 3 PDN 5 D3V 15 1 12 100 R11 100 R12 K 14 1 A 9 EMCK2 H DAUX2 6 7 R10 DAUX2 DAUX 8 100 C16 SW 2 PDN 3 L U2B 74HC14 4 7 4Y 7 3 3Y DVDD B U2A 74HC14 2 14 16 D3V 2Y 8 G A/B 1Y DVDD D3V 10k D1 7 100 R83 10k D3V 4 1 EMCK1 1A 1B 2A 2B 3A 3B 4A 4B 9 0.1u MCKO1 2 R82 2 3 5 6 11 10 14 13 R9 GND U1 B 4 10 74LVC157 11 12 D3V 1 2 3 4 5 MCLK BICK LRCK SDTO DAUX 100 100 100 100 DIR U3 18 17 16 15 14 13 12 11 B0 B1 B2 B3 B4 B5 B6 B7 GND A R15 R16 R18 R20 R13 13 20 PORT2 10 9 8 7 6 D3V/VD GND GND GND GND GND 100 A0 A1 A2 A3 A4 A5 A6 A7 DIR OE 2 3 4 5 6 7 8 9 1 19 47k 47k 47k 47k 47k 47k R76 R77 R78 R79 R80 R81 100 R17 BICK 100 100 R19 R21 SDTO LRCK 14 15 A 16 10 74AC245 Title - 19- Size A3 Date: 5 4 3 2 AKD4117-B Document Number Rev MAIN Tuesday, September 29, 2015 1 Sheet 1 1 of 2 5 4 3 2 1 CN2 GND +5V T45_BK T45_BK 17 18 1 1 TP1 U U 19 +5V 20 D D 21 22 23 24 25 26 27 28 29 30 C C 31 14 32 LE1 A CN3 U2C R45 K 6 33 5 1k INT0 34 14 7 74HC14 LE2 A D3V INT0 U2D 8 INT1 9 R49 470 10k R52 470 R54 10k R55 470 14 U2E 11 10 PORT6 10 8 6 4 2 14 7 74HC14 U2F 9 7 5 3 1 CSN R56 SCL/CCLK SDA/CDTI 51 SDA(ACK)/CDTO 15 1 12 1A 1B 2A 2B 3A 3B 4A 4B G A/B 1Y 2Y 3Y 4Y 8 13 2 3 5 6 11 10 14 13 CM0/CDTO/CAD1 D3V 10k R51 VD B U5 R48 7 74HC14 4 7 36 37 R50 CM1/CDTI/SDA 100 R53 38 B 100 9 OCKS1/CCLK/SCL 39 12 OCKS0/CSN/CAD0 GND 1k 16 D3V INT1 35 R47 K 40 41 74LVC157 uP-I/F 42 7 74HC14 R58 R59 D3V R60 43 100 10k 44 100 45 46 47 A A 48 Title - 20- Size A3 Date: 5 4 3 2 AKD4117-B Document Number Rev MAIN Tuesday, September 29, 2015 1 Sheet 1 2 of 2 - 21- - 22- - 23- - 24- - 25- - 26- - 27- - 28-