AK7742EQ

[AKD7742-B]
AKD7742-B
AK7742 Evaluation Board Rev.1
GENERAL DESCRIPTION
The AKD7742-B is an evaluation board for AK7742, which is a highly integrated audio processor including
a stereo ADC with 6ch input selector, two stereo DAC and an audio DSP. This board is composed of a
main board and a sub board. It is possible to control the setting of board via USB port. RCA connector is
used for the input and output of analog signal. This board also has digital interface and can achieve the
interface with digital audio system via optical connector.
„ Ordering guide
AKD7742-B
---
Evaluation board for AK7742
Control software is packed with this.
FUNCTION
† Read/Write access to PRAM, CRAM, OFFRAM and registers of AK7742
† Compatible with 2 types of digital audio interface
- Optical input (x1) / Optical output (x1)
- 10pin header for interface with external data source (x2)
† ADC 6ch input (differential input 2ch, single-end input 4ch), DAC 4ch output
† USB port for board control
+12V
Regulator
Regulator
USB 3.3V
-12V GND
Regulator
3.3V
3.3V
PIC4550
USB
Amp
FPGA
Opt In
AOUT 4ch
AK7742
(XC95144)
AIN 6ch
AK4114
Amp
Opt Out
SMUX
SMUX2
10 Pin Header
(Note) AK4114 has DIR, DIT and X’tal oscillator.
Figure 1. AKD7742-B Block Diagram
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Evaluation Board Diagram
„ Board Diagram
+12V
JP5
SMUX2
(JP16)
JP2
SMUX
(JP15)
CLKO
(JP6B)
JP3
JP13
Clock
(JP4B)
GND
FPGA
AK7742
JP14
JTAG
(JP17)
USB Port
PIC
4550
-12V
SW1
AKD7742-B sub-board
JP9
JP10
AK
4114
JP1
SPD IF-OUT
(PORT2)
SPDIF-IN
(PORT1)
AKD7742-B Rev.1
AOUT2
AOUT1
AIN(D)
AIN(S)
Figure 2. AKD7742-B Board Diagram
„ Description
(1) AIN/DAC
RCA Jack. The white jacks are used for left channel and the red ones are for right channel. AIN(D) is for differential
input and AIN(S) is for single-end input. AOUT1/AOUT2 is used for DAC1/ DAC2.
(2) AK4114
AK4114 has DIR, DIT and X’tal oscillator. It transports digital data to AK7742 when working in master mode and
outputs data from AK7742 when working in slave mode.
(3) SPDIF-IN
Optical input connector. It supports sampling frequencies from 32Hz to 96kHz for input. It is used as digital data
source for AK7742.
(4) SPDIF-OUT
Optical output connector. It outputs the data from whichever among SDOUT1~3.
(5) Power supply
Connect to +12V, GND and -12V. Current of about 250mA is consumed when normal operation.
(6) PIC4550
USB control chip. It is possible to set up the registers of AK7742, FPGA and AK4114 from PC via USB port.
(7) SW1
Push type button. It is used to initialize the PIC4550. When connecting the board to PC, it is required to push down
the button for initialization.
(8) FPGA
FPGA used for data path control. It is possible to run a variety of tests by way of controlling the data path via control
software.
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(9) Clock （jumper）
The jumper is used to select clock source between [EXT] and [XTL] to change the clock mode of AK7742. The
setting of other jumper pins is according to Table 1 and Table 2.
(10) SMUX port
10 pin header for interface with external data source. Two ports are equipped and available to achieve with other
audio system.
Pin I/O Function
pin
I/O Function
1
I
MCLK
2
P
GND
3
I
BITCLK
4
P
GND
5
I
LRCLK
6
(NC)
7
I
DI
8
(NC)
9
P
VDD
10
O
DO
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Evaluation Board Manual
„ Operation sequence
(1) Set up the power supply lines.
Name Color
Voltage
+12V
Red
+9～+12V
-12V
Blue
-9～-12V
GND
Black
0V
Comment
Regulator,
Power supply for op-amp
Power supply for op-amp
Ground
Attention
This jack is always needed.
Power line
This jack is always needed.
Power line
This jack is always needed.
Each supply line should be distributed from the power supply unit. The power of AK7742 and peripheral device is
supplied by two 12V=>3.3V regulators equipped on the board.
(2) Set up the evaluation mode, jumper pins and connectors. ( according to the follows )
(3) Connect the board to PC with the USB cable packed.
It is required to push down the button(SW1) to initialize the USB control chip.
(4) Power On
(5) Start the control soft and setup the register
„ Evaluation Mode
(1) Evaluation mode of ADC using DIT of AK4114 in Master Mode
PORT2(optical output connector) is used. Port1(optical input connector) should be open. Set the clock mode of
AK7742 to Master Mode (12.288MHz). AK7742 supplies MCLK, BICK, LRCK to AK4114 and AK4114
outputs the data from SDOUT1.
[The jumper pins should be set as following]
JP1
AK4114 Clock
XTL
EXT
JP4B
AK7742 Clock
XTL
JP6B
CLKO
EXT
(Note) The jumpers of number with B are located at sub board.
1. Connection of connector
For analog differential input, RCA1(L)/RCA2(R) are available.
For analog single-end input, RCA3(L)/RCA4(R) are available.
For digital output, optical connector PORT2 (SPDIF-OUT) is available.
2. Setting of jumper pins for analog input (JP9, JP10)
Set the jumper pins according to Table 3 when using analog single-end input.
3. Set up the FPGA and AK7742 control register via PC.
(2) Evaluation mode of DAC using DIR of AK4114 in Slave Mode
PORT1 (optical input connector) is used. Set the clock mode of AK7742 to Slave Mode(12.288MHz). AK4114
supplies MCLK, BICK, LRCK and digital data to AK7742.
[The jumper pins should be set as following]
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JP4B
AK7742 Clock
XTL
EXT
1. Connection of connector
For digital input, optical connector PORT1 (SPDIF-IN) is available.
For analog output, RCA5(DAC1L)/RCA6(DAC1R） or RCA8(DAC2L)/RCA8(DAC2R) are available.
2. Set up the FPGA and AK7742 control register via PC.
(3) Evaluation mode of internal loopback in Master Mode
（Analog input → ADC → DSP → DAC → Analog output）
Leave the PORT1, PORT2 open and set the clock mode of AK7742 to Master Mode (12.288MHz).
[The jumper pins should be set as following]
JP4B
AK7742 Clock
XTL
JP6B
CLKO
EXT
1. Connection of connector
For analog differential input, RCA1(L)/RCA2(R) are available.
For analog single-end input, RCA3(L)/RCA4(R) are available.
For analog output, RCA5(DAC1L)/RCA6(DAC1R） or RCA8(DAC2L)/RCA8(DAC2R) are available.
2. Setting of jumper pins for analog input (JP9, JP10)
Set the jumper pins according to Table 3 when using analog single-end input.
3. Set up the FPGA and AK7742 control register via PC.
„ Board control
It is possible to control AKD7742-B via general USB port. Connect the USB port on board to PC with the packed
cable.
Control software is packed with this board. The software operation sequence is included in the evaluation board
manual.
„ Indication for LED
[LED]: U11
When power is supplied, LED is lighted to red. Monitor the PC-SCL clock signal and change the
color when the board is communicating with PC.
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„ Setting of Jumper Pins
(main board)
Jumper
JP01 (AK4114 Clock)
JP02 (CHIP-GND)
JP03 (AVDD)
JP05 (DVDD)
JP09 (AINL)
JP10 (AINR)
JP13 (USB DVDD)
JP14 (P DVDD)
Setting (Default)
Note
AK4114 Clock Source
“XTL”: Crystal Clock
“EXT”: External Clock
Short
AK7742 GND
Short
AK7742 AVDD
Short
AK7742 DVDD
“AIN2L”: Analog Input AIN2L
“AIN2L”
“AIN3L”: Analog Input AIN3L
“AIN2R”: Analog Input AIN2R
“AIN2R”
“AIN3R”: Analog Input AIN3R
USB chip power supply
“USB-5V”: USB 5V
“DVDD”
“USB-3.3V”: USB 3.3V
“DVDD”: Peripheral DVDD 3.3V
Short
Peripheral DVDD
Table 1. Setting of jumper pins on main board
“XTL”
(sub board)
Jumper
JP4B (Clock)
JP6B (CLKO)
Setting (Default)
Note
AK7742 Clock Source
“XTL”: Crystal Clock
“EXT”: External Clock
Short
Short: MCLK output
Table 2. Setting of jumper pins on sub board
“EXT”
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„ Analog Input Circuit
Figure 3. Analog Differential Input Circuit
For analog differential input, RCA1(AIN(D)L)/RCA2(AIN(D)R) are available.
The input range of each channel is ±[email protected].
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Figure 4. Analog Single-end Input Circuit
For analog single-end input, RCA3(AIN(S)L)/ RCA4(AIN(S)R) are available.
The input range of AIN is [email protected].
Setting of jumper pins of analog single-end input circuit
JP09, JP10 1-2 pin JP09, JP10 3-4 pin
Input Pin
AINL2/ AINR2
Open
Short
AINL3/ AINR3
Short
Open
Table 3. Setting of single-end input
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„ Analog Output Circuit
Figure 5. DAC1 Analog Output Circuit
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Figure 6. DAC2 Analog Output Circuit
For analog output, RCA5(DAC1L)/RCA6(DAC1R) and RCA8(DAC2L)/RCA7(DAC2R) are available.
The analog output circuit supports single-ended mode and the output range(AOUTP-AOUTN) is [email protected].
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„ Digital Input Circuit (External DIR:PORT1)
Figure 7. Digital Input Circuit (AK4114)
For digital input SPDIF-IN, optical connector PORT1 is available.
„ Digital Output Circuit (External DIT:PORT2)
Figure 8. Digital output circuit (AK4114)
For digital output SPDIF-OUT, optical connector PORT2 is available.
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[AKD7742-B]
Control Software Manual
„ Set-up of the evaluation board and control software
(1) Set up the AKD7742-B according to previous term.
(2) Connect AKD7742-B to PC with the cable packed Push down the reset button(SW1) to initialize the USB chip.
(3) Insert the CD-ROM labeled “AKD7742-B Evaluation Kit” into the CD-ROM drive.
(4) Access the CD-ROM drive and double-click the icon of “AK7742b.exe” to set up the program.
(5) Then please evaluate according to the follows.
„ Operation flow
Keep the following flow
1. Set up the control program according to the explanation above.
2. Click “Board Init” button to initialize the board.
3. Select the needed dialogue to evaluate by changing the setting.
If the USB cable is removed when control software is used, please close the software and set up it again when operation
is needed again.
Figure 9. The image of control software
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Control software is possible to execute program downloading, to set up the registers, to set up the FPGA and to process
script file. They can be selected by the tab items above. The buttons of control signals which are frequently used and the
initialization buttons are placed outside the tab dialogue.
[INIT_RESET]:
[S_RESET]:
[DSP]:
[ADC]:
[DAC2]:
[DAC1]:
[CK]:
[I2CSEL]
[Board Init]:
[READ]:
Initial Reset. It is used to initialize the AK7742.
System Reset. DSP/ADC/DAC will be set to reset mode but the register will not be initialized.
DSP Reset.
ADC Reset.
DAC2 Reset.
DAC1 Reset.
Clock Reset. Clock Reset is required when changing the clock mode or the frequency of input clock
without initial reset. The register will not be initialized.
Selector for 3-wire serial control mode or I2C control mode. I2C control mode is selected when the
button is pushed down and 3-wire serial mode is selected when button is released.
The setting of registers of AK7742, FPGA and AK4114 is written to board together.
Read back CONT register or TEST register decided by [Read Select] button and show the result on
register column.
(1) Download
Figure 10. [Download] Dialogue
File of Source column, Program column, CRAM column or OFFSET column can be selected by clicking the [refer]
button of each column or by way of dropping or tracking files from desktop.
CRAM file or OFFSET file can be selected and be written to CRAM or OFF-RAM by clicking the [refer] button of
CRAM write@operation column or OFF-RAM write@operation column when system is running. The data will be
written to specific address of CRAM or OFF-RAM when the [write] button at right side is clicked.
[Assemble]:
Compile the source file and the output file will be selected to the download file automatically.
[Write]:
Download the program to AK7742.
[Assemble Write]: Compile the source file and then download the file to AK7742.
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[PRAM read]:
[CRAM read]:
[Offset read]:
[CRAM SAVE]:
[Offset SAVE]:
[MICR1]:
[MICR2]:
[JX]:
Read the data of PRAM to temporary file.
Read the data of CRAM to temporary file.
Read the data of OFF-RAM to temporary file.
Read the data of CRAM and save to file.
Read the data of OFF-RAM and save to file.
Read the data of register MICR1 when program is running and show the result to dialogue.
Read the data of register MICR2 when program is running and show the result to dialogue.
JX code setting column.
(2) Register Set up
Figure 11. [REG1] Dialogue
Tab Dialogues of REG1/REG2 are used to regulate the registers’ setting. (It is prohibited to process test and reserved
items.)
As the checkbox is clicked, the data is written to the register after system reset.
The reference pages of registers in datasheet are as following:
Register
Reference Page
Register
Reference Page
Register
CONT00
21
CONT04
25
CONT08
CONT01
22
CONT05
26
CONT10-11
CONT02
23
CONT06
27
CONT12-15
CONT03
24
CONT07
28
Table 4. Reference page of registers
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Reference Page
28
29
29
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(3) FPGA Set up
Figure 12. [FPGA1] Dialogue
The dialogue is used to regulate the data path and the setting of AK4114 via FPGA.
FPGA Set up (It is prohibited to process test and reserved items.)
FPGA Set up
SDOUT
SDIN2/JX0
SDIN1/JX1
Description
Output data source for AK4114
0 : SDOUT1
1 : SDOUT2/SO/RDY/GPO
2 : SDOUT3
3 : Low
Input data source to SDIN2/JX0 pin of AK7742
0 : AK4114 IN
1 : SMUX1_DAT1
2 : SMUX2_DAT1
3 : Low
4 : Low
5 : High
6 : Low
7 : Low
Input data source to SDIN1/JX1 pin of AK7742
0 : AK4114 IN
1 : SMUX1_DAT1
2 : SMUX2_DAT1
3 : Low
4 : Low
5 : High
6 : Low
7 : Low
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CKM[2:0]
CAD[1:0]
MASTER
TRXPDN
SMUX2_DAT2
SMUX1_DAT2
AK4114 Setup
MCLK
CM
DIF
Clock mode of AK7742
0 : MASTER 12.288MHz
1 : MASTER 18.432MHz
2 : SLAVE 12.288MHz
3 : SLAVE 64fs ( fs = 48kHz )
4 : SLAVE 32fs ( fs = 8kHz )
5 : SLAVE 64fs ( fs = 8kHz )
L/H set up of CAD1, CAD0 pin used by I2C mode
1 : Low, Low
1 : Low, High
2 : High, Low
3 : High, High
Master device selector (This item should be changed together with CKM mode)
0: AK4114
1: AK7742
2: SMUX1
3: SMUX2
Power Switch of AK4114
0 : Low ( OFF )
1 : High ( ON )
Output data source for DAT2 pin of port SMUX2
0 : SDOUT1
1 : SDOUT2/SO/RDY/GPO
2 : SDOUT3
3 : Low
Output data source for DAT2 pin of port SMUX1
0 : SDOUT1
1 : SDOUT2/SO/RDY/GPO
2 : SDOUT3
3 : Low
Table 5. FPGA Set up
Description
Frequency of main clock output from AK4114
0 : 265fs
1 : 256fs
2 : 512fs
3 : 128fs
Master clock operation mode of AK4114
0 : CM = 00
1 : CM = 01
2 : CM = 10
3 : CM = 11
Format setup of AK4114 I/O
0 : 16bit Right ( O )
1 : 18bit Right ( O )
2 : 20bit Right ( O )
3 : 24bit Right ( O )
4 : 24bit Left ( O )
5 : 24bit I2S ( O )
6 : 24bit Left ( I )
7 : 24bit I2S ( I )
Table 6. AK4114 Set up
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(4) Script
Figure 13. [SCRIPT] Dialogue
As the script file is selected, it is executed directly. If [Repeat] button is clicked, the selected script file will be executed
once again.
The script commands are listed as follow.
Command
[SCRIPT]
;Comment
W,<address>,<data>
W,0xC0,0x00
WL,<command>,<address>,<data>,…
WL,0x82,0x0022,0x4000,0x4000,0x4000,
D,<address>,<data>
X,<address>,<data>
P,<message>
RI: H / RI:L
RA:H / RA:L
RD:H / RD:L
R2:H / R2:L
T,<wait>
T,50mS
LP:<filename>
LC:<filename>
LO:<filename>
Description
Header of script file. The script file will be compiled to error without this header.
The content after semicolon is ignored as comment.
Write data to register. Both address and data must be BYTE(8bit).
Write data continuously. It can be used when CRAM is running. The command
must be BYTE(8bit) and the data below must be WORD(16bit).
Write data to AK4114.
Write data to the register of FPGA.
Show message and pause the processing of script.
Init reset.
ADC reset.
DSP reset.
Select for I2C bus mode
Wait some milliseconds.
When actual operation, it is possible to wait longer than this.
Download program file to DSP.
Download CRAM file to DSP.
Download OFRAM file to DSP.
Table 7. Script Command
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Measurement Results
[Measurement condition]
・ Measurement unit
・ MCKI
・ BICK
・ fs
・ Bit
・ Measurement Mode
・ Power Supply
・ Input Frequency
・ Measurement Frequency
・ Temperature
: Audio Precision, System two Cascade
: 256fs (12.288MHz)
: 64fs
: 48kHz
: 24bit
: Slave Mode, CKM Mode 2
: +12V, -12V, GND
: 1kHz
: 20 ~ 20kHz
: Room
[Measurement Results]
1. ADC
Result
ADC: AIN(D) => ADC
S/(N+D) (-1dBFS)
DR
(-60dBFS, A-Weighted)
S/N
(A-weighted)
Lch
Rch
91.4
96.4
96.5
91.8
96.5
96.6
Unit
dB
dB
dB
2. DAC1
Result
DAC1: SDIN1 => DAC1 => AOUT1
S/(N+D) (0dBFS)
DR
(-60dBFS, A-Weighted)
S/N
(A-weighted)
Lch
Rch
92.6
106.7
107.1
92.9
106.4
106.8
Unit
dB
dB
dB
3. DAC2
Result
DAC2: SDIN2 => DAC2 => AOUT2
S/(N+D) (0dBFS)
DR
(-60dBFS, A-Weighted)
S/N
(A-weighted)
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Lch
Rch
92.3
106.6
106.8
92.4
106.7
107.1
Unit
dB
dB
dB
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[Plot Data]
1. ADC ( AIN(D) => ADC )
AKM
A K 7 7 4 2 A I N (D ) = > A D C
[F F T , f s = 4 8 k H z , f in = 1 k H z , I n p u tL e v e l= -1 d B F S ]
+0
-1 0
-2 0
-3 0
-4 0
-5 0
-6 0
d
B
F
S
-7 0
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 3 0
-1 4 0
-1 5 0
-1 6 0
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 14. FFT ( 1kHz, -1dBFS )
AKM
A K 7 7 4 2 A I N (D ) = > A D C
[F F T , f s = 4 8 k H z , f in = 1 k H z , I n p u tL e v e l= -6 0 d B F S ]
+0
-1 0
-2 0
-3 0
-4 0
-5 0
-6 0
d
B
F
S
-7 0
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 3 0
-1 4 0
-1 5 0
-1 6 0
20
50
100
200
500
1k
2k
5k
Hz
Figure 15. FFT ( 1kHz, -60dBFS )
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AKM
A K 7 7 4 2 A I N (D ) = > A D C
[F F T , f s = 4 8 k H z , f in = 1 k H z , N o S ig n a l]
+0
-1 0
-2 0
-3 0
-4 0
-5 0
-6 0
d
B
F
S
-7 0
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 3 0
-1 4 0
-1 5 0
-1 6 0
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 16. FFT ( No Signal )
AKM
A K 7 7 4 2 A I N (D ) = > A D C
[T H D + N vs I n p u tL e ve l, f s = 4 8 kH z, f in = 1 kH z]
-6 0
-6 5
-7 0
-7 5
-8 0
-8 5
d
B
F
S
-9 0
-9 5
-1 0 0
-1 0 5
-1 1 0
-1 1 5
-1 2 0
-1 2 0
-1 0 0
-8 0
-6 0
-4 0
-2 0
+0
dB r
Figure 17. THD+N vs. Input Level
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AKM
A K 7 7 4 2 A I N (D ) = > A D C
[T H D + N vs F re q u e n c y , f s = 4 8 kH z , I n p u tL e ve l= -1 d B F S ]
-6 0
-6 5
-7 0
-7 5
-8 0
-8 5
d
B
F
S
-9 0
-9 5
-1 0 0
-1 0 5
-1 1 0
-1 1 5
-1 2 0
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 18. THD+N vs. Frequency
AKM
A K 7 7 4 2 A I N (D ) = > A D C
[L in e a rity, f s = 4 8 kH z, f in = 1 kH z]
+0
TTT T
T
-1 0
-2 0
-3 0
-4 0
-5 0
d
B
F
S
-6 0
-7 0
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 2 0
-1 0 0
-8 0
-6 0
-4 0
-2 0
+0
dB r
Figure 19. Linearity
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AKM
A K 7 7 4 2 A I N (D ) = > A D C
[F re q u e n c y R e s p o n s e , f s = 4 8 k H z , I n p u tL e v e l= -1 d B F S ]
+0
-0 . 2
-0 . 4
-0 . 6
-0 . 8
d
B
F
S
-1
-1 . 2
-1 . 4
-1 . 6
-1 . 8
-2
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 20. Frequency Response
AKM
A K 7 7 4 2 A I N (D ) = > A D C
[C ro s s ta lk , f s = 4 8 kH z , I n p u tL e v e l= -1 d B F S , R e d = L c h , B lu e = R c h ]
-6 0
TT
TT
TT
T
TT
TT
TT
TT
TT
T
T
T
T
T
-6 5
-7 0
-7 5
-8 0
-8 5
-9 0
-9 5
d
B
-1 0 0
-1 0 5
-1 1 0
-1 1 5
-1 2 0
-1 2 5
-1 3 0
-1 3 5
-1 4 0
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 21. Crosstalk
<KM093201>
2008/09
- 22 -
[AKD7742-B]
2. DAC1 ( SDIN1 => DAC1 => AOUT1 )
AKM
A K 7 7 4 2 S D IN1 => D A C 1
[F F T , f s = 4 8 k H z , f in = 1 k H z , I n p u tL e v e l= 0 d B F S ]
+0
-1 0
-2 0
-3 0
-4 0
-5 0
-6 0
d
B
r
A
-7 0
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 3 0
-1 4 0
-1 5 0
-1 6 0
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 22. FFT ( 1kHz, 0dBFS )
AKM
A K 7 7 4 2 S D IN1 => D A C 1
[F F T , f s = 4 8 k H z , f in = 1 k H z , I n p u tL e v e l= -6 0 d B F S ]
+0
-1 0
-2 0
-3 0
-4 0
-5 0
-6 0
d
B
r
A
-7 0
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 3 0
-1 4 0
-1 5 0
-1 6 0
20
50
100
200
500
1k
2k
5k
Hz
Figure 23. FFT ( 1kHz, -60dBFS )
<KM093201>
2008/09
- 23 -
[AKD7742-B]
AKM
A K 7 7 4 2 S D IN1 => D A C 1
[F F T , f s = 4 8 k H z , f in = 1 k H z , N o S ig n a l]
+0
-1 0
-2 0
-3 0
-4 0
-5 0
-6 0
d
B
r
A
-7 0
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 3 0
-1 4 0
-1 5 0
-1 6 0
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 24. FFT ( No Signal )
AKM
A K 7 7 4 2 S D IN1 => D A C 1
[T H D + N vs I n p u tL e ve l, f s = 4 8 kH z, f in = 1 kH z]
-6 0
-6 5
-7 0
-7 5
-8 0
d
B
r
A
-8 5
-9 0
-9 5
-1 0 0
-1 0 5
-1 1 0
-1 1 5
-1 2 0
-1 2 0
-1 0 0
-8 0
-6 0
-4 0
-2 0
+0
dB FS
Figure 25. THD+N vs. Input Level
<KM093201>
2008/09
- 24 -
[AKD7742-B]
AKM
A K 7 7 4 2 S D IN1 => D A C 1
[T H D + N v s F re q u e n c y, f s = 4 8 kH z , I n p u tL e ve l= 0 d B F S ]
-6 0
-6 5
-7 0
-7 5
-8 0
d
B
r
A
-8 5
-9 0
-9 5
-1 0 0
-1 0 5
-1 1 0
-1 1 5
-1 2 0
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 26. THD+N vs. Frequency
AKM
A K 7 7 4 2 S D IN1 => D A C 1
[L in e a rity, f s = 4 8 kH z, f in = 1 kH z]
+0
-1 0
-2 0
-3 0
-4 0
d
B
r
A
-5 0
-6 0
-7 0
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 2 0
-1 0 0
-8 0
-6 0
-4 0
-2 0
+0
dB FS
Figure 27. Linearity
<KM093201>
2008/09
- 25 -
[AKD7742-B]
AKM
A K 7 7 4 2 S D IN1 => D A C 1
[F re q u e n c y R e s p o n s e , f s = 4 8 k H z, I n p u tL e v e l= 0 d B F S ]
+1
+ 0.8
+ 0.6
+ 0.4
+ 0.2
d
B
r
+0
A
-0 . 2
-0 . 4
-0 . 6
-0 . 8
-1
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 28. Frequency Response
AKM
A K 7 7 4 2 S D IN1 => D A C 1
[C ro s s ta lk, f s = 4 8 k H z, I n p u tL e v e l= 0 d B F S , R e d = L c h , B lu e = R c h ]
-6 0
-6 5
-7 0
-7 5
-8 0
-8 5
-9 0
-9 5
d
B
-1 0 0
-1 0 5
-1 1 0
-1 1 5
-1 2 0
-1 2 5
-1 3 0
-1 3 5
-1 4 0
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 29. Crosstalk
<KM093201>
2008/09
- 26 -
[AKD7742-B]
3. DAC2 ( SDIN2 => DAC2 => AOUT2 )
AKM
A K 7 7 4 2 S D IN2 => D A C 2
[F F T , f s = 4 8 k H z , f in = 1 k H z , I n p u tL e v e l= 0 d B F S ]
+0
-1 0
-2 0
-3 0
-4 0
-5 0
-6 0
d
B
r
A
-7 0
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 3 0
-1 4 0
-1 5 0
-1 6 0
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 30. FFT ( 1kHz, 0dBFS )
AKM
A K 7 7 4 2 S D IN2 => D A C 2
[F F T , f s = 4 8 k H z , f in = 1 k H z , I n p u tL e v e l= -6 0 d B F S ]
+0
-1 0
-2 0
-3 0
-4 0
-5 0
-6 0
d
B
r
A
-7 0
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 3 0
-1 4 0
-1 5 0
-1 6 0
20
50
100
200
500
1k
2k
5k
Hz
Figure 31. FFT ( 1kHz, -60dBFS )
<KM093201>
2008/09
- 27 -
[AKD7742-B]
AKM
A K 7 7 4 2 S D IN2 => D A C 2
[F F T , f s = 4 8 k H z , f in = 1 k H z , N o S ig n a l]
+0
-1 0
-2 0
-3 0
-4 0
-5 0
-6 0
d
B
r
A
-7 0
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 3 0
-1 4 0
-1 5 0
-1 6 0
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 32. FFT ( No Signal )
AKM
A K 7 7 4 2 S D IN2 => D A C 2
[T H D + N vs I n p u tL e ve l, f s = 4 8 kH z, f in = 1 kH z]
-6 0
-6 5
-7 0
-7 5
-8 0
d
B
r
A
-8 5
-9 0
-9 5
-1 0 0
-1 0 5
-1 1 0
-1 1 5
-1 2 0
-1 2 0
-1 0 0
-8 0
-6 0
-4 0
-2 0
+0
dB FS
Figure 33. THD+N vs. Input Level
<KM093201>
2008/09
- 28 -
[AKD7742-B]
AKM
A K 7 7 4 2 S D IN2 => D A C 2
[T H D + N v s F re q u e n c y, f s = 4 8 kH z , I n p u tL e ve l= 0 d B F S ]
-6 0
-6 5
-7 0
-7 5
-8 0
d
B
r
A
-8 5
-9 0
-9 5
-1 0 0
-1 0 5
-1 1 0
-1 1 5
-1 2 0
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 34. THD+N vs. Frequency
AKM
A K 7 7 4 2 S D IN2 => D A C 2
[L in e a rity, f s = 4 8 kH z, f in = 1 kH z]
+0
-1 0
-2 0
-3 0
-4 0
d
B
r
A
-5 0
-6 0
-7 0
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 2 0
-1 0 0
-8 0
-6 0
-4 0
-2 0
+0
dB FS
Figure 35. Linearity
<KM093201>
2008/09
- 29 -
[AKD7742-B]
AKM
A K 7 7 4 2 S D IN2 => D A C 2
[F re q u e n c y R e s p o n s e , f s = 4 8 k H z, I n p u tL e v e l= 0 d B F S ]
+1
+ 0.8
+ 0.6
+ 0.4
+ 0.2
d
B
r
+0
A
-0 . 2
-0 . 4
-0 . 6
-0 . 8
-1
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 36. Frequency Response
AKM
A K 7 7 4 2 S D IN2 => D A C 2
[C ro s s ta lk, f s = 4 8 k H z, I n p u tL e ve l= 0 d B F S , R e d = L c h , B lu e = R c h ]
-6 0
-6 5
-7 0
-7 5
-8 0
-8 5
-9 0
-9 5
d
B
-1 0 0
-1 0 5
-1 1 0
-1 1 5
-1 2 0
-1 2 5
-1 3 0
-1 3 5
-1 4 0
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 37. Crosstalk
<KM093201>
2008/09
- 30 -
[AKD7742-B]
REVISION HISTORY
Date
(yy/mm/dd)
08/03/26
Manual
Revision
KM093200
Board
Revision
0
Reason
First edition
08/09/01
KM093201
1
Correction
5
Change
12
Change
Page
Contents
Jumper Setting of evaluation mode 2 was corrected.
The name of control software was updated.
AK7742.exe => AK7742b.exe
12-17 The figures 9-13 of control software were updated.
Change
13
Change
14
The names of reset buttons were updated.
The description of [DSP] button was added.
Table 4 was updated.
Change
18
Measure Results were updated for Rev.B device.
Change
Change
19-30 PLOT data was updated
40
Circuit diagram of sub-board was changed.
C21, C22, C23, C24 => Not Connected.
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
<KM093201>
2008/09
- 31 -
5
4
3
2
XILINX
1
AK7742
SDIN1/JX1
SDIN2/JX0
D
SDOUT1
SO/RDY/GPO/SDOUT2
CLKO/SDOUT3
LRCLK
BITCLK
EXT
SDIN1/JX1
SDIN2/JX0
SDOUT1
SO/RDY/GPO/SDOUT2
CLKO/SDOUT3
LRCLK
BITCLK
EXT
ANALOG OUT
SDIN1/JX1
SDIN2/JX0
D
SDOUT1
SO/RDY/GPO/SDOUT2
CLKO/SDOUT3
AOUT1LP
AOUT1LN
AOUT1RP
AOUT1RN
AOUT2LP
AOUT2LN
AOUT2RP
AOUT2RN
LRCLK
BITCLK
AOUT1LP
AOUT1LN
AOUT1RP
AOUT1RN
AOUT1LP
AOUT1LN
AOUT1RP
AOUT1RN
AOUT2LP
AOUT2LN
AOUT2RP
AOUT2RN
AOUT2LP
AOUT2LN
AOUT2RP
AOUT2RN
EXT
AK4114
TRX-PDN
RX-CLK
RX-CLK2
RX-DAT
TRX-PDN
RX-CLK
RX-CLK2
RX-DAT
TRX-PDN
CKM[2]
CKM[1]
CKM[0]
RX-CLK
RX-CLK2
RX-DAT
TESTI
C
POWER
TRX-LRCK
TRX-BICK
TX-CLK
TX-DAT
TRX-LRCK
TRX-BICK
TX-CLK
TX-DAT
TESTI
CKM[2]
CKM[1]
CKM[0]
ANALOG OUT
TESTI
C
ANALOG IN
TRX-LRCK
TRX-BICK
TX-CLK
TX-DAT
X-I2CSEL
X-INITRSTN
X-I2CSEL
X-INITRSTN
AIN1LP
AIN1LN
AIN1RP
AIN1RN
X-I2CSEL
X-INITRSTN
AIN2L
AIN2R
PC-SCLK
PC-SI
CS3-N
POWER
CKM[2]
CKM[1]
CKM[0]
RQ-N/CAD1
SI/CAD0
SCLK/SCL
RQ-N/CAD1
SI/CAD0
SCLK/SCI
RQ-N/CAD1
SI/CAD0
SCLK/SCL
AIN3L
AIN3R
AIN1LP
AIN1LN
AIN1RP
AIN1RN
AIN1LP
AIN1LN
AIN1RP
AIN1RN
AIN2L
AIN2R
AIN2L
AIN2R
AIN3L
AIN3R
AIN3L
AIN3R
SDA
PC-SCL
PC-SO
LEN-IND
PC-INITRSTN
PC-I2CSEL
PC_SCLK
PC-SI
PC-RQN
PC-CS2N
PC-CS3N
PC-CS4N
AK4114
PC I/F
B
B
AK7742
XILINX
ANALOG IN
PC-SCLK
PC-SI
PC-RQN
PC-CS2N
PC-CS3N
PC-CS4N
PC-SCLK
PC-SI
PC-RQN
PC-CS2N
PC-CS3N
PC-CS4N
PC-INITRSTN
PC-I2CSEL
PC-INITRSTN
PC-I2CSEL
PC-SO
LED-IND
PC-SO
LED-IND
PC-SCL
PC-SDA
PC-SCL
PC-SDA
PC I/F
A
A
Title
<TOP>
Size
A3
Date:
5
4
3
2
Document Number
<Doc>
Monday, January 07, 2008
Rev
<RevCode>
Sheet
1
1
of
8
5
4
3
2
1
D
D
DVDD-3.3V
DVDD-3.3V
C1
+
SILK-SCREEN
SPDIN-IN
C2
L1
10uF
10uH
0.1uF
PORT1
SPDIF-IN
VCC
GND
OUT
3
2
1
R2
470
C3
R1
DIF-RX
0.1uF
18k
TORX141
SILK-SCREEN
1: XTL
3: EXT
SPDI/F Optical in
DVDD-3.3V
SILK-SCREEN
SPDIN-OUT
RX4
NC1
RX5
TEST2
RX6
NC3
RX7
IIC
P/SN
XTL0
XTL1
VIN
AK4114
13
14
15
16
17
18
19
20
21
22
23
24
L2
default 1-2 short
36
35
34
33
32
31
30
29
28
27
26
25
INT0
CSN
CCLK
CDTI
CDTO
PDN
XTI
XTO
DAUX
MCKO2
BICK
SDTO
TRX-PDN
TX-CLK
R3
R4
R5
100
100
100
TX-DAT
RX-CLK2
TRX-BICK
RX-DAT
XTAL1
22pF
C6
22pF
C7
AK4114
10uH
IN
VCC
GND
CS3-N
PC-SCLK
PC-SI
12.288MHz
PORT2
SPDIF-OUT
C
1
2
3
1
2
3
4
5
6
7
8
9
10
11
12
TVDD
NC4
TX0
TX1
BOUT
COUT
UOUT
VOUT
DVDD
DVSS
MCKO1
LRCK
C
JP1
HEADER 3
RX3
NC6
RX2
TEST1
RX1
NC5
RX0
AVSS
VCOM
R
AVDD
INT1
U1
48
47
46
45
44
43
42
41
40
39
38
37
C5
10uF
+
C4
0.1uF
R6
100
R7
100
TRX-LRCK
RX-CLK
DIF-TX
3
2
1
C8
0.1uF
0.1uF C9
C12
10uF
10uF
TOTX141
C11
10uF
+
SPDI/F Optical out
C10
0.1uF
DVDD-3.3V
SILK-SCREEN
DVSS
DVSS
C13
B
+
+
B
DVDD-3.3V
DVDD-3.3V
1
TP1
TP(BLACK)
+
C14
100uF/16V(A)
A
A
Title
<AK4114>
Size
A3
Date:
5
4
3
2
Document Number
<Doc>
Monday, November 05, 2007
Rev
<RevCode>
Sheet
1
2
of
8
5
4
3
2
SILK-SCREEN
CHIP-GND
2PIN: [->]
SILK-SCREEN
CHIP-AVDD
2PIN: [->]
JP2
HEADER 2
JP3
HEADER 2
D
2
1
default short
1
2
default short
1
C15
10uF(A)
D
AVDD
+
JP4
1
3
5
7
9
11
13
15
17
19
DVDD
SILK-SCREEN
CHIP-DVDD
2PIN: [->]
2
4
6
8
10
12
14
16
18
20
AIN1RN
AIN1RP
AIN1LN
AIN1LP
AIN3R
AIN3L
AIN2R
AIN2L
HEADER 10X2
JP5
HEADER 2
1
2
default short
CHIP-DVDD
CHIP-AVDD
+ C16
10uF(A)
+
C
C
HEADER 10X2
JP6
1
3
5
7
9
11
13
15
17
19
C17
10uF(A)
2
4
6
8
10
12
14
16
18
20
TESTI
CKM[2]
EXT
SDOUT1
SDIN1/JX1
SDIN2/JX0
CKM[1]
CKM[0]
20
18
16
14
12
10
8
6
4
2
AOUT1LP
AOUT1LN
AOUT1RP
AOUT1RN
AOUT2LP
AOUT2LN
AOUT2RP
AOUT2RN
HEADER 10X2
19
17
15
13
11
9
7
5
3
1
JP7
CHIP-GND
+
C18
10uF(A)
JP8
B
1
3
5
7
9
11
13
15
17
19
21
23
B
2
4
6
8
10
12
14
16
18
20
22
24
X-INITRSTN
X-I2CSEL
LRCLK
BITCLK
CLKO/SDOUT3
SO/RDY/GPO/SDOUT2
SDA
SCLK/SCL
SI/CAD0
RQ-N/CAD1
HEADER 12X2
CHIP-GND
A
A
Title
<AK7742>
Size
A3
Date:
5
4
3
2
Document Number
<Doc>
Monday, November 05, 2007
Rev
<RevCode>
Sheet
1
3
of
8
5
4
3
2
1
AREA : SHORTEST WIRING
AMP-PWAMP-PW-
RCA: WHITE
RCA: RED
22uF(A)
C26
RCA2
T
B
S
C27
68pF
22uF(A)
T
B
S
C28
68pF
R12
10k
R13
10k
AIN1RN
22uF(A)
C29
68pF
22uF(A)
C30
68pF
MR-552LS(R)
7
+
+
8
4
3
6
AIN1RP
8
22uF(A)
8
+
C32
7
5
22uF(A)
C33
0.1uF
U3B
NJM5532D
8
AIN1LP
R15
10k
1
+
5
SILK-SCREEN
AIN(D)R
U3A
NJM5532D
4
4
4
-
3
6
2
C31
-
1
AIN(D)-Rch
U2B
NJM5532D
+
R14
10k
+
SILK-SCREEN
AIN(D)L
U2A
NJM5532D
+
2
-
AIN(D)-Lch
-
MR-552LS(W)
R11
10k
+
R10
10k
+
R9
10k
C24
C23
10uF
+
R8
10k
C22
0.1uF
AIN1LN
+
C25
RCA1
D
C21
C20
10uF
+
C19
0.1uF
+
D
C34
10uF
C35
0.1uF
+
C36
10uF
AMP-PW+
AMP-PW+
C
TP2
TP(BLACK)
TP3
TP(BLACK)
1
SILK-SCREEN
AVSS
1
SILK-SCREEN
AVSS
C
AMP-PW-
C38
10uF
R17
10k
+
4
+
22uF(A)
22uF(A)
8
MR-552LS(W)
JP9
1
3
2
4
AIN3L
AIN2L
SILK-SCREEN
AIN(S)L
4
R19
10k
6
U4B
NJM5532D
B
C44
JP10
7
22uF(A)
MR-552LS(R)
5
1
3
22uF(A)
AIN3R
AIN2R
2
4
HEADER 2X2
HEADER 2X2
default 3-4 pin short
default 3-4 pin short
AIN(S)-Lch
+
C43
1
3
T
B
S
8
+
2
C42
RCA4
U4A
NJM5532D
+
T
B
S
R18
10k
-
C41
RCA3
+
B
SILK-SCREEN
1: AIN3R
3: AIN2R
C39
68pF
SILK-SCREEN
1: AIN3L
3: AIN2L
C40
68pF
-
+
C37
0.1uF
R16
10k
C45
0.1uF
+
AIN(S)-Rch
C46
10uF
SILK-SCREEN
AIN(S)R
AMP-PW+
A
A
Title
<ANALOG IN>
Size
A3
Date:
5
4
3
2
Document Number
<Doc>
Monday, January 07, 2008
Rev
<RevCode>
Sheet
1
4
of
8
5
4
3
2
1
AREA : SHORTEST WIRING
AMP-PWC48
10uF
RCA: WHITE
RCA: RED
+
C47
0.1uF
D
D
R20
4.7k
R21
4.7k
AOUT1RN
4
R33
10k
8
R32
4.7k
C62
470pF(F)
C63
+
0.1uF
C60
33uF(A)
RCA5
T
B
S
+
+
1
3
R26
220
AOUT1RP
R30
3.6k
C58
R31
8.2nF(F) 180
6
R34
4.7k
C59
22uF(A)
7
5
MR-552LS(W)
U5B
NJM5532D
C61
470pF(F)
R27
220
+
2
C56
22uF(A)
+
C55
R29
8.2nF(F) 180
U5A
NJM5532D
RCA6
T
B
S
R35
10k
8
4
DAC1
-
AOUT1LP
R28
3.6k
C50
470pF(F)
C52
8.2nF(F)
C54
8.2nF(F)
C57
33uF(A)
R23
180
+
AOUT1LN
R22
3.6k
+
C49
33uF(A)
C53
470pF(F)
+
R25
180
+
R24
3.6k
-
C51
33uF(A)
MR-552LS(R)
SILK-SCREEN
DAC1R
SILK-SCREEN
DAC1L
C64
10uF
SILK-SCREEN
AVSS
C
AMP-PW+
C
TP4
TP(BLACK)
1
AMP-PWC66
10uF
+
C65
0.1uF
R36
4.7k
R37
4.7k
AOUT2RN
R49
4.7k
C79
470pF(F)
4
R50
10k
8
+
1
3
C81
+
0.1uF
C82
10uF
AMP-PW+
C78
33uF(A)
RCA8
T
B
S
AOUT2RP
R46
3.6k
C74
R47
8.2nF(F) 180
U6B
NJM5532D
C76
22uF(A)
7
5
R51
4.7k
MR-552LS(W)
6
C80
470pF(F)
R42
220
+
R45
220
+
2
C75
22uF(A)
+
AOUT2LP
C73
R44
8.2nF(F) 180
U6A
NJM5532D
R48
10k
8
4
DAC2
-
B
R43
3.6k
C70
470pF(F)
C72
8.2nF(F)
C71
8.2nF(F)
C77
33uF(A)
R41
180
+
AOUT2LN
R40
3.6k
+
C69
33uF(A)
C68
470pF(F)
+
R39
180
+
R38
3.6k
-
C67
33uF(A)
RCA7
T
B
S
B
MR-552LS(R)
SILK-SCREEN
DAC2R
SILK-SCREEN
DAC2L
SILK-SCREEN
AVSS
1
TP5
TP(BLACK)
A
A
Title
<ANALOG OUT>
Size
A3
Date:
5
4
3
2
Document Number
<Doc>
Monday, February 18, 2008
Rev
<RevCode>
Sheet
1
5
of
8
5
4
3
2
1
USB-VDD
R52 10k
D
D
+
C83
0.1uF
C84
0.1uF
C85
10uF
R54
10k
18
6
29
VSS1
JP11
MCLR_N/Vpp/RE3
12
13
33
34
NC/ICCK/ICPGC
NC/ICDT/ICPGD
NC/ICRST_N/ICVpp
NC/ICPORTS
30
31
OSC1/CLKI
OSC2/CLKO/RA6
25
26
27
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CPP2/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
1
2
3
4
5
17
16
15
14
11
10
9
8
SILK-SCREEN
1: VDD
2: MCLR
3: PGD
4: PGC
5: GND
SILK-SCREEN
1: USB-5V
3: USB-3.3V
JP13
HEADER 3X25: DVDD
1
3
5
USB-RST
VSS0
APE 1F
Up
:Release
Down :Push Down
VDD1
VDD0
SW1
7
U8
28
C86
0.1uF
100k
2
4
6
R53
default 3-4 pin short
HEADER 5
DVDD-3.3V
C87 22pF
SILK-SCREEN
SDA
C
DVDD-3.3V
TP6
TP(BLUE)
R56
C93
470nF
37
100
19
20
21
22
23
24
PC-SDA
PC-SCL
PC-SO
RD0/SPP0
RD1/SPP1
RD2/SPP2
RD3/SPP3
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
38
39
40
41
2
3
4
5
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RC2/CCP1/P1A
32
35
36
PC-CS3N
PC-INITRSTN
PC-CS4N
PC-I2CSEL
PC-SCLK
PC-SI
PC-RQN
PC-CS2N
REG1
LM1117-3.3V
1
+
VUSB
1
R55
4.7k
PIC18F4550
TQFP 44-PIN
RA0/AN0
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS_N/HLVDIN/C2OUT
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
C91
C89
10uF
0.1uF
IN
GND
C88 22pF
OUT
2
C
C90
3
XTI
XTO
Y1
20MHz
C92
+
0.1uF
10uF
U9
VUSB
DD+
GND
42
43
44
1
1
2
3
4
VUSB
DD+
GND
USB(B type)
PIC18F4550
B
B
SILK-SCREEN
DVSS
DVDD-3.3V
DVDD-3.3V
U10A
+
R57
C96
0.1uF
LED-IND
10k
DVDD-3.3V
U10B
VCC
CEXT
16
6
C94
33uF(A)
15
1
2
3
8
U11
REXT/CEXT
A
B
CLR
GND
13
Q
4
Q
R58
R59
100
100
1
3
7
GREEN
COM
2
9
10
11
8
RED
BICOLOR LED
74HC221
TP7
TP(BLACK)
C95
VCC
CEXT
+
100uF/16V(A)
1
16
14
REXT/CEXT
A
B
CLR
GND
74HC221
Q
5
Q
12
A
A
Title
<Title>
Size
A3
Date:
5
4
3
2
Document Number
<Doc>
Monday, February 18, 2008
Rev
<RevCode>
Sheet
1
6
of
8
5
4
3
2
1
D
D
AMP-PW+
DVDD
AVDD
2
C98
0.1uF
+ C101
10uF
OUT
C99
0.1uF
TM1
1
IN
1
C100
0.1uF
3
+ C97
10uF
LM1084-3.3V
GND
SILK-SCREEN
CHIP-GND
TP8
TP(BLACK)
REG2
L3
10uH
+ C102
10uF
+
i
RED(+12V)
TJ-563
C103
100uF/16V(A)
1
TM2
WIRE1
1
WIRE
WIRE SHORT
WIRE2
+
BLACK(GND)
C104
100uF/16V(A)
WIRE SHORT
TM3
1
WIRE
SILK-SCREEN
P-DVDD
2 PIN: [->]
C
i
TJ-563
i
BLUE(-12V)
TJ-563
AMP-PWC
DVDD-3.3V
JP14
HEADER 2
REG3
2
1
2
1
+ C105
10uF
C106
0.1uF
OUT
LM1084-3.3V
GND
default short
TP9
TP(BLACK)
3
SILK-SCREEN
DVSS
IN
1
C107
0.1uF
+ C108
10uF
B
B
A
A
Title
<Title>
Size
A3
Date:
5
4
3
2
Document Number
<Doc>
Monday, January 07, 2008
Rev
<RevCode>
Sheet
1
7
of
8
5
4
3
2
1
DVDD-3.3V
SMUX-DVDD
SMUX PORT
C109
0.1uF
+ C110
10uF
JP15
D
SMUX-MCLK
SMUX-BICK
SMUX-LRCK
SMUX-DAT1
1
3
5
7
9
D
2
4
6
8
10
SILK-SCREEN
SMUX PORT/SMUX PORT2
1: MCLK
3: BIT
5: LR
7: DI
10: DO
HEADER 5X2
SMUX-DAT2
SMUX PORT2
JP16
U12
SILK-SCREEN
TP10
SO
TP(BLUE)
R60
R61
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
24
25
28
29
30
32
33
34
35
36
37
39
40
41
42
43
46
49
50
100
100
1
C
PC-SO
R63
PC-SCL
100
PC-CS2N
PC-RQN
PC-SI
PC-I2CSEL
PC-CS4N
PC-INITRSTN
PC-CS3N
LEN-IND
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
I/O33
52
53
54
55
56
58
59
60
61
63
64
65
66
67
68
70
71
72
73
74
76
77
78
79
80
81
82
85
86
87
89
90
91
92
93
94
95
96
97
VINT0
VINT1
VINT2
5
57
98
VIO0
VIO1
VIO2
VIO3
26
38
51
88
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
21
31
44
62
69
75
84
100
1
3
5
7
9
2
4
6
8
10
HEADER 5X2
SILK-SCREEN
SCLK/SCL
SMUX2-DAT2
R62
X-INITRSTN
X-I2CSEL
LRCLK
BITCLK
CLKO/SDOUT3
SO/RDY/GPO/SDOUT2
100
TP11
TP(BLUE)
C
1
TRX-PDN
TX-CLK
TX-DAT
RX-CLK2
TRX-BICK
RX-DAT
TRX-LRCK
RX-CLK
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I/O64
I/O65
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
I/O72
SMUX2-MCLK
SMUX2-BICK
SMUX2-LRCK
SMUX2-DAT1
SCLK/SCL
SI/CAD0
RQ-N/CAD1
R64
R65
100
100
R66
100
CKM[0]
CKM[1]
SDIN2/JX0
SDIN1/JX1
SDOUT1
EXT
CKM[2]
TESTI
DVDD-3.3V
B
PC_SCLK
R67
99
2
1
4
3
27
23
22
100
GSR
GTS4
GTS3
GTS2
GTS1
GCK3
GCK2
GCK1
JP17
1
3
5
7
9
2
4
6
8
10
48
45
83
47
VDD-JTAG
TCK
TDI
TDO
TMS
C111
0.1uF
+ C114
10uF
C116
0.1uF
C117
0.1uF
C118
0.1uF
+ C119
10uF
SILK-SCREEN
DVSS
DVSS
TP12
TP(BLACK)
XC95144
WIRE
1
WIRE3
A
C113
0.1uF
C115
0.1uF
HEADER 5X2
C120
0.1uF
C112
0.1uF
B
WIRE SHORT
DVDD-3.3V
+ C121
100uF/16V(A)
A
DVDD-3.3V
Title
<Title>
Size
A3
Date:
5
4
3
2
Document Number
<Doc>
Monday, January 07, 2008
Rev
<RevCode>
Sheet
1
8
of
8
5
4
3
2
1
C1 100uF(A)
CHIP-AVDD
+
TP2
TP(BLUE)
JP1
D
CHIP-AVDD
2
4
6
8
10
12
14
16
18
20
SILK-SCREEN
VCOM
TP1
TP(BLACK)
C4
10uF
0.1uF
+ C5
C6
10uF
+ C7
0.1uF
10uF
CHIP-GND
(4,5) (4,5) (30,32) (30,32) (41,43) (41,43)
1
AIN1RN
AIN1RP
AIN1LN
AIN1LP
AIN3R
AIN3L
AIN2R
AIN2L
+ C3
0.1uF
1
1
3
5
7
9
11
13
15
17
19
C2
D
C12
2.2uF(DIP)
CHIP-DVDD
+
CHIP-GND
SILK-SCREEN
CHIP GND
C13 0.1uF(DIP)
C8
+ C10
C9
+ C11
HEADER 10X2
0.1uF
10uF
0.1uF
10uF
CHIP-GND
(9,10)(9,10)(20,21) (20,21)
R7
1.1k
R8
1.1k
C21
7
TESTI
8
CKM[2]
37
1.1k
R12
1.1k
100uF(A) C14
+
38
AOUT1RP
AOUT1RN
39
40
AVSS
AOUT1LN
VCOM
41
43
42
AVDD
VCOM
45
CHIP-GND
AVDD
32
AVDRV
31
AVSS
30
RQ_N/CAD1
29
28
R13
1.1k
DVDD
SI/CAD0
DVSS
SCLK/SCL
27
11
XTI
SDA
26
NC
R14
1.1k
HEADER 10X2
CHIP-AVDD
AOUT1LP
AOUT1LN
AOUT1RP
AOUT1RN
AOUT2LP
AOUT2LN
AOUT2RP
AOUT2RN
CHIP-AVDD
AVDRV
C17
20
18
16
14
12
10
8
6
4
2
1uF(DIP)
19
17
15
13
11
9
7
5
3
1
JP2
CHIP-GND
C
CHIP-GND
CLKO/SDOUT3
BITCLK
25
SILK-SCREEN
AVDRV
TP(BLUE)
TP4
R1 100
24
23
LRCLK
22
DVSS
DVDD
20
21
I2CSEL
INITRST_N
SO/RDY/GPO/SDOUT2
19
18
XTO
17
12
CKM[0]
1
9
10
Y1
B
22pF(DIP)
R3
100
CHIP-GND
C19
CHIP-DVDD
22pF(DIP)
AK7742
CKM[1]
12nF(DIP)
R2
0(DIP)
12.288MHz
44
LFLT
XTO
C18
AIN1RN
AVSS
6
AK7742
B
46
5
XTI
SILK-SCREEN
1: XTL
3: EXT
AIN1LN
33
CHIP-GND
SDIN2/JX0
3
2
1
34
AOUT2RP
16
JP4
HEADER 3
AOUT2LN
35
AOUT2RN
CHIP-GND
default 2-3 short
36
AVDD
CHIP-DVDD
HEADER 10X2
AOUT2LP
AIN2L
15
C16
R11
C24
4
CHIP-GND
1.1k
NC
3
SDIN1/JX1
TESTI
CKM[2]
EXT
SDOUT1
SDIN1/JX1
SDIN2/JX0
CKM[1]
CKM[0]
1.1k
R10
C23
CHIP-AVDD
TP(BLUE)
CHIP-DVDD
SDOUT1
2
4
6
8
10
12
14
16
18
20
1
1
3
5
7
9
11
13
15
17
19
AIN2R
14
JP3
CHIP-GND
NC
AIN3L
2
13
+
1
SILK-SCREEN
LFLT TP3
R9
C22
AOUT1LP
C15 100uF(A)
C
AIN1RP
48
AIN3R
AIN1LP
U1
47
CHIP-AVDD
NC
R4 R5 R6
100 100 100
SILK-SCREEN
CLKO
C20 100uF(A)
+
JP6
1
2
JP5
CHIP-GND
SILK-SCREEN
CHIP GND
TP5
TP(BLACK)
1
A
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
default short
HEADER 2
CHIP-DVDD
INITRST-N
I2CSEL
LRCLK
BITCLK
CLKO/SDOUT3
SO/RDY/GPO/SDOUT2
SDA
SCLK/SCL
SI/CAD0
RQ-N/CAD1
A
HEADER 12X2
Title
<AK7742-CHIP>
Size
A3
Date:
5
4
3
2
Document Number
<Doc>
Monday, September 01, 2008
Rev
<RevCode>
Sheet
1
1
of
1