AK7757VQ

[AKD7757-A]
AKD7757-A
AK7757 Evaluation Board Rev.0
GENERAL DESCRIPTION
The AKD7757-A is an evaluation board for AK7757, which is a highly integrated digital signal processor
with an integrated 4ch DAC, a stereo ADC with input selector, a mono ADC and an integrated digital audio
interface. This board is composed of a main board and a sub board. The AKD7757-A can be set-up by a
PC via USB port. RCA connector is used for both input and output of the analog signal. Digital audio
interfaces are also integrated, enabling to Interface with a digital audio system via optical connectors or
SMUX-PORTs.
„ Ordering Guide
AKD7757-A
---
Evaluation board for the AK7757
Control software is packed with the evaluation board.
FUNCTION
† Read/Write access to PRAM, CRAM, OFREG and registers of the AK7757
† Compatible with 2 types of digital audio interface
- Optical input (x1) / Optical output (x1)
- 10pin header for interface with external data source (x2)
† ADC1 6ch input (differential input 3ch, single-end input 3ch), ADC2 1ch input, DAC 4ch
output
† USB port for board control
+12V GND
Regulator
Regulator
USB 3.3V
Regulator
3.3V
3.3V
PIC18F4550
Amp
AOUT 4ch
Amp
AIN(D) 4ch
USB
FPGA
Opt In
AK7757
(XC95144XL)
AIN1(S) 2ch
AK4118A
AIN(S) 1ch
Opt Out
Amp
SMUX1
AINT(D) 1ch
SMUX2
10 Pin Header
(Note) AK4118A has DIR, DIT and X’tal oscillator.
Figure 1. AKD7757-A Block Diagram
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Evaluation Board Diagram
„ Board Diagram
Figure 2. AKD7757-A Board Diagram
„ Description
(1) AIN/DAC (RCA Jack)
AIN: Analog input jacks. DAC: Analog output jacks.
(2) AK4118A
AK4118A has DIR, DIT and X’tal oscillator. It transports digital data to AK7757 when working in master mode and
outputs data from AK7757 when working in slave mode.
(3) SPDIF-IN/SPDIF-OUT (Optical Connector)
SPDIF-IN (Input): Supports sampling frequencies from 8 to 48kHz. Optical digital signal input to the AK4118A.
SPDIF-OUT (Output): Supports sampling frequencies from 8 to 48kHz. Optical digital signal output from the
AK4118A.
(4) +12V/GND (Power supply)
Connect to +12V and GND according to the following operation sequence.
(5) PIC18F4550
USB control chip. Control registers of the AK7757, the XC95144XL and the AK4118A can be set by a PC via USB
port.
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(6) SW1
Toggle type switch. Use this switch to select the clock source between [TX-CLK] and [XTL] for changing the clock
mode of the AK4118A. Please refer to Table 3 and Table 4 about the setting of other jumper pins.
(7) SW2
Push type switch. Use this switch to initialize the PIC18F4550. When connecting the evaluation board to a PC, it is
required to initialize the PIC18F4550 once by pushing down this switch.
(8) XC95144XL(Xilinx)
FPGA for data path control. It is possible to run a variety of tests by way of controlling the data path via control
software.
(9) SMUX PORT (PORT1/PORT2)
10 pin header for interfacing with external data sources. The AKD7757-A has two SMUX ports, enabling to connect
other audio systems.
Pin
1
3
5
7
9
I/O
I
I
I
I
P
Function
pin
I/O Function
MCLK
2
P
GND
BITCLK
4
P
GND
LRCLK
6
P
GND
SDTI
8
P
GND
VDD
10
O
SDTO
Table 1. Pin Assignment of SMUX Port
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Evaluation Board Manual
„ Operation Sequence
(1) Set up the power supply lines.
Jumper Pin Setting
JP1
DVDD
(Short)
JP2
AVDD
(Short)
JP7
PVDD
JP6
PIC-VDD-SEL
(Short)
DVDD
USB-3.3V
USB-5V
Connection of power supply lines
Name
+12V
Color
Red
Voltage
+9~+12V
GND
Black
0V
Comment
Regulator,
Power supply for op-amp
Ground
Table 2. Power Supply Connection
Attention
This jack is always needed.
This jack is always needed.
Each supply line should be distributed separately from the power supply unit. The power of the AK7757 and
peripheral devices is supplied by two 12V=>3.3V regulators mounted on the evaluation board.
(2) Set up the evaluation mode, jumper pins and connectors according to the following section.
(3) Connect the AKD7757-A to a PC with the USB cable that is packed with the board.
It is required to initialize the USB control chip once by pushing down the SW2.
(4) Power On.
(5) Start the control soft and setup the registers.
„ Evaluation Mode
In case of evaluating the AK7757 using the AK4118A, it is necessary to adjust audio interface formats of the
AK7757 and the AK4118A to correspond with each other. Refer to the AK7757’s datasheet for audio interface
format of the AK7757. Refer to Table 10 for audio interface format of the AK4118A.
Applicable Evaluation Mode
(1) Evaluation mode of ADC and DAC via SMUX-PORT: CKM Master Mode = 0/1
(2) Evaluation mode of ADC and DAC via SMUX-PORT: CKM Slave Mode = 2/3/
(3) Evaluation mode of DSP via SMUX-PORT: CKM Master Mode = 0/1
(4) Evaluation mode of DSP via SMUX-PORT: CKM Slave Mode = 2/3
Refer to the “CONTROL SOFT MANUAL” paragraph and the datasheet of the AK7757 to set up FPGA, AK4118A
and AK7757 by a PC.
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(1) Evaluation mode of ADC and DAC via SMUX-PORT: CKM Master Mode = 0/1
SMUX-POUT is used. Set the clock mode of the AK7757 to CKM Master Mode 0 (12.288MHz) or CKM Master
Mode 1 (18.432MHz). AK7757 supplies BICK and LRCK to the SMUX-PORT and the SMUX-PORT outputs the
data from SDOUT1, SDOUT2, SDOUT3 or SDOUTM to SDIN1 or SDIN2.
[Jumper Setting]
JP10
XTI-SEL
EXT
CRY
[Connector Setting]
For evaluating ADC1, RCA1/RCA2 (differential input 1), RCA3 (differential input 2), RCA5/RCA6
(single-ended input 1) and RCA7 (single-ended input 2) are available. For evaluating ADC2, RCA4 (differential
input) is available. For evaluating DAC, use terminals of the sub board or main board. Refer to Table 3 and Table
4 to set up the jumpers.
(2) Evaluation mode of ADC and DAC via SMUX-PORT: CKM Slave Mode = 2/3
SMUX-PORT is used. Set the clock mode of the AK7757 to CKM Slave Mode 2/3.
SMUX-PORT supplies MCLK, BICK, LRCK and digital data to the AK7757.
(MCLK is needed only in CKM Slave Mode 2.)
[Jumper Setting]
JP10
XTI-SEL
EXT
CRY
(It is needed only when CKM Slave Mode = 2)
[Connector Setting]
For evaluating ADC1, RCA1/RCA2 (differential input 1), RCA3 (differential input 2), RCA5/RCA6
(single-ended input 1) and RCA7 (single-ended input 2) are available. For evaluating ADC2, RCA4 (differential
input) is available. For evaluating DAC, use terminals of the sub board or main board. Refer to Table 3 and Table
4 to set up the jumpers.
(3) Evaluation mode of DSP using SMUX-PORT: CKM Master Mode = 0/1
SMUX-PORT and SMUX-PORT2 are used. Set the clock mode of the AK7757 to CKM Master Mode 0
(12.288MHz) or CKM Master Mode 1 (18.432MHz). The AK7757 supplies BICK and LRCK to SMUX-PORT
and SMUX-PORT2. SMUX-PORT outputs data from SDOUT1, SDOUT2 or SDOUTM and SMUX-PORT2
inputs data to SDIN1 or SDIN2.
[Jumper Setting]
JP10
XTI-SEL
EXT
CRY
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(4) Evaluation mode of DSP via SMUX-PORT: CKM Slave Mode = 2/3
SMUX-PORT and SMUX PORT2 are used. Set the clock mode of the AK7757 to CKM Slave Mode 2/3.
SMUX PORT is used as an input port for MCLK, BICK and LRCK to the AK7757. (MCLK is needed only in
CKM Slave Mode 2.) SMUX-PORT outputs data from SDOUT1, SDOUT2 or SDOUTM, and SMUX-PORT2
inputs data to SDIN1 or SDIN2.
[Jumper Setting]
JP10
XTI-SEL
EXT
CRY
(It is needed only in CKM Slave Mode 2.)
„ Board Control
The AKD7757-A can be controlled by a PC via general USB port. Connect the USB port on the board to PC with the
cable packed with the AKD7757-A.
Control software is also packed with this board and the software manual is included in this manual.
„ LED Indicator
[LED] U11:
When power is supplied, the LED emits red light. It monitors PC-RQN signal and changes the color
to yellow when the board is communicating with a PC.
[LED] D1:
Monitor the status of the IRESTN pin of the AK7757.
“L” → Lighting, “H” → Not Lighting.
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„ Setting of Jumper Pins
Main board:
Jumper / Switch
SW1 (AK4118A Clock)
Setting (Default)
“TX-CLK”
Note
AK4118A Clock Source
“XTL”: Crystal Clock
“TX-CLK”: External Clock
JP1 (DVDD)
Short
DVDD of the AK7757
JP2 (AVDD)
Short
AVDD of the AK7757
JP3 (AINL)
AINL3
JP4 (AINR)
AINR3
Single-end input selector for ADC1
USB chip power supply
JP6 (PIC-VDD-SEL)
“USB 3.3V”
JP7 (PVDD)
Short
JP11 (AOUTL1N)
Short
JP12 (AOUTL1P)
Open
JP13 (AOUTR1N)
Short
JP14 (AOUTR1P)
Open
JP15 (AOUTL2N)
Short
JP16 (AOUTL2P)
Open
JP17 (AOUTR2N)
Short
JP18 (AOUTR2P)
Open
“USB-5V”: USB 5V
“USB-3.3V”: USB 3.3V
“DVDD”: Peripheral DVDD 3.3V
Peripheral DVDD 3.3V
DAC1, DAC2 Output
Table 3. Setting of Jumper Pins on Main Board
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Sub board:
Jumper / Switch
Setting (Default)
JP1 (REG-SEL)
Short
JP2 (DVDD18-SEL)
Short
JP3 (AO2R-SEL)
“THR”
JP4 (AO2L-SEL)
“THR”
JP5 (AO1R-SEL)
“THR”
JP7 (AO1L-SEL)
“THR”
JP6 (SO-SEL)
“SO”
JP8 (MB-SEL)
open
JP9 (MICIN-SEL)
“AIN”
JP10 (XTI-SEL)
“CRY”
Note
Regulator(U1) Operation Select
“Short”: ON
“Open”: OFF
DVDD18 of the AK7757
“Short”: Regulator(U1) Output
“Open”: JP2-2 Input
AOUT2R Output Select of the AK7757
“THR”: RCA4(DAC2R) on the Sub Board
“AMP”: RCA12(DAC2R) on the Main Board
AOUT2L Output Select of the AK7757
“THR”: RCA3(DAC2L) on the Sub Board
“AMP”: RCA11(DAC2L) on the Main Board
AOUT1R Output Select of the AK7757
“THR”: RCA2(DAC1R) on the Sub Board
“AMP”: RCA10(DAC1R) on the Main Board
AOUT1L Output Select of the AK7757
“THR”: RCA1(DAC1L) on the Sub Board
“AMP”: RCA9(DAC1L) on the Main Board
SO/SDA Input Select of the AK7757
“SO”: Microprocessor Interface (I2CSEL=L)
“SDA”: I2C-bus Interface (I2CSEL=H)
for MICBIAS evaluation of the AK7757
AIN/INP Input Select of the AK7757
“AIN”: MIC Single-ended Input
“INP”: MIC Differential Non-inverted Input
AK7757 Clock Source
“CRY”: Crystal Clock
“EXT”: External Clock
Table 4. Setting of jumper pins on sub board
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„ Analog Input Circuit
Figure 3. ADC1 Analog Differential Input Circuit 1
For ADC1 analog differential input 1, RCA1(AIN(D)-2R), RCA2(AIN(D)-2L) are available.
The input range of each channel is ±[email protected].
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Figure 4. ADC1 Analog Differential Input Circuit 2
For ADC1 analog differential input 2, RCA3(AIN(D)-IN) is available. Set the JP9 jumper pin on the sub board to INP
setting. The input range of each channel is ±[email protected].
Figure 5. ADC2 Analog Differential Input Circuit
For ADC2 analog differential input, RCA4(AIN(D)-T) is available.
The input range of each channel is [email protected].
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Invert the Polarity
Invert the Polarity
Figure 6. ADC1 Analog Single-ended Input Circuit 1
For ADC1 analog single-ended input 1, RCA5(AIN(S)-L), RCA6(AIN(S)-R) are available.
The input range of each channel is [email protected].
Jumper Pin Setting for Analog Single-ended Input Circuit
1-2 pin
3-4 pin
5-6 pin
7-8 pin
Input
AIN1L/ AIN1R
Short
Open
Open
Open
Default
Table 5. Jumper Pin Setting for Analog Single-ended Input Circuit of ADC1
Invert the Polarity
Figure 7. ADC1 Analog Single-ended Input Circuit 2
For ADC1 analog single-ended input 2, RCA7(AIN) is available.
The input range of each channel is [email protected].
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„ Analog Output Circuit
Load Capacitance
Load Capacitance
Load Resistance
Load Resistance
Figure 8. DAC1 Analog Output Circuit on Sub Board
For DAC1 sub board analog output, RCA1(DAC1L), RCA2(DAC1R) are available.
The output range of each channel is 2.2Vpp @3.3V.
Load Capacitance
Load Resistance
Load Capacitance
Load Resistance
Figure 9. DAC2 Analog Output Circuit on Sub Board
For DAC2 sub board analog output, RCA3(DAC2L), RCA4(DAC2R) are available.
The output range of each channel is 2.2Vpp @3.3V.
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Open
Open
Figure 10. DAC1 Analog Output Circuit on Main Board
For DAC1 main board analog output, RCA9(DAC1L), RCA10(DAC1R) are available.
The output range of each channel is 2.2Vpp @3.3V.
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Open
Open
Figure 11. DAC2 Analog Output Circuit on Main Board
For DAC2 main board analog output, RCA11(DAC2L), RCA12(DAC2R) are available.
The output range of each channel is 2.2Vpp @3.3V.
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„ Digital Input Circuit (External DIR: PORT1)
Figure 12. Digital Input Circuit
For digital input SPDIF-IN, optical connector PORT1 is available.
„ Digital Output Circuit (External DIT: PORT2)
Figure 13. Digital Output Circuit
For digital output SPDIF-OUT, optical connector PORT2 is available.
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Control Software Manual
„ Set-up of the Evaluation Board and Control Software
(1) Set up the AKD7757-A according to previous paragraphs of this document.
(2) Connect AKD7757-A to PC with the cable packed Push down the reset button (SW2) to initialize the USB control
chip.
(3) Insert the CD-ROM labeled “AKD7757-A Evaluation Kit” into the CD-ROM drive.
(4) Access the CD-ROM drive and double-click the icon of “AK7757.exe” to start the control software.
AK7757.exe: Control Software for the AK7757
(5) Proceed the evaluation according to the follow sections.
„ Operation Flow
(1) Start the control software according to the set-up sequence above.
(2) Select the needed dialogue and set for the evaluation. (If the USB cable is disconnected when the control software
is running, it is necessary to quit the control software once and restart to use the software again.)
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„ Description of Control Software
(1) Main Dialogue
Figure 14. Main Dialogue of Control Software
Control software is used to a download program, to set up the registers of the AK7757 and FPGA and to process a script
file. These functions can be selected by the tab items above. The buttons of control signals that are frequently used and
the initialization buttons are placed outside the tab dialogue. The control interface of the control software, “Serial
(4-wire)” or “I2C”, is displayed in the “Control I/F” window.
[IRSTN]:
[CODEC]:
[DSP]:
[Clock]:
[Board Init]:
[READ]:
Initial Reset. It is used to initialize the AK7757.
CODEC Reset. ACD and DAC will be reset.
DSP Reset.
Clock Reset. Clock Reset is required when changing the clock mode or the frequency of input clock
without initial reset. All registers will not be initialized.
Initial Reset. It initializes all software setting of the AKD7757; registers of the AK7757, FPGA and
AK4118A.
Read out register settings of the AK7757 and display them in “Register” window.
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(2) “DownLoad” Dialogue
Figure 15. “Down Load” Dialogue
Select a file for Source box, Program box, CRAM box or OFREG bix by clicking the [refer] button of each box, or by
drag and drop a file to the box.
Select a file for CRAM box and OFRAM box by clicking [refer] button. CRAM and OFREG writings during RUN are
available. Data is written to the determined address of CRAM/OFRAM during RUN by clicking the [write] button.
[Assemble]:
[Write]:
[Assemble Write]:
[PRAM read]:
[CRAM read]:
[OFREG read]:
[CRAM SAVE]:
[OFREG SAVE]:
[MICR1~MIR4]:
[JX]:
[CRC-Check]:
[Auto RUN]:
Compiles the source file, and the output file will be selected to the download program automatically.
Downloads the program file to the AK7757.
Compiles the source file, and then downloads the program file to the AK7757.
Reads the data of PRAM to a temporary file and opens the file.
Reads the data of CRAM to a temporary file and opens the file.
Reads the data of OFREG to a temporary file and opens the file.
Reads the data of CRAM and saves to a file.
Reads the data of OFREG and saves to a file.
Reads the data of register MICR1~MIR4 when a program is running and displays the result.
JX code setting.
If this box is checked, simple write error check is done by CRC when downloading a file to
theAK7757.
If this box is checked, the AK7757 will be set to run mode automatically after downloading a
program. If this box is not checked, the AK7757 will be set to DSP reset and CODEC reset mode after
downloading a program.
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(3) “REG” Dialogue
Figure 16. “REG1” Dialogue
Set up the registers of the AK7757 by REG1~REG6 dialogues. (It is prohibited to modify TEST and Reserved items.) As
the checkbox is clicked, the data will be written to the AK7757. Register settings must be made during CODEC reset and
DSP reset.
The reference pages of register settings in datasheet are shown below:
Register
Reference Page
Register
Reference Page
CONT00
27
CONT09
36
CONT01
28
CONT0A
36,37
CONT02
29
CONT0B
38
CONT03
30
CONT0C
38,39
CONT04
31
CONT0D
40
CONT05
32
CONT0E
41
CONT06
33
CONT10-13
42
CONT07
34
CONT14-17
43
CONT08
35
Table 6. Reference Page of Register Settings
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(4) “FPGA” Dialogue
Figure 17. “FPGA1” Dialogue
FPGA1/FPGA2 dialogues are used to modify the data path of the AK7757 and the setting of the AK4118A.
(It is prohibited to modify TEST and Reserved items.)
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FPGA Setting Table: (Bold type items are default settings.)
ADDRESS: 00
Bit
Function
D[15]
Reserved
D[14]
SDOUT3or M-SEL
D[13:12]
TX-DAT
D[11:10]
SDIN1
D[9:7]
SDIN2/JX0
D[6:5]
RDY/SDOUT2/JX
3
D[4:0]
Reserved
Description
Reserved
SDOUT3 or M Output Data Select
0: SDOUT3
1: SDOUTM
Output Data Source to the TX-DAT of the AK4118
00: SDOUT1
01: SDOUT2
10: SDOUT3 or M
11: Low
Input Data source to the SDIN1 pin of the AK7757
00: AK4118 IN
01: SMUX1-DAT1
10: SMUX2-DAT1
11: Low
Input Data Source to the SDIN2/JX0 pin of the AK7757
000: AK4118 IN
001: SMUX1-DAT1
010: SMUX2-DAT1
011: Low
100: Low
101: High
110: Low
111: Low
Input/Output Setting of the AK7757’s RDY/SDOUT2/JX3 pin
00: RDY output
01: SDOUT2 output
10: JX3 input Low
11: JX3 input High
Reserved
Table 7. FPGA Setting Table 1
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ADDRESS: 01
Bit
Function
D[15,14]
BICK1/LRCK1
D[13:11]
BICK2/JX2
D[10:8]
LRCK2/JX1
D[7:6]
EXT-XTI
D[5]
TRX-PDN
D[4]
TRX-BICK/LRCK
D[3]
SMUX2 In/Out
D[2]
SMUX1 In/Out
D[1:0]
Reserved
Description
Input Data Source to the BICK1/LRCK1 pin of the AK7757
00: AK4118-BICK/LRCK
01: SMUX1-BICK/LRCK
10: SMUX2-BICK/LRCK
11: Low
Input Data Source to the BICK2/JX2 pin of the AK7757
000: AK4118-BICK
001: SMUX1-BICK
010: SMUX2-BICK
011: Low
100: Low
101: High
110: Low
111: Low
Input Data Source to the LRCK2/JX1 pin of the AK7757
000: AK4118-LRCK
001: SMUX1-LRCK
010: SMUX2-LRCK
011: Low
100: Low
101: High
110: Low
111: Low
Input Data Source to the XTI pin of the AK7757 in Slave Mode
00: AK4118-RX-CLK
01: SMUX1-MCLK
10: SMUX2-MCLK
11: Low
High/Low select of the AK4118’s PDN pin
0: Low
1: High
Input/Output Setting of the AK4118’s BICK/LRCK pin
0: BICK/LRCK input
1: BICK/LRCK output
Input/Output Setting of the SMUX PORT2’s BICK/LRCK pin
0: BICK/LRCK input
1: BICK/LRCK output
Input/Output Setting of the SMUX1 PORT1’s BICK/LRCK pin
0: BICK/LRCK input
1: BICK/LRCK output
Reserved
Table 8. FPGA Setting Table 2
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ADDRESS: 02
Bit
Function
D[15:14]
SMUX2-DAT2
D[13:12]
SMUX1-DAT2
D[11,10]
TX-CLK
D[9]
D[8:7]
Reserved
CAD[1:0]
D[6:5]
SMUX2-MCLK
D[4:3]
SMUX1-MCLK
D[2:0]
Reserved
Description
Output Data Source to the DAT2 pin of the SMUX PORT2
00: SDOUT1
01: SDOUT2
10: SDOUT3 or M
11: Low
Output Data Source to the DAT2 pin of the SMUX PORT1
00: SDOUT1
01: SDOUT2
10: SDOUT3 or M
11: Low
Input Clock Source to the XTI pin of the AK4118
00: AK7757 CLKO
01: SMUX1-MCLK
10: SMUX2-MCLK
11: Low
Reserved
The CAD pin Setting of the AK7757
00: Low,Low
01: Low,High
10: High,Low
11: High,High
Input/Output setting and Output Data Source of the SMUX
PORT2’s MCLK pin
00: MCLK input
01: AK7757-CLKO
10: AK4118-RX-CLK
11: SMUX1-MCLK
Input/Output setting and Output Data Source of the SMUX
PORT2’s MCLK pin
00: MCLK input
01: AK7757-CLKO
10: AK4118-RX-CLK
11: SMUX2-MCLK
Reserved
Table 9. FPGA Setting Table 3
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AK4118A Setting Table: (Bold type items are the default setting.)
Function
Description
MCLK
MCLK Setting of the AK4118A
00: 256fs
01: 256fs
10: 512fs
11: 128fs
CM
CM Mode Setting of the AK4118A
00: CM = 00
01: CM = 01
10: CM = 10
11: CM = 11
DIF
DOF Mode Setting of the AK4118A
000: 16bit Right ( O )
001: 18bit Right ( O )
010: 20bit Right ( O )
011: 24bit Right ( O )
100: 24bit Left ( O )
101: 24bit I2S ( O )
110: 24bit Left ( I )
111: 24bit I2S ( I )
Table 10. AK4118A Setting Table
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(5) “SCRIPT” Dialogue
Figure 18. “SCRIPT” Dialogue
When a script file is selected, it will be executed automatically. If [Repeat] button is clicked, the selected script file will be
executed once again.
The script commands are listed as follows.
Command
[SCRIPT]
; Comment
W,<address>,<data>
W,0xC0,0x00
WL,<command>,<address>,<data>,…
WL,0x82,0x0022,0x4000,0x4000,0x4000
WS,<command>,<address>,<data>,…
WS,0x81,0x00,0x22,0x40,0x00,0x40,0x00
RI: H / RI: L
RS: H / RS: L
RD: H / RD: L
RC: H / RC: L
D,<address>,<data>
X,<address>,<data>
P,<message>
T,<wait>
T,50mS
LP:<filename>
LC:<filename>
LO:<filename>
Description
Header of script file. A data error will be detected without this header.
The line following to “;” is recognized as comment and ignored.
Register Write. Both address and data are byte (8bit) assigned.
Continuous Data Write. This command can be used during CRAM run. The
command is byte (8bit) assigned and the following data is word (16bit) assigned.
Continuous Data Write. This command can be used during CRAM run. The
command, address and data are byte (8bit) assigned.
Initial Reset. (PDN pin)
CODEC Reset.
DSP Reset.
Clock Reset.
AK4118A Write Command
FPGA Register Write Command
Displays a message and pose the script.
Wait some micro sec.
50msec wait.
Program file download to the DSP.
Coefficient file download to the DSP.
Off-set file download to the DSP.
Table 11. Script Command Table
<KM109000>
2011/12
- 25 -
[AKD7757-A]
REVISION HISTORY
Date
(yy/mm/dd)
11/12/19
Manual
Revision
KM109000
Board
Revision
0
Reason
Page
Contents
First Edition
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
<KM109000>
2011/12
- 26 -
5
4
3
2
1
TP1
TP2
AVDD1
DVDD2
TP3
TP4
TP5
I2CSEL
IRSTN
TP6
TP7
TP8
TP9
TP10
TP11
TP12
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
60
0.1uFを優先にAK7757の近くに配置してください
テストピンは未実装にしてください(AGND,DGNDは実装)
59
CN1
TP13
TP14
SDO3/EXPDRN
TP16
SDOUT1
AVSS
DVSS
BICK2/JX2
TP15
LRCK2/JX1
D
C6
0.1uF
0.1uF
0.1uF
TA48018BF
2
DAC出力はジャンパーで
AMPorスルー出力を切り替える
G61
AMP-AO2R
61
TP20
JP4
AO2L-SEL
R7 R1 R3 R4
R5 R8 R6
51
51
51
AO1L-SEL
40
41
TP33
AVDD2
42
TP35
VCOM
C14
45
+
1uF
出力電流
JP8
46
TP39
MICBIAS
47
TP40
R22
25
SDOUT1
DVDD18
26
27
28
30
LRCK2/JX1
23
R11
51
22
R13
51
TP32
SI/CAD0
TP34
SCLK/SCL
SDA-SO
R10
51
SO-SO
R12
51
34
LRCK1
33
20
R14
51
19
R15
51
18
R16
51
17
R17
51
16
R18
51
15
R19
51
14
R20
51
13
R21
51
32
TP36
CSN/CAD1
31
TP38
STO/RDY/SDOM
30
TP41
29
XTO
XTI
DVSS
DVDD
28
TP45
12
11
10
AIN2RP
LFLT
9
8
7
負荷容量
27
AVSS
TP46
TP47
SDIN2/JX0
AVSS
G75
TP27
SO
TP43
負荷抵抗
(open)
BICK1
AIN1R
(short)
R23
SDIN1
AGND
AINTN
33pF(DIP)
2.0k(DIP)
TP44
AINTP
AIN2RN
74
SDIN2/JX0
1
73
C16
TP42
AIN
C17
STO/RDY/SDOUTM
AIN1L
72
G74
48
MB-SEL
SCLK/SCL
MICBIAS
51
21
RQN/CAD1
MPRF
R9
JP6
75
26
B
TP48
76
G77
77
25
JP9
MICIN-SEL
AIN-MICIN
TP50
TP52
G78
78
TP51
BICK1
24
TP53
LRCK1
23
TP55
TP54
TP56
LFLT
79
G80
22
R24
TP57
AIN1R
C18
TP58
C19
80
JP10
XTI-SEL
0F(DIP)
(short)
21
8.2k(DIP)
TP59
(open)
EXT-XTI
C20
R25
C21
33nF(DIP)
AIN1L
AVSS
AVSS
CRY-XTI
G79
B
TP49
SDIN1
INP-MICIN
G76
C
35
24
SO-SEL
CLKO
AK7757
AIN2LP
71
0.1uF
LRCKO
AVSS
6
2.2uF
VCOM
5
C13
44
TP37
MPRF
BICKO
SO/SDA
AIN2LN
70
43
C15
0.1uF
36
TP31
SDA
I2CSEL=H：SDA
I2CSEL=L：SO
SI/CAD0
4
10uF
TP30
U2
AVDD
AIN/INP
C12
+
G73
38
51
AOUT1L
INN
C11
AOUT2R
3
69
G72
51
RDY/SDOUT2/JX3
38
39
THR-AO1L
BICK2/JX2
DGND
IRSTN
AOUT1R
I2CSEL
EXPDRN/SDOUT3
JP7
TP28
AOUT1L
68
G71
51
AOUT2L
AO1R-SEL
AMP-AO1L
TP29
G70
51
29
32
31
33
DVSS
34
TP25
AOUT1R
35
JP5
AVSS
THR-AO1R
67
G69
39
100k(DIP)
37
AMP-AO1R
37
G68
DVSS
TP22
CLKO
TP23
AOUT2L
66
G67
DVSS
10u/16V(A)
40
2
G66
C10
DVSS
THR-AO2L
TP26
C
+
0.1uF
TP21
LRCKO
AVDD
65
C9
10uF
TP18
BICKO
DVDD
64
1
R2
TP24
G65
IN
AO2R-SEL
AMP-AO2L
63
G64
0.1uF
DVDD18-SEL
62
G63
OUT
C8
TP19
AOUT2R
36
G62
THR-AO2R
JP3
C7
+
short：REG入力
open：DVDD18入力
JP2
1
10uF
C5
2
10uF
C4
GND
+
+
10uF
REG-SEL
U1
TP17
DVDD18
CN2
D
C3
3
C2
+
C1
short：REG=ON
open：REG=OFF
JP1
SDO2/RDY/JX3
CN3
Y1
R26
0.1uF
C22
C23
0(DIP)
12.288MHz
+
(short)
R27
(open)
AVSS
TP68
9
10
11
12
13
14
15
16
17
18
19
20
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
CN4
C24
C25
22pF(DIP)
22pF(DIP)
EXT
8
DVDD1
7
AIN2RN AIN2RP
G8
AIN2LP
TP74
G7
AIN2LN
10uF
TP73
6
INP
TP72
G6
INN
TP71
5
AINTP
TP70
G5
AINTN
TP69
4
TP67
G4
TP66
3
TP65
G3
TP64
2
1
TP63
G2
CL1
Cut Land short
TP62
1
A
TP61
G1
AVSS
TP60
A
2
DVSS
TP75
AGND
80pin_1_double
TP76
DGND
Title
AKD7757-A-SUB
AVSS
DVSS
Size
C
Date:
5
4
3
2
Document Number
Rev
0
AK7757
Friday, October 14, 2011
Sheet
1
1
of
2
5
4
3
2
1
D
D
RCA:WHITE
20111014変更
100
MR-552LS(W)
T
B
S
+
R28
C28
22uF(A)
33pF(F)(DIP)
R29
THR-AO1R
R30
C29
RCA1
4.7k(DIP)
負荷容量
負荷抵抗
AVSS
C27
AVSS
AVSS
100
MR-552LS(R)
T
B
S
+
C26
THR-AO1L
RCA:RED
22uF(A)
33pF(F)(DIP)
SILK-SCREEN
DAC1L
R31
RCA2
4.7k(DIP)
負荷容量
負荷抵抗
AVSS
AVSS
AVSS
SILK-SCREEN
DAC1R
C
C
20111014変更
100
MR-552LS(W)
T
B
S
+
R32
C32
22uF(A)
33pF(F)(DIP)
R33
THR-AO2R
R34
C33
RCA3
4.7k(DIP)
負荷容量
負荷抵抗
AVSS
C31
AVSS
AVSS
100
MR-552LS(R)
T
B
S
+
C30
THR-AO2L
22uF(A)
33pF(F)(DIP)
SILK-SCREEN
DAC2L
R35
負荷抵抗
AVSS
RCA4
4.7k(DIP)
負荷容量
AVSS
AVSS
SILK-SCREEN
DAC2R
B
B
A
A
Title
AKD7757-A-SUB
Size
B
Date:
5
4
3
2
Document Number
ANALOG
Friday, October 14, 2011
Rev
0
Sheet
1
2
of
2
5
4
3
DGND
CHIP-DGND
XILINX
CLKO
BICKO
LRCKO
EXT-XTI
JX0
SDIN5
GBICK
GLRCK
AK4114
RX-CLK
RX-CLK2
RX-DAT
TX-CLK
TX-DAT
TRX-BICK
TRX-LRCK
RX-CLK
RX-CLK2
RX-DAT
SDIN1
SDIN2
BICKI
LRCLKI
TESTI1
TESTI2
INITRSTN
PC-CS3N
PC-SCLK
PC-SI
RX-CLK
RX-CLK2
RX-DAT
TRX-PDN
TX-CLK
TX-DAT
TRX-BICK
TRX-LRCK
LED-IND
I2CSEL
RQN
SI
SCLK-SCL
SO
RDY
PC-CS3N
PC-SCLK
PC-SI
PC-RQN
PC-SCL
B
PC-I2CSEL
PC-INITRSTN
LED-IND
GP1
SDOUT1
SDOUT2
SDOUT3
CLKO
BICKO
LRCKO
EXT-XTI
JX0
SDIN5
GBICK
GLRCK
SRIN1
SRBICK1
SRLRCK1
SRIN2
SRBICK2
SRLRCK2
SRIN3
SRBICK3
SRLRCK3
SDIN1
SDIN2
BICKI
LRCKI
TESTI1
TESTI2
INITRSTN
I2CSEL
RQN
SI
SCLK-SCL
SO
RDY
GP1
PC-SO
C
SRIN1
SRBICK1
SRLRCK1
SRIN2
SRBICK2
SRLRCK2
SRIN3
SRBICK3
SRLRCK3
PC-CSN2
PC-CS4N
TX-CLK
TX-DAT
TRX-BICK
TRX-LRCK
AGND
SDOUT1
SDOUT2
SDOUT3
CLKO
BICKO
LRCKO
EXT-XTI
Analog Out
AOUTL2N
AOUTL2P
AOUTR2N
AOUTR2P
AOUTL2N
AOUTL2P
AOUTR2N
AOUTR2P
AOUTL2N
AOUTL2P
AOUTR2N
AOUTR2P
AOUTL1N
AOUTL1P
AOUTR1N
AOUTR1P
AOUTL1N
AOUTL1P
AOUTR1N
AOUTR1P
D
AOUTL1N
AOUTL1P
AOUTR1N
AOUTR1P
JX0
SDIN5
GBICK
GLRCK
SRIN1
SRBICK1
SRLRCK1
SRIN2
SRBICK2
SRLRCK2
SRIN3
SRBICK3
SRLRCK3
SDIN1
SDIN2
Analog In
AINL2N
AINL2P
AINR2N
AINR2P
AINL2N
AINL2P
AINR2N
AINR2P
BICKI
LRCKI
TESTI1
TESTI2
INITRSTN
AIN3L
AIN3R
I2CSEL
RQN
SI
SCLK-SCL
SO
RDY
AIN5L
AIN5R
GP1
AINL1N
AINL1P
AINR1N
AINR1P
AINL1N
AINL1P
AINR1N
AINR1P
AINL3
AINR3
AINL2N
AINL2P
AINR2N
AINR2P
AINL5
AINR5
AINL6
AINR6
AINL6
AINR6
A2INL
A2INR
A2INL
A2INR
C
AINL4
AINR4
AINL5
AINR5
AIN6L
AIN6R
AINL1N
AINL1P
AINR1N
AINR1P
AINL3
AINR3
AINL4
AINR4
AIN4L
AIN4R
POWER
B
A2INL
A2INR
SDA
D
TRX-PDN
1
AK7722
SDOUT1
SDOUT2
SDOUT3
TRX-PDN
2
LED-IND
PC-IF
PC-CS3N
PC-SCLK
PC-SI
PC-RQN
PC-SCL
PC-I2CSEL
PC-INITRSTN
A
PC-CS2N
PC-CS4N
PC-SO
PC-SDA
PC-CS3N
PC-SCLK
PC-SI
PC-RQN
PC-SCL
PC-I2CSEL
PC-INITRSTN
A
PC-CS2N
PC-CS4N
Title
PC-SO
PC-SDA
<AKD7722-A>
Size
A4
Date:
5
4
3
2
Document Number
<TOP>
Tuesday, August 30, 2011
Rev
<0.0>
Sheet
1
1
of
8
5
4
3
2
1
D
D
DVDD-3.3V
DVDD-3.3V
C1
+
C2
L1
SILK-SCREEN
SPDIN-IN
10uF
0.1uF
10uH
PORT1
SPDIF-IN
VCC
GND
OUT
3
2
1
R2
470
C3
R1
DIF-RX
0.1uF
10k
TORX147
RX3
VSS4
RX2
TEST1
RX1
NC
RX0
VSS3
VCOM
R
AVDD
INT1
U1
1
2
3
4
5
6
7
8
9
10
11
12
C
DVDD-3.3V
RX4
NC
RX5
TEST2
RX6
VSS1
RX7
IIC
P/SN
XTL0
XTL1
VIN
L2
AK4118A
13
14
15
16
17
18
19
20
21
22
23
24
SILK-SCREEN
SPDIN-OUT
48
47
46
45
44
43
42
41
40
39
38
37
C5
10uF
10uH
PORT2
SPDIF-OUT
IN
VCC
GND
3
2
1
INT0
CSN
CCLK
CDTI
CDTO
PDN
XTI
XTO
DAUX
MCKO2
BICK
SDTO
36
35
34
33
32
31
30
29
28
27
26
25
C
PC-CS3N
PC-SCLK
PC-SI
SW1
TRX-PDN
TX-CLK
TX-CLK
XTL
R3
R4
R5
TX-DAT
RX-CLK2
TRX-BICK
RX-DAT
100
100
100
TVDD
NC
TX0
TX1
BOUT
COUT
UOUT
VOUT
DVDD
VSS2
MCKO1
LRCK
+
C4
0.1uF
XTAL1
12.288MHz
22pF
C6
22pF
C7
AK4118A
R6
100
R7
100
TRX-LRCK
RX-CLK
DIF-TX
C8
0.1uF
0.1uF C9
C12
10uF
10uF
TOTX147
C10 +
0.1uF
C11
10uF
C13
B
+
+
B
DVDD-3.3V
DVDD-3.3V
DVDD-3.3V
TP1
TP (Black)
+
DVSS
C14
100uF/16V(A)
A
A
Title
<AKD7722-A>
Size
A3
Date:
5
4
3
2
Document Number
<AK4118A>
Tuesday, August 30, 2011
Rev
<0.0>
Sheet
1
2
of
8
1
SDOUT1
SDOUT2
㩿㪪㪛㪦㪬㪫㪉㪆㪩㪛㪰㪆㪡㪯㪊㪀
SDOUT3
㩿㪪㪛㪦㪬㪫㪊㪆㪜㪯㪧㪛㪩㪥㪀
SRLRCK2
SRIN2
2
SRBICK2
㩿㪣㪩㪚㪢㪉㪆㪡㪯㪈㪀
SRBICK3
SRLRCK3
㩿㪙㪠㪚㪢㪉㪆㪡㪯㪉㪀
SRIN3
㩿㪠㪩㪪㪫㪥㪀
I2CSEL
3
INITRSTN
4
TESTI2
5
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
D
60
D
CN3
CN4
G61
61
AOUTR2N
40
BICKO
G62
62
AOUTR2P
39
LRCKO
CLKO
㩿㪘㪦㪬㪫㪉㪩㪀
G63
63
AOUTL2N
38
G64
64
AOUTL2P
37
G65
65
AOUTR1N
36
G66
66
AOUTR1P
35
㩿㪘㪦㪬㪫㪉㪣㪀
SDA
㩿㪘㪦㪬㪫㪈㪩㪀
G67
67
AOUTL1N
G68
68
AOUTL1P
34
SO
33
SI
DGND
C
C
㩿㪪㪠㪆㪚㪘㪛㪇㪀
㩿㪘㪦㪬㪫㪈㪣㪀
G69
69
32
G70
70
31
SCLK-SCL
RQN
㩿㪚㪪㪥㪆㪚㪘㪛㪈㪀
RDY
G71
71
30
G72
72
A2INR
29
SRIN1
G73
73
A2INL
㩿㪘㪠㪥㪀
28
SRBICK1
G74
74
AIN6R
27
SRLRCK1
G75
75
AIN6L
26
㩿㪪㪫㪦㪆㪩㪛㪰㪆㪪㪛㪦㪬㪫㪤㪀
AGND
SDIN2
㩿㪪㪛㪠㪥㪉㪆㪡㪯㪇㪀
㩿㪘㪠㪥㪉㪩㪧㪀
SDIN1
BICKI
EXT-XTI
SDIN5
GBICK
GLRCK
㩿㪙㪠㪚㪢㪈㪀
TESTI1
㩿㪘㪠㪥㪉㪩㪥㪀
24
AINL1P
AINL1N
㩿㪘㪠㪥㪉㪣㪧㪀
㩿㪘㪠㪥㪉㪣㪥㪀
AINR1P
AINR1N
㩿㪠㪥㪥㪀
㩿㪠㪥㪧㪀
AIN4R
AINL2P
78
AINL2N
G78
㩿㪘㪠㪥㪫㪧㪀
AIN5L
㩿㪘㪠㪥㪫㪥㪀
77
AINR2P
G77
25
AINR2N
AIN5R
㩿㪘㪠㪥㪈㪣㪀
76
AIN3L
B
G76
23
B
LRCKI
㩿㪣㪩㪚㪢㪈㪀
G79
79
AIN4L
22
JX0
G80
80
AIN3R
㩿㪘㪠㪥㪈㪩㪀
21
GP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
CN2
CN1
DVDD
HEADER 2
AVDD
CHIP-DVDD
HEADER 2
SILK-SCREEN
CHIP-AVDD
2PIN: [->]
A
1
2
1
2
JP1
CHIP-AVDD
SILK-SCREEN
CHIP-DVDD
2PIN: [->]
default short
JP2
A
default short
Title
<AKD7722-A>
Size
A2
Date:
5
4
3
2
Document Number
<AK7722>
Rev
<0.0>
Tuesday, September 13, 2011
1
Sheet
3
of
8
5
4
3
RCA: WHITE
1
RCA: RED
AREA : SHORTEST WIRING
SILK-SCREEN
AIN(D)-1L
2
AINL1N
SILK-SCREEN
AIN(D)-1R
㩿㪘㪠㪥㪉㪩㪥㪀
RCA2
C16
R8
10k
C17
RCA1
R10
10k
R9 10k
22uF(A)
C21 68pF(F)
22uF(A)
T
B
S
C19
68pF(F)
D
㩿㪘㪠㪥㪉㪣㪥㪀
C22 68pF(F)
22uF(A)
C20
68pF(F)
MR-552LS(R)
8
㩿㪘㪠㪥㪉㪩㪧㪀
R16
C24
4
7
AINR1P
22uF(A)
㩿㪘㪠㪥㪉㪣㪧㪀
C32
0.1uF
C34
10uF
+
U3B
LME49720MA
AMP-PW+
+
C31
10uF
TP2
TP (Black)
AVSS
5
2k
C28
100pF
R23
10k
C29
0.1uF
C33
0.1uF
C26
100pF
R21
10k
AMP-PW+
+
C30
10uF
3
2k
6
+
R18
AINL1P
R15
10k
1
8
4
4
7
22uF(A)
C27
100pF
U3A
LME49720MA
+
5
2k
8
R19
2
AMP-PW+
8
4
6
+
C25
100pF
R20
10k
1
C23
+
-
3
2k
U2B
LME49720MA
-
R17
R14
10k
+
U2A
LME49720MA
-
2
AMP-PW+
R22
10k
22uF(A)
+
MR-552LS(W)
R13
10k
R12 10k
+
+
T
B
S
R11
10k
C18
-
D
+
AINR1N
+
C15
C35
0.1uF
C36
10uF
+
C
C
SILK-SCREEN
AIN(D)-2L
AINL2N
SILK-SCREEN
AIN(D)-2R
㩿㪠㪥㪥㪀
RCA4
C38
R24
10k
C39
RCA3
22uF(A)
22uF(A)
T
B
S
C41
68pF(F)
C44
68pF(F)
8
8
㩿㪠㪥㪧㪀
R39
10k
C51
0.1uF
C55
0.1uF
C59
RCA5
ᭂᕈ䉕ㅒ䈮
1
3
5
7
22uF(A)
MR-552LS(W)
AVSS
C56
10uF
2
4
6
8
AINL3
AINL4
AINL5
AINL6
+
C54
10uF
AINL3
AINL4
AINL5
AINL6
AINR2P
22uF(A)
㩿㪘㪠㪥㪫㪧㪀
AMP-PW+
B
C57
0.1uF
C60
T
B
S
22uF(A)
MR-552LS(R)
ᭂᕈ䉕ㅒ䈮
+
C58
10uF
JP4
1
3
5
7
AINR3
AINR4
AINR5
AINR6
2
4
6
8
AINR3
AINR4
AINR5
AINR6
㩿㪘㪠㪥㪈㪩㪀
(default 1-2 pin short)
SILK-SCREEN
AIN(S)-R
A2INL
㩿㪘㪠㪥㪀
T
B
S
MR-552LS(W)
MR-552LS(R)
SILK-SCREEN
A2INL
SILK-SCREEN
A2INR
+
C62
RCA8
ᭂᕈ䉕ㅒ䈮
22uF(A)
A2INR
A
22uF(A)
Title
<AKD7722-A>
Size
A3
Date:
5
C46
7
HEADER 4X2
+
T
B
S
5
TP3
TP (Black)
㩿㪘㪠㪥㪈㪣㪀
(default 1-2 pin short)
C61
RCA7
2k
U5B
LME49720MA
C53
0.1uF
HEADER 4X2
SILK-SCREEN
AIN(S)-L
R35
C50
100pF
RCA6
JP3
+
T
B
S
+
C48
100pF
R37
10k
AMP-PW+
+
C52
10uF
3
2k
6
+
R34
AINL2P
1
8
7
R33
10k
4
4
AMP-PW+
22uF(A)
C49
100pF
U5A
LME49720MA
8
5
2k
2
+
4
+
R32
C45
+
4
6
+
-
1
U4B
LME49720MA
+
R30
10k
-
U4A
LME49720MA
+
3
2k
C47
100pF
R36
10k
A
C43 68pF(F)
22uF(A)
-
2
R31
R38
10k
㩿㪘㪠㪥㪫㪥㪀
MR-552LS(R)
AMP-PW+
B
22uF(A)
-
MR-552LS(W)
R29
10k
R28 10k
+
C42 68pF(F)
R27
10k
C40
+
T
B
S
R26
10k
R25 10k
+
AINR2N
+
C37
4
3
2
Document Number
<Analog In>
Tuesday, September 13, 2011
Rev
<0.0>
Sheet
1
4
of
8
5
4
3
JP11, JP12, JP13, JP14,
JP15, JP16, JP17, JP18
default short
AOUTR1N
TP6
RCA: WHITE
㩿㪘㪦㪬㪫㪈㪩㪀
AOUTL1JP11
R41 8.2k
C64
22uF(A)
RCA: RED
AOUTR1JP13
R49 300
R58
8.2k
C76
270pF(F)
RCA9
T
B
S
R55
10k
8
䉥䊷䊒䊮
C75
30pF (DIP,open)
R54
5.1k (DIP,open)
1
AOUTR1P
AOUTR1P
TP7
C74
22uF(A)
AMP-PW+
C70
2200pF(F)
AOUTR1+
JP14
6
R52 8.2k
R53 300
5
䉥䊷䊒䊮
C77
30pF (DIP,open)
R56
5.1k (DIP,open)
MR-552LS(W)
C68 270pF(F)
R59
8.2k
U6B
LME49720MA
4
R48
220
R47 300
+
3
C72
22uF(A)
C66
30pF (DIP,open)
7
C73
22uF(A)
R51
220
RCA10
T
B
S
R57
10k
8
2
R50 8.2k
U6A
LME49720MA
+
AOUTL1+
JP12
4
C69
2200pF(F)
R45
5.1k (DIP,open)
+
C71
22uF(A)
C67 270pF(F)
-
AOUTL1P
TP5
R42 8.2k
R46 300
+
AOUTL1P
C65
30pF (DIP,open)
+
R40 8.2k
R44
5.1k (DIP,open)
D
R43 8.2k
+
AOUTR1N
+
AOUTL1N
AOUTL1N
TP4
C63
22uF(A)
AREA : SHORTEST WIRING
+
㩿㪘㪦㪬㪫㪈㪣㪀
1
-
D
2
C78
270pF(F)
MR-552LS(R)
SILK-SCREEN
DAC1L
C79
+
0.1uF
AMP-PW+
SILK-SCREEN
DAC1R
C80
10uF
AMP-PW+
R60
4.7k
AOUTR2N
AOUTL2+
JP16
4
C89
2200pF(F)
2
R71 8.2k
R70 300
䉥䊷䊒䊮
C95
30pF (DIP,open)
R76
5.1k (DIP,open)
R78
8.2k
U7A
LME49720MA
C94
22uF(A)
1
C96
270pF(F)
R75
220
R77
10k
RCA11
T
B
S
AOUTR2P
R65 8.2k
C86
30pF (DIP,open)
AOUTR2P
TP12
C93
22uF(A)
R69 300
C88 270pF(F)
C90
2200pF(F)
AOUTR2+
JP18
6
R73 8.2k
R74 300
5
䉥䊷䊒䊮
C97
30pF (DIP,open)
R79
5.1k (DIP,open)
MR-552LS(W)
AMP-PW+
R64 8.2k
+
+
3
R67
5.1k (DIP,open)
+
C91
22uF(A)
C87 270pF(F)
8
AOUTL2P
TP10
R68 300
+
B
C85
30pF (DIP,open)
AOUTR2JP17
R81
8.2k
U7B
LME49720MA
7
B
C92
22uF(A)
R72
220
RCA12
T
B
S
+
R63 8.2k
4
R62 8.2k
AOUTR2N
TP11
C84
22uF(A)
C144
0.1uF
R80
10k
8
㩿㪘㪦㪬㪫㪉㪩㪀
C143
10uF
+
+
R66
5.1k (DIP,open)
AOUTL2P
AOUTL2JP15
R123
4.7k
+
AOUTL2N
AOUTL2N
TP9
C83
22uF(A)
AVSS
C82
0.1uF
-
㩿㪘㪦㪬㪫㪉㪣㪀
C81
10uF
+
+
R61
4.7k
C
TP8
TP (Black)
-
C
R122
4.7k
C98
270pF(F)
MR-552LS(R)
SILK-SCREEN
DAC2L
C99
+
0.1uF
AMP-PW+
C100
10uF
AMP-PW+
R82
4.7k
AVSS
R83
4.7k
C101
10uF
+
SILK-SCREEN
DAC2R
R124
4.7k
TP13
TP (Black)
C102
0.1uF
R125
4.7k
+
C145
10uF
C146
0.1uF
䉝䊮䊒䉕ㅢ䈚䈢಴ജ䈮෻ォ౉ജ஥䉕૶↪䈚䇮
㕖෻ォ஥䉕䉥䊷䊒䊮䈮䈜䉎䇯
A
A
Title
<AKD7722-A>
Size
A3
Date:
5
4
3
2
Document Number
<Analog Out>
Tuesday, September 13, 2011
Rev
<0.0>
Sheet
1
5
of
8
5
4
3
2
1
R84 10k
APE 1F
Reset
18
USB-RST
12
13
33
34
29
JP5
MCLR_N/Vpp/RE3
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CPP2/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
(default : Release)
R86
10k
VDD1
SW2
VDD0
Release
VSS1
7
U8
6
USB Reset
D
C107
0.1uF
28
C106
0.1uF
NC/ICCK/ICPGC
NC/ICDT/ICPGD
NC/ICRST_N/ICVpp
NC/ICPORTS
1
2
3
4
5
17
16
15
14
11
10
9
8
SILK-SCREEN
1: VDD
2: MCLR
3: PGD
4: PGC
5: GND
SILK-SCREEN
1: USB-5V
3: USB-3.3V
5: DVDD
2
4
6
C104
10uF
1
3
5
+
C103
10uF
VSS0
R85
100k
D
+
USB-VDD
C105
0.1uF
default 3-4 pin short
JP6
PIC-VDD-SEL
DVDD-3.3V
HEADER 5
C10822pF
25
26
27
DVDD-3.3V
OSC1/CLKI
OSC2/CLKO/RA6
PIC18F4550
TQFP 44-PIN
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
C
R87
10k
R88
37
C114 470nF
100
19
20
21
22
23
24
PC-SDA
PC-SCL
PC-SO
RD0/SPP0
RD1/SPP1
RD2/SPP2
RD3/SPP3
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
38
39
40
41
2
3
4
5
PC-CS3N
PC-INITRSTN
PC-CS4N
PC-I2CSEL
PC-SCLK
PC-SI
PC-RQN
PC-CS2N
REG1
LM1117-3.3V
1
+
VUSB
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RA0/AN0
RC2/CCP1/P1A
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RC4/D-/VM
RA5/AN4/SS_N/HLVDIN/C2OUT
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
C111
C110
10uF
0.1uF
32
35
36
GND
C10922pF
IN
OUT
2
C112
+
C113
C
3
30
31
XTI
XTO
XTAL2
20MHz
0.1uF
10uF
U9
42
43
44
1
R89
R90
VUSB
DD+
GND
22
22
1
2
3
4
VUSB
DD+
GND
USB(B type)
PIC18F4550
DVDD-3.3V
DVSS
TP14
TP (Black)
C115
+
100uF/16V(A)
B
B
DVDD-3.3V
DVDD-3.3V
U10A
16
14
+
R91
C117
0.1uF
LED-IND
10k
C116
33uF(A)
15
1
2
3
8
U10B
VCC
CEXT
16
6
U11
REXT/CEXT
A
B
CLR
GND
Q
Q
13
R92
4
R93
100
100
1
3
7
GREEN
COM
2
9
10
11
8
RED
BICOLOR LED
74HC221
VCC
CEXT
REXT/CEXT
A
B
CLR
GND
Q
Q
5
12
74HC221
A
A
Title
<AKD7722-A>
Size
A3
Date:
5
4
3
2
Document Number
<PC-IF>
Tuesday, August 30, 2011
Rev
<0.0>
Sheet
1
6
of
8
5
4
3
2
1
D
D
AMP-PW+
DVDD
heatsink
AVDD
REG2
LM1084-3.3V
L3
10uH
+ C119
10uF
C118
0.1uF
+ C120
10uF
C121
0.1uF
CL2
2
GND
TM1
2
CHIP-DVSS
OUT
+ C147
IN
1
1
C122
0.1uF
3
TP15
TP (Black)
+ C123
10uF
+
i
RED(+12V)
TJ-563
C124
100uF/16V(A)
TM2
100uF/16V(A)
1
1
Cut Land short
i
BLACK(GND)
TJ-563
C
C
TP16
TP (Black)
AVSS
SILK-SCREEN
P-DVDD
2 PIN: [->]
2
+ C127
10uF
C125
0.1uF
OUT
LM1084-3.3V
GND
DVSS
REG3
2
1
3
default short
TP17
TP (Black)
IN
1
2
DVDD-3.3V
JP7
HEADER 2
heatsink
CL1
Cut Land short
1
C126
0.1uF
+ C128
10uF
B
B
A
A
Title
<AKD7722-A>
Size
A3
Date:
5
4
3
2
Document Number
<POWER>
Tuesday, August 30, 2011
Rev
<0.0>
Sheet
1
7
of
8
5
4
3
2
1
DVDD-3.3V
C129
0.1uF
SMUX PORT
+ C130
10uF
JP8
D
SMUX-MCLK
SMUX-BICK
SMUX-LRCK
SMUX-DAT1
1
3
5
7
9
D
2
4
6
8
10
SILK-SCREEN
SMUX PORT/SMUX PORT2
1: MCLK
3: BIT
5: LR
7: DI
9: VDD
10: DO
HEADER 5X2
SMUX-DAT2
U12
SMUX PORT2
JP9
TESTI1
GLRCK
GBICK
SDIN5
EXT-XTI
TRX-PDN
TX-CLK
TX-DAT
RX-CLK2
TRX-BICK
RX-DAT
TRX-LRCK
RX-CLK
C
PC-SO
PC-SCL
PC-CSN2
PC-RQN
PC-SI
PC-I2CSEL
PC-CS4N
PC-INITRSTN
PC-CS3N
R98
R94
R95
R121
100
100
100
100
R96
R97
100
100
R104
R105
R106
100
100
100
LED-IND
PC-SCLK
B
R120
100
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
24
25
28
29
30
32
33
34
35
36
37
39
40
41
42
43
99
2
1
4
3
27
23
22
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
GSR
GTS4
GTS3
GTS2
GTS1
GCK3
GCK2
GCK1
JTAG
JP10
2:
4:
6:
8:
10:
TCK
TDI
TDO
TMS
VDD
1
3
5
7
9
48
45
83
47
2
4
6
8
10
HEADER 5X2
TCK
TDI
TDO
TMS
DVDD-3.3V
C141 0.1uF
I/O31
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I/O64
I/O65
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
I/O72
46
49
50
52
53
54
55
56
58
59
60
61
63
64
65
66
67
68
70
71
72
73
74
76
77
78
79
80
81
82
85
86
87
89
90
91
92
93
94
95
96
97
SMUX2-MCLK
SMUX2-BICK
SMUX2-LRCK
SMUX2-DAT1
1
3
5
7
9
C131
0.1uF
2
4
6
8
10
HEADER 5X2
DVDD-3.3V
SMUX2-DAT2
R112
R111
R110
R109
R108
R107
SDOUT1
SDOUT2
SDOUT3
SRLRCK2
SRBICK2
SRIN2
SRLRCK3
SRBICK3
SRIN3
100
100
100
100
100
100
LEAD RED LED
R102
2
1
C
D1
470
INITRSTN
I2CSEL
TESTI2
R99
0
R100
R101
R103
100
100
100
R113
R114
R115
R116
R117
R118
R119
100
100
100
100
100
100
100
BICKO
LRCKO
CLKO
SO
SI
SCLK-SCL
RQN
RDY
SRIN1
SRBICK1
SRLRCK1
SDIN2
SDIN1
BICKI
LRCLKI
JX0
GP1
DVDD-3.3V
VINT0
VINT1
VINT2
VIO0
VIO1
VIO2
VIO3
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
B
5
57
98
C132
0.1uF
C133
0.1uF
26
38
51
88
C134
0.1uF
+ C135
10uF
C136
0.1uF
C137
0.1uF
C138
0.1uF
C139
0.1uF
+ C140
10uF
21
31
44
62
69
75
84
100
XC95144XL
DVSS
TP18
TP (Black)
DVDD-3.3V
+ C142
100uF/16V(A)
A
A
Title
<AKD7722-A>
Size
A3
Date:
5
4
3
2
Document Number
<XILINX>
Tuesday, August 30, 2011
Rev
<0.0>
Sheet
1
8
of
8