D a ta S he e t , V 1 . 3, J u n . 20 0 6 CIC751 Companion IC M i c r o c o n t r o l l er s Edition 2006-06 Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 2006. All Rights Reserved. Attention please! The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D a ta S he e t , V 1 . 3, J u n . 20 0 6 CIC751 Companion IC M i c r o c o n t r o l l er s CIC751 CONFIDENTIAL Revision History: 2006-06 Previous Version: None. V 1.3 Page Subjects (major changes since last revision) 25 chapter 4.4.4. Power Sequencing was reworked for version 1.2 25 chapter 4.4.4. Power Sequencing was reworked for version 1.3 33 table 4-13 updated for version 1.3 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Template: mc_a5_ds_tmplt.fm / 5 / 2006-01-20 CIC751 CONFIDENTIAL Table of Contents Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 2.1 2.2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 3.1 3.1.1 3.1.2 3.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 11 12 12 4 4.1 4.2 4.3 4.4 4.4.1 4.4.1.1 4.4.1.2 4.4.2 4.4.3 4.4.4 4.4.5 4.4.5.1 4.4.6 4.5 4.5.1 4.5.2 4.5.3 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prescaler Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing Waveforms of the digital input/output signals . . . . . . . . . . . . . . Output Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Serial Channel (SSC) Slave Mode Timing . . . . . . . . . . . . Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 15 17 21 21 21 21 23 24 25 27 27 30 32 32 32 33 Data Sheet 1 V 1.3, 2006-06 CIC751 CONFIDENTIAL Data Sheet Table of Contents 2 V 1.3, 2006-06 CIC751 CONFIDENTIAL 1 Summary of Features Summary of Features This section provides a high-level description of the features on the CIC751. • • • • • • • • • • • • 5 V Analog to Digital Converter 16 analog input channels Internal low power oscillator Slave (SPI) SSC interface operating on 5 V or 3.3 V MLI Interface operating on 5 V or 3.3 V Maximum system frequency of 40 MHz Low-power design Single power supply concept design (for pad and core supply) Separated ADC supply Input and output pins with 3.3 V and 5.0 V Flexible clocking concept Crossbar bus architecture Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • • the derivative itself, i.e. its function set, the temperature range, and the supply voltage the package and the type of delivery. For the available ordering codes for the CIC751 please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants. Data Sheet 3 V 1.3, 2006-06 CIC751 CONFIDENTIAL General Device Information 2 General Device Information 2.1 Introduction The CIC751 is a companion IC for the Infineon AUDO-NG family of 32-bit microcontrollers. The major function of the CIC751 is to provide the AUDO-NG 32-bit microcontrollers with the capability of a 5 V Analog to Digital Converter (ADC). The interconnection of the CIC751 and the microcontroller is accomplished via either the Micro Link Interface (MLI) or the Synchronous Serial Interface (SSC). Internal operations of the CIC751 are supported by the very flexible on-chip DMA controller. 2.2 Pin Configuration and Definition The pins of the CIC751 are described in detail in Table 2-1, including all their alternate functions. Table 2-1 Pin Definitions and Functions Symbol Pin/Port I/O Function AIN0 35 P1.0 I Analog Input 01) For this pin a Multiplexer Test Mode is available. AIN1 36 P1.1 I Analog Input 11) AIN2 37 P1.2 I Analog Input 21) AIN3 38 P1.3 I Analog Input 31) AIN4 1 P1.4 I Analog Input 41) AIN5 2 P1.5 I Analog Input 51) AIN6 7 P1.6 I Analog Input 61) AIN7 8 P1.7 I Analog Input 71) AIN8 5 P1.8 I Analog Input 81) AIN9 6 P1.9 I Analog Input 91) Data Sheet 4 V 1.3, 2006-06 CIC751 CONFIDENTIAL Table 2-1 General Device Information Pin Definitions and Functions (cont’d) Symbol Pin/Port I/O Function AIN10 3 P1.10 I Analog Input 101) AIN11 4 P1.11 I Analog Input 111) AIN12 11 P1.12 I Analog Input 121) AIN13 12 P1.13 I Analog Input 131) AIN14 13 P1.14 I Analog Input 141) AIN15 14 P1.15 I Analog Input 151) VAREF 9 I Analog Reference Voltage VAGND 10 I Analog Ground TCLK/SR3 17 P0.0 I/O MODE = 0: MLI Transmit Channel Clock Output MODE = 1: Event output line 3 TREADY/SR4 19 P0.1 I/O MODE = 0: MLI Transmit Channel Ready Input MODE = 1: Event request output line 4 TVALID/SCLK 20 P0.2 I/O MODE = 0: MLI Transmit Channel Valid Output MODE = 1: SPI Serial Channel Clock TDATA/MRST 21 P0.3 I/O MODE = 0: MLI Transmit Channel Data Output MODE = 1: SPI Master Receive Slave Transmit RCLK 22 P0.4 I/O MODE = 0: MLI Receive Channel Clock Input MODE = 1: GPIO Data Sheet 5 V 1.3, 2006-06 CIC751 CONFIDENTIAL Table 2-1 General Device Information Pin Definitions and Functions (cont’d) Symbol Pin/Port I/O Function RREADY/RDY 23 P0.5 I/O MODE = 0: MLI Receive Channel Ready Output MODE = 1: SSC Ready Signal RVALID/SLS 24 P0.6 I/O MODE = 0: MLI Receive Channel Valid Input MODE = 1: SSC Select Slave RDATA/MTSR 25 P0.7 I/O MODE = 0: MLI Receive Channel Data Input MODE = 1: SPI Master Transmit Slave Receive MODE 2) 26 P0.8 I/O Interface Selection Pin MODE selects whether the on-chip MLI or SSC are used to access the CIC751 device. 0: On-chip MLI 1: On-chip SSC Event request output line 5 (SR5) TESTMODE 3) 27 P0.9 I/O Test Mode Selection 4) 0: Reserved; do no use 1: Normal Mode SR0 28 P0.10 I/O Event request output line 0 SR1 29 P0.11 I/O External Trigger SR2 30 P0.12 I/O External Trigger PORST 31 I Power-on Reset5) VDDM 34 +5 V Power Supply, supply for ADC module VDDP 18, 33 +3.3 V Power Supply, supply for I/O pads or +5.0 V VDDC 16 +2.5 V Power Supply, supply for digital module cores6) VSS 15, 32 0V Data Sheet Ground 6 V 1.3, 2006-06 CIC751 CONFIDENTIAL General Device Information 1) In addition to the analog input function of pin P1.x, a digital input stage is available. This input stage is activated while STCU_SYSCON.P1DIDIS = 0. 2) The initial logic state on pin MODE is latched while the PORST input is active. A weak pull-up can be disabled if used as the SR5 pin. 3) The initial logic state on pin TESTMODE is latched while the PORST input is active. 4) The meaning of 0 and 1 is only valid while this pin is latched. Thereafter it can be used as GPIO pin. 5) This pin has no internal pulls. If required an external pull has to be provided. 6) An external capacitance of 220 nF is required for this pin. Figure 2-1 shows the pin-out for a 38-pin package Data Sheet 7 V 1.3, 2006-06 CIC751 CONFIDENTIAL Modules General Device Information Ports Pins P 0. 0 TCLK / S R3 P 0. 1 TRE A DY / S R4 P 0. 2 TV A LI D/ S CLK P 0. 3 TDA TA / M RS T P 0. 4 RCLK P 0. 5 RRE A DY / RDY MLI SSC P0 P 0. 6 Port P 0. 7 Control SCU Function RV A LI D/ S LS RDA TA / M TS R P 0. 8 M ODE / S R5 P 0. 9 TE S TM ODE P 0. 10 S R0 P 0. 11 S R1 P 0. 12 S R2 P ORS T V A RE F V A GND ADC P1 Port Control P 1. 0 A I N0 P 1. 15 A I N15 V DDM V DDC POWER 2 2 V DDP VSS P ort s Figure 2-1 Data Sheet Pins for P/PG-TSSOP-38 Package 8 V 1.3, 2006-06 CIC751 CONFIDENTIAL General Device Information AIN4 1 38 AIN3 AIN5 2 37 AIN2 AIN10 3 36 AIN1 AIN11 4 35 AIN0 AIN8 5 34 VDDM AIN9 6 33 VDDP AIN6 7 32 VSS AIN7 8 31 PORST VAREF 9 30 SR2 VAGND 10 29 SR1 AIN12 11 28 SR0 AIN13 12 27 TESTMODE AIN14 13 26 MODE AIN15 14 25 RDATA/MTSR VSS 15 24 RVALID/SLS VDDC 16 23 RREADY/RDY TCLK/SR3 17 22 RCLK VDDP 18 21 TDATA/MRST TREADY/SR4 19 20 TVALID/SCLK CIC751 PAC KAGE_ 3 8 Figure 2-2 Data Sheet Pin Numbering for P/PG-TSSOP-38 Package 9 V 1.3, 2006-06 CIC751 CONFIDENTIAL 3 Functional Description Functional Description Figure 3-1 provides the block diagram of the CIC751 companion chip. This design allows access to the ADC by the host CPU without sacrificing any of the features of the ADC. This can be achieved because all registers of the ADC are mapped to the on-chip bus. This bus can be accessed via one of the two serial interfaces. Selection of the interface is made via pin MODE, which can be directly connected to the supply voltage or via pull-up/down resistors. The bus domain is completely separated from the address domain on the CPU chip. The addresses of all modules on the companion chip are 32-bit addresses. Transactions between the CPU and the SSC are executed with the SSC transmission protocol; transactions between the MLI and the CPU use the MLI transmission protocol. Each transaction via any of the two serial interfaces is defined by address, data, data width, and type of frame. The address from which data is read or written to, is related to the address domain. The data width may be 8, 16 or 32 bits for the MLI and 16 bits for the SSC. The ADC and the MLI may send request triggers to the DMA Controller. MLI ADC Slave Slave Master SSC Master PORTS Slave Bus Switch Master Slave Slave DMA SCU BL OC K_ D IAGR AM Figure 3-1 3.1 CIC751 Block Diagram Detailed Features The following sections provide detailed information about each of the on-chip modules. Data Sheet 10 V 1.3, 2006-06 CIC751 CONFIDENTIAL 3.1.1 Functional Description ADC The CIC751 provides an Analog/Digital Converter with 8-bit or 10-bit resolution and a sample & hold circuit on-chip. An input multiplexer selects between up to 16 analog input channels either via software (Fixed Channel Modes) or automatically (Auto Scan Modes). To fulfill most requirements of embedded control applications, the ADC supports the following conversion modes: • • Standard Conversions – Fixed Channel Single Conversion produces just one result from the selected channel – Fixed Channel Continuous Conversion repeatedly converts the selected channel – Auto Scan Single Conversion produces one result from each of a selected group of channels – Auto Scan Continuous Conversion repeatedly converts the selected group of channels – Wait for Read Mode start a conversion automatically when the previous result was read Channel Injection Mode can insert the conversion of a specific channel into a group conversion (auto scan) The key features of the ADC are: • • • • • • • • • • • Use of Successive Approximation Method Integrated sample and hold functionality Analog Input Voltage Range from 0V to 5V 16 Analog Input Channels 16 ADC result registers Resolution: 8-Bit or 10-Bit in Compatibility Mode Minimum Conversion Time:2.55 µs @ 10-Bit Total Unadjusted Error (TUE):±1 LSB @ 8-Bit, ± 2 LSB @10-Bit Support of several Conversion Modes Fixed Channel Single Conversion Fixed Channel Continuous Conversion Auto Scan Single Conversion Auto Scan Continuous Conversion Wait for Result Read and Start Next Conversion Channel Injection during Group Conversion Programmable Conversion and Sample Timing Scheme Automatic Self-Calibration to changing temperatures or process variations Data Sheet 11 V 1.3, 2006-06 CIC751 CONFIDENTIAL 3.1.2 Functional Description MLI The Micro Link Interface (MLI) is a fast synchronous serial interface that makes it possible to exchange data between microcontrollers or other devices. The key features of the MLI are: • • • • • • • • • Synchronous serial communication between an MLI transmitter and an MLI receiver Different system clock speeds are supported in the MLI transmitter and MLI receiver due to full handshake protocol (4 lines between a transmitter and a receiver) Fully transparent read/write access is supported (= remote programming) Complete address range of target device (Remote Controller) is available Specific frame protocol to transfer commands, addresses, and data Error detection by parity bit 32-bit, 16-bit, or 8-bit data transfers are supported Programmable baud rate: fMLI/2 (max.: fMLI = fSYS) Multiple receiving devices are supported 3.1.3 SSC The SSC supports full-duplex and half-duplex serial synchronous communication up to 10 Mbit/s (@ 40 MHz module clock). The serial clock signal is received from an external master (Slave Mode). Data width, shift direction, clock polarity, and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A shift clock generator provides the SSC with a separate serial clock signal. This section describes only the use of the SSC module as a slave because the CIC751 always operates as a slave to a host. Features • • • Slave Mode operation – Full-duplex or half-duplex operation – Automatic pad control possible Flexible data format – Programmable shift direction: LSB or MSB shift first – Programmable clock polarity: Idle low or idle high state for the shift clock – Programmable clock/data phase: Data shift with leading or trailing edge of the shift clock Internal Master Function – Access to the all addresses – Automatic address handling – Automatic data handling Data Sheet 12 V 1.3, 2006-06 CIC751 CONFIDENTIAL 4 Electrical Parameters Electrical Parameters The Electrical Specifications comprise parameters to ensure the product’s lifetime (Absolute Maximum Parameters) as well as parameters to describe the product’s operating conditions. 4.1 General Parameters Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Note: Table 4-2 and Table 4-3 are valid for port 0 only. Table 4-1 Absolute Maximum Ratings Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condit ion Storage temperature TST -65 – 150 °C – Voltage on VDDC pins with respect to ground (VSS) VDDC -0.5 – 3.25 V – Voltage on VDDP pins with respect to ground (VSS) VDDP -0.5 – 6.2 V – Voltage on any pin with respect to ground (VSS) VIN -0.5 – VDDP + 0.5 V – Input current on any pin during overload condition – -10 – 10 mA – Absolute sum of all input currents during overload condition – – – |100| mA – Junction temperature TJ -40 – 150 °C under bias Operating Conditions The following operating conditions must not be exceeded to ensure correct operation of the CIC751. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Data Sheet 13 V 1.3, 2006-06 CIC751 CONFIDENTIAL Electrical Parameters Table 4-2 Operating Condition Parameters Parameter Symbol Min. Typ. Max. Unit Note / Test Condit ion fSYS RCOSC output frequency fRCOSC – – 40 MHz – 8 9 10 MHz over all conditions Digital supply voltage for the core 2.25 – 2.75 V System frequency VDDC Values Active Mode, fSYS = fSYSmax1) Digital supply voltage for IO pads for 5 V Mode VDDP 4.5 5.0 5.5 V Active Mode2)3) Digital supply voltage for IO pads for 3.3 V Mode VDDP 3.13 3.3 3.47 V Active Mode4)5) Supply Voltage Difference ∆VDD for IO pads in 5.0 V Mode -0.5 – – V VDDP - VDDC6) Digital ground voltage VSS 0 – – V Reference voltage Overload current IOV -5 – 5 mA Per IO pin7)8) -2 – 5 mA Per analog input pin7)8) – – 1.0 × 10-4 – IOV > 0 – – 1.5 × 10-3 – IOV < 0 Overload current coupling KOVA factor for analog inputs9) Overload current coupling KOVD factor for digital I/O pins9) – – 5.0 × 10-3 – IOV > 0 – – 1.0 × 10-2 – IOV < 0 Absolute sum of overload currents Σ|IOV| – – 50 mA 8) External Load Capacitance CL – – 50 pF 1) fSYSmax = 40 MHz 2) External circuitry must guarantee low-level at the PORST pin at least until both power supply voltages have reached the operating range. 3) The specified voltage range is allowed for operation. The range limits may be reached under extreme operating conditions. However, specified parameters, such as leakage currents, refer to the standard operating voltage range of VDDP = 4.5 V to 5.5 V. 4) External circuitry must guarantee low-level at the PORST pin at least until both power supply voltages have reached the operating range. Data Sheet 14 V 1.3, 2006-06 CIC751 CONFIDENTIAL Electrical Parameters 5) The specified voltage range is allowed for operation. The range limits may be reached under extreme operating conditions. However, specified parameters, such as leakage currents, refer to the standard operating voltage range of VDDP = 4.5 V to 5.5 V. 6) This limitation must be fulfilled under all operating conditions including power-ramp-up and power-ramp-down. 7) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range: VOV > VDDP + 0.5 V (IOV > 0) or VOV < VSS - 0.5 V (IOV < 0). The absolute sum of input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified limits. Proper operation is not guaranteed if overload conditions occur on functional pins. 8) Not subject to production test - verified by design/characterization. 9) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error current adds to the respective pin’s leakage current (IOZ). The amount of error current depends on the overload current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse compared to the polarity of the overload current that produces it. The total current through a pin is |ITOT| = |IOZ| + (|IOV| × KOV). The additional error current may distort the input voltage on analog inputs. 4.2 DC Parameters The following chapter describes the DC parameters of the device. Table 4-3 DC Characteristics (Operating Conditions apply)1) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Input low voltage TTL VIL – – 0.3 × VDDP V 2) Input low voltage (Special Threshold) VILS – – 0.45 × VDDP V 3) Input high voltage TTL VIH 0.7 × VDDP – – V 2) Input high voltage (Special Threshold) VIHS 0.8 × VDDP – - 0.2 VDDP + 0.5 V 3) Input Hysteresis (Special Threshold) HYS 0.02 × VDDP – – V VDDP in [V], Series resistance = 0 Ω3) Output low voltage VOL – – 1.0 V IOL = 8 mA4) – – 0.45 V IOL = 2.5 mA4)5) VDDP - 1.0 – – V IOH = - 8 mA4) VDDP 0.45 – – V IOH = - 2.5 mA4)5) – – ±300 nA 0 V < VIN < VDDM, TA ≤ 125 °C Output high voltage6) VOH Input leakage current IOZ1 (Port 1)7) Data Sheet 15 V 1.3, 2006-06 CIC751 CONFIDENTIAL Table 4-3 Electrical Parameters DC Characteristics (Operating Conditions apply)1) (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Leakage current of pin VAREF (Idle Mode) IVAREFIM – – ±800 nA 0 V < VIN < VDDP, TA ≤ 125 °C Leakage current of pin VAREF (Active Mode) IVAREFAM – – ±20 + IVAREFIM µA 0 V < VIN < VDDP, TA ≤ 125 °C Input leakage current IOZ2 (Port 0)7) – – ±500 nA 0.45 V < VIN < VDDP Configuration pull-up ICPUH9) current8) ICPUL10) – – -5 µA VIN = VIHmin -100 – – µA VIN = VILmax -100 – – µA VOUT = 0.45 V – – 10 pF – Level active hold current ILHA11) CIO Pin capacitance12) digital inputs/outputs 1) Keeping signal levels within the limits specified in this table, ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current IOV. 2) This parameter is tested for PORST 3) This parameter is tested for P0. 4) The maximum deliverable output current of a port driver depends on the selected output driver mode, see Table 4-4, Current Limits for Port Output Drivers. The limit for pin groups must be respected. 5) As a rule, with decreasing output current the output levels approach the respective supply level (VOL → VSS, VOH → VDDP). However, only the levels for nominal output currents are guaranteed. 6) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 7) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to the definition of the overload coupling factor KOV. 8) This specification is valid during Reset for configuration on PORT0. 9) The maximum current may be drawn while the respective signal line remains inactive. 10) The minimum current must be drawn to drive the respective signal line active. 11) The minimum current must be drawn to drive the respective signal line active. 12) Only one point on the curve is tested in production. The rest of the curve is verified by design/characterization. Data Sheet 16 V 1.3, 2006-06 CIC751 CONFIDENTIAL Table 4-4 Electrical Parameters Current Limits for Port Output Drivers Port Output Driver Mode Maximum Output Current (IOLmax, -IOHmax)1) Nominal Output Current (IOLnom, -IOHnom) Strong driver2)3) 8 mA 2.5 mA 10 mA 2.5 mA Medium driver6) 4.0 mA 1.0 mA Weak driver6) 0.5 mA 0.1 mA Strong driver 4)5) 1) An output current above |IOXnom| may be drawn from up to three pins at the same time. For any group of 16 neighboring port output pins the total output current in each direction (ΣIOL and Σ-IOH) must remain below 50 mA. 2) For 3.3 V operation. 3) The strong driver is used for all pins beside pin 35 (AIN0) 4) For 5.0 V operation. 5) The strong driver is used for all pins beside pin 35 (AIN0) 6) The medium / weak driver is only used for pin 35 (AIN0) Table 4-5 Power Consumption CIC751 Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Power supply current (active) with all peripherals active IDDC – – 30 mA at 40 MHz system frequency Power supply current (active) with all peripherals active IDDC – – 18 mA at 20 MHz system frequency Pad I/O current IDDP – 4 – mA VDDM supply current IDDM – – 5 mA 4.3 Analog/Digital Converter Parameters The parameters of the ADC module are described below. Data Sheet 17 V 1.3, 2006-06 CIC751 CONFIDENTIAL Table 4-6 Electrical Parameters A/D Converter Characteristics (Operating Conditions apply) Parameter Min. Typ. Max. Unit Note / Test Condition VDDM 4.5 5.0 5.5 V 1) Analog reference supply VAREF 4.5 – VDDM + 0.1 V 2) Analog reference ground VAGND VSS - 0.1 – VSS + 0.1 V – Analog input voltage range VAIN VAGND – VAREF V 3) Basic clock frequency fBC 0.5 – 20 MHz 4) Conversion time for 10-bit result5) tC10P 52 × tBC + tS – + 6 × tSYS – – Post-calibr. on tC10 40 × tBC + tS – + 6 × tSYS – – Post-calibr. off tC8P 44 × tBC + tS – + 6 × tSYS – – Post-calibr. on tC8 32 × tBC + tS – + 6 × tSYS – – Post-calibr. off Calibration time after reset tCAL 484 – 11,696 tBC 6) Total unadjusted error TUE – – ±2 LSB 2) Total capacitance of an analog input CAINT – – 15 pF 7) Switched capacitance of an analog input CAINS – – 10 pF 7) Resistance of the analog input path RAIN – – 2 kΩ 7) Total capacitance of the reference input CAREFT – – 20 pF 7) Switched capacitance of the reference input CAREFS – – 15 pF 7) – – 1 kΩ 7) Analog supply voltage Conversion time for 8-bit result5) Symbol Resistance of RAREF the reference input path Data Sheet Values 18 V 1.3, 2006-06 CIC751 CONFIDENTIAL Electrical Parameters 1) The specified voltage range is allowed for operation. The range limits may be reached under extreme operating conditions. However, specified parameters, such as leakage currents, refer to the standard operating voltage range of VDDM = 4.5 V to 5.5 V. 2) TUE is tested at VAREF = VDDP + 0.1 V, VAGND = 0 V. It is verified by design for all other voltages within the defined voltage range. If the analog reference supply voltage drops below 4.5 V (i.e. VAREF ≥ 4.0 V) or exceeds the power supply voltage by up to 0.2 V (i.e. VAREF = VDDP + 0.2 V) the maximum TUE is increased to ±3 LSB. This range is not subject to production test. The specified TUE is guaranteed only, if the absolute sum of input overload currents on Port 1 pins (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the respective period of time. During the reset calibration sequence the maximum TUE may be ±4 LSB. 3) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. 4) The limit values for fBC must not be exceeded when selecting the peripheral frequency and the ADCTC setting. 5) This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result (tSYS = 1/fSYS). Values for the basic clock tBC depend on programming and can be taken from Table 4-7. When the post-calibration is switched off, the conversion time is reduced by 12 x tBC. 6) The actual duration of the reset calibration depends on the noise on the reference signal. Conversions executed during the reset calibration increase the calibration time. The TUE for those conversions may be increased. 7) Not subject to production test - verified by design/characterization. The given parameter values cover the complete operating range. Under relaxed operating conditions (temperature, supply voltage) reduced values can be used for calculations. At room temperature and nominal supply voltage the following typical values can be used: CAINTtyp = 12 pF, CAINStyp = 7 pF, RAINtyp = 1.5 kΩ, CAREFTtyp = 15 pF, CAREFStyp = 13 pF, RAREFtyp = 0.7 kΩ. RSource V AIN R AIN, On C AINT - C AINS C Ext A/D Converter CAINS MCS05570 Figure 4-1 Equivalent Circuitry for Analog Inputs Sample time and conversion time of the CIC751’s A/D Converter are programmable. In compatibility mode, the above timing can be calculated using Table 4-7. The limit values for fBC must not be exceeded when selecting ADCTC. Data Sheet 19 V 1.3, 2006-06 CIC751 CONFIDENTIAL Table 4-7 Electrical Parameters A/D Converter Computation Table1) ADCON.15|14 (ADCTC) A/D Converter Basic Clock fBC ADCON.13|12 (ADSTC) Sample Time 00 fSYS / 4 fSYS / 2 fSYS / 16 fSYS / 8 00 tBC × 8 01 tBC × 16 10 tBC × 32 11 tBC × 64 01 10 11 tS 1) These selections are available in compatibility mode. An improved mechanism to control the ADC input clock can be selected. Converter Timing Example = 40 MHz (i.e. tSYS = 25 ns), ADCTC = ‘01’, ADSTC = ‘00’ Basic clock fSYS fBC Sample time tS = tBC × 8 = 400 ns Assumptions: = fSYS / 2 = 20 MHz, i.e. tBC = 50 ns Conversion 10-bit: With post-calibr. tC10P = 52 × tBC + tS + 6 × tSYS = (2600 + 400 + 150) ns = 3.15 µs Post-calibr. off tC10 = 40 × tBC + tS + 6 × tSYS = (2000 + 400 + 150) ns = 2.55 µs With post-calibr. tC8P = 44 × tBC + tS + 6 × tSYS = (2200 + 400 + 150) ns = 2.75 µs Post-calibr. off = 32 × tBC + tS + 6 × tSYS = (1600 + 400 + 150) ns = 2.15 µs Conversion 8-bit: Data Sheet tC8 20 V 1.3, 2006-06 CIC751 CONFIDENTIAL 4.4 Electrical Parameters AC Characteristics The internal operation and consequently the timings of the CIC751 are based on the internal system clock fSYS. 4.4.1 Definition of Internal Timing The system clock signal fSYS can be generated from the oscillator clock signal fOSC or from the clock applied to the RCLK pin via different mechanisms. The duration of system clock periods and their variation (and also the derived external timing) depend on the used mechanism to generate fSYS. This influence must be regarded when calculating the timings for the CIC751. The used mechanism to generate the system clock is selected by register PLLCON. 4.4.1.1 Prescaler Mode When Prescaler Mode is configured (SCU_PLLCON.PLLCTRL = 01B) the system clock is derived from the internal oscillator through the P- and K-dividers: fSYS = fOSC / ((SCU_PLLCON.PDIV+1)×(SCU_PLLCON.KDIV+1)). If both divider factors are selected as ’1’ (SCU_PLLCON.PDIV = SCU_PLLCON.KDIV = ’0’) the frequency of fSYS directly follows the frequency of fOSC so the high and low time of fSYS is defined by the duty cycle of the input clock fOSC. The lowest system clock frequency is achieved by selecting the maximum values for both divider factors: fSYS = fOSC / ((3+1)×(14+1)) = fOSC / 60. 4.4.1.2 Phase Locked Loop (PLL) When PLL operation is configured (SCU_PLLCON.PLLCTRL = 11B) the on-chip phase locked loop is enabled and provides the system clock. The PLL multiplies the input frequency by the factor F (fSYS = fOSC × F) which results from the input divider, the multiplication factor, and the output divider (F = SCU_PLLCON.NDIV+1 / (SCU_PLLCON.PDIV+1 × SCU_PLLCON.KDIV+1)). The PLL circuit synchronizes the system clock to the input clock. This synchronization is done smoothly, i.e. the system clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fSYS is constantly adjusted so it is locked to fOSC. The slight variation causes a jitter of fSYS which also affects the duration of individual TCMs. The actual minimum value for TCM depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency the relative deviation for periods of more than one TCM is lower than for one single TCM (see formula and Figure 4-2). Data Sheet 21 V 1.3, 2006-06 CIC751 CONFIDENTIAL Electrical Parameters This is especially important for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. The value of the accumulated PLL jitter depends on the number of consecutive VCO output cycles within the respective time frame. The VCO output clock is divided by the output prescaler (K = SCU_PLLCON.KDIV+1) to generate the system clock signal fSYS. Therefore, the number of VCO cycles can be represented as K × N, where N is the number of consecutive fSYS cycles (TCM). For a period of NN × TCM the accumulated PLL jitter is defined by the deviation D: DN [ns] = ±(1.5 + 6.32 × N / fSYS); fSYS in [MHz], N = number of consecutive TCMs. So, for a period of 3 TCMs @ 20 MHz and K = 12: D3 = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns. This formula is applicable for K × N < 95. For longer periods the K×N=95 value can be used. This steady value can be approximated by: DNmax [ns] = ±(1.5 + 600 / (K × fSYS)). A cc. jitter D N ns K =15 K =12 K =1 0 K =8 K =6 K =5 ±8 ±7 ±6 M Hz ±5 10 ±4 ±3 ±2 z MH 0 2 Hz 40 M ±1 0 1 5 15 10 20 25 N m cb 04 4 13 _x c .vs d Figure 4-2 Approximated Accumulated PLL Jitter Note: The bold lines indicate the minimum accumulated jitter which can be achieved by selecting the maximum possible output prescaler factor K. Different frequency bands can be selected for the VCO, so the operation of the PLL can be adjusted to a wide range of input and output frequencies: Data Sheet 22 V 1.3, 2006-06 CIC751 CONFIDENTIAL Table 4-8 Electrical Parameters VCO Bands for PLL Operation1) PLLCON.PLLVB VCO Frequency Range Base Frequency Range 00 100 … 150 MHz 20 … 80 MHz 01 150 … 200 MHz 40 … 130 MHz 10 200 … 250 MHz 60 … 180 MHz 11 Reserved 1) Not subject to production test - verified by design/characterization. 4.4.2 Testing Waveforms of the digital input/output signals The relation between a real and the ideal digital waveform, together with the characteristically measurement levels is shown below. Input signal (driven by tester) Output signal (measured) 2.0 V 0.8 V 0.45 V Figure 4-3 Input Output Waveforms The figure below shows the transition between an actively driven digital output level and three-state (input state). Data Sheet 23 V 1.3, 2006-06 CIC751 CONFIDENTIAL Electrical Parameters VLoad + 0.1 V VOH - 0.1 V Timing Reference Points VLoad - 0.1 V VOL + 0.1 V For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH / VOL level occurs (I OH / I OL = 20 mA). MCA00763 Figure 4-4 4.4.3 Float Waveforms Output Rise and Fall Times The Output Rise/Fall time of a GPIO is tr = tf = 14ns, at CL = 50pF. Data Sheet 24 V 1.3, 2006-06 CIC751 CONFIDENTIAL 4.4.4 Electrical Parameters Power Sequencing The CIC751 device needs two power supply voltages: digital ports power supply voltage VDDP, analog supply voltage VDDM. The digital core supply voltage VDDC is derived from VDDP by embedded voltage regulator of the CIC751. The following section defines the time and voltage constraints and relations between these two power supplies that have to be satisfied at power up and power down of the device. Figure 4-5 describes the requirements that the external power supplies VDDP, and VDDM must satisfy in order to provide the correct operation of the device. The following rules should be applied in order to guarantee a stable power-up behavior: • • The active PORST should not be released before VDDP reached 2.7 V At any time it is not allowed that VDDM > VDDP if VDDP < 2.1 V. The second rule can be violated (without operation lifetime reduction) if instead the following conditions are not violated: • • The external resistor on the Analog Inputs AIN0 to AIN15 has to be equal or greater than 2 KΩ The accumulated time the second rule is violated is less than 4 % of the total product operation lifetime. Voltage VDDP (3.3V or 5V) VDDM (5V) 2.7V 2.1V Time Ramp-up Time PORST Time 300µs Reset Time PowerSeq Figure 4-5 Data Sheet Power-up Sequence 25 V 1.3, 2006-06 CIC751 CONFIDENTIAL Table 4-9 Electrical Parameters Ramp-up Times Case Time Ramp-up after a power-on event max. 500 µs Ramp-up after a reset event max. 450 µs Data Sheet 26 V 1.3, 2006-06 CIC751 CONFIDENTIAL 4.4.5 Electrical Parameters Timing Parameters Peripheral timing parameters are not subject to production test. They are verified by design/characterization. 4.4.5.1 Micro Link Interface (MLI) Timing The timing of the MLI handshake signals refer to the system clock frequency fSYS. This frequency is the base for the generation of the MLI baud rate fTCLK. Table 4-10 MLI Timing (VSS = 0 V; fMLI <= 40MHz VDDP = 3.13 to 3.47 V; TA = -40 °C to +125 °C; CL = 50 pF) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Con dition tSYS = 1 / fSYS TCLK clock period t10 2 * tSYS – – ns TCLK high period t11 20% 50% 80% t10 TCLK low period t12 20% 50% 80% t10 TCLK rise time t13 – – 35% t10 TCLK fall time t14 – – 35% t10 TDATA and TVALID setup time t20 to TCLK raising edge – – 10% t10 TDATA and TVALID hold time to TCLK raising edge t21 – – 10% t10 TREADY setup time to TCLK raising edge1) t30 10% – – t10 TREADY hold time to TCLK raising edge 2) t31 10% – – t10 RCLK clock period t40 <2* tSYS – – ns RCLK high period t41 20% 50% 80% t40 RCLK low period t42 20% 50% 80% t40 RCLK rise time t43 – – 35% t40 RCLK fall time t44 – – 35% t40 RDATA and RVALID setup time to RCLK falling edge t50 10% – – t40 Data Sheet 27 tSYS = 1 / fSYS V 1.3, 2006-06 CIC751 CONFIDENTIAL Table 4-10 Electrical Parameters MLI Timing (VSS = 0 V; fMLI <= 40MHz VDDP = 3.13 to 3.47 V; TA = -40 °C to +125 °C; CL = 50 pF) Parameter Symbol Values Unit Min. Typ. Max. RDATA and RVALID hold time t51 to RCLK falling edge 10% – – t40 RREADY setup time to RCLK falling edge 3) t60 50% – – t40 RREADY hold time to RCLK falling edge 4) t61 – – 50% t40 Note / Test Con dition 1) Referring to the TCLK edge when TVALID becomes 0 and the TCLK edge when the ready delay time elapses. 2) Referring to the TCLK edge when TVALID becomes 0 and the TCLK edge when the ready delay time elapses. 3) Referring to the former value at the RCLK edge when RVALID changes. 4) Referring to the new value at the RCLK edge when RVALID changes. Data Sheet 28 V 1.3, 2006-06 CIC751 CONFIDENTIAL Electrical Parameters t10 t13 t11 t14 t12 0.9 VDDP 0.1 VDDP TCLK t20 t21 TDATA TVALIDx t30 t31 TREADYx t40 t43 t41 t44 t42 RCLKx t50 t51 t60 t61 0.9 VDDP 0.1 VDDP RDATAx RVALIDx RREADYx MLI_timing Figure 4-6 Data Sheet MLI Timing 29 V 1.3, 2006-06 CIC751 CONFIDENTIAL 4.4.6 Electrical Parameters Synchronous Serial Channel (SSC) Slave Mode Timing The timing of the Synchronous Serial Channel in slave mode is defined below. Table 4-11 SSC Timing (VSS = 0 V; fSSC <= 40MHz VDDP = 3.13 to 3.47 V (Class A); TA = -40 °C to +125 °C; CL = 50 pF) Parameter Sy mb ol Min. t20 TSSC – ns 4 12 ns – 14 ns 0 – ns MTSR hold from SCLK t23 Rising/Falling Edge SR from SCLK RE (CON.PO,CON.PH = 00) from SCLK FE (CON.PO,CON.PH = 10) 2 + TSSC – ns t24 SLSI lead delay from SCLK Rising/Falling Edge SR from SCLK RE (CON.PO,CON.PH = 00) from SCLK FE (CON.PO,CON.PH =10) 6 – ns 13 15 ns 4 – ns SCLK clock period Values Typ. Max. Unit Note / Test Co ndition CC t21 MRST delay from SCLK CC Rising/Falling Edge from SCLK RE (CON.PO,CON.PH = 00) from SCLK FE (CON.PO,CON.PH = 10) MRST hold from SLS Rising Edge t26 CC MTSR setup to SCLK Rising/Falling Edge to SCLK RE (CON.PO,CON.PH = 00) to SCLK FE (CON.PO,CON.PH = 10) RDY lead delay to SLS RE t22 SR t25 1) CC SLS hold from RDY RE t27 SR 1) This is only valid if SSC move engine is idle (RDY = 1). Data Sheet 30 V 1.3, 2006-06 CIC751 CONFIDENTIAL Electrical Parameters t20 0.9 VDD SCLK 0.1 VDD (CON.PO, CON.PH = 00) 0.9 VDD SCLK (CON.PO, CON.PH = 10) t21 t26 t21 MRST First Data t22 t23 Data valid MTSR t24 0.1 VDD Last Data t22 t23 Data valid t27 SLS t25 RDY SSC_TMG_SLAVE_MOONGOOSE Figure 4-7 Data Sheet SSC Slave Mode Timing 31 V 1.3, 2006-06 CIC751 CONFIDENTIAL 4.5 Electrical Parameters Package and Reliability This chapter defines the parameters related to the Package and Reliability of the device. 4.5.1 Packaging The parameters of the package of the CIC751 are defined below. Table 4-12 Package Parameters (P/PG-TSSOP-38) Parameter Symbol Power dissipation Thermal resistance 4.5.2 PDISS RTHJA Limit Values Unit Notes Min. Max. – tbd. W – – 59 K/W Chip-Ambient Package Outlines The physical characteristics of the package are described below. Figure 4-8 Data Sheet Package Outlines for P/PG-TSSOP-38 32 V 1.3, 2006-06 CIC751 CONFIDENTIAL 4.5.3 Electrical Parameters Quality Declarations The following chapter defines some quality parameters of CIC751. Table 4-13 Quality Parameters Parameter Symbol Limit Values Unit Notes Min. Max. – 18000 hours at average weighted junction temperature TJ = 116°C (ambient temperature TA = 102°C) – 240001) hours at average weighted junction temperature TJ = 106°C (ambient temperature TA = 92°C) tB VHBM 20 – years – 2000 V Conforming to EIA/JESD22-A114-B ESD susceptibility according to Socketed Device Model (SDM) VSDM – 500 V Conforming to ESDA Std DS5.3-1993 Moisture Sensitivity Level (MSL) – – 3 – Conforming to Jedec J-STD-020C for 240°C Operation Lifetime Life Expectancy ESD susceptibility according to Human Body Model (HBM) tOP 1) One example of a detailed temperature profile is: 1200 hours at TJ = 140 °C (TA = 125 °C) 3600 hours at TJ = 115 °C (TA = 100 °C) 7200 hours at TJ = 100 °C (TA = 85 °C) 12000 hours at TJ = 90 °C (TA = 75 °C) Note: Information about soldering can be found on the “package” information page under: http://www.infineon.com/products. Data Sheet 33 V 1.3, 2006-06 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG