C164CI - 3V Low Power Data Sheet

Da ta S heet, V1.0, Jan. 2003
C164CI-3V
Low Power
1 6 -B i t S i n g l e - C h i p M ic r o co n t ro l l e r
Preliminary
M i c r o c o n t ro l le r s
N e v e r
s t o p
t h i n k i n g .
Edition 2003-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
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ar
C164CI-3V
Low Power
y
Da ta S heet, V1.0, Jan. 2003
P
re
li
m
Preliminary
in
1 6 -B i t S i n g l e - C h i p M ic r o co n t ro l l e r
M i c r o c o n t ro l le r s
N e v e r
s t o p
t h i n k i n g .
C164CI-3V
Preliminary
Revision History:
2003-01
Previous Version:
---
Page
V1.0
Subjects (major changes since last revision)
Controller Area Network (CAN): License of Robert Bosch GmbH
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Preliminary
16-Bit Single-Chip Microcontroller
C166 Family
C164CI-3V
C164CI/SI, C164CL/SL
• High Performance 16-bit CPU with 4-Stage Pipeline
– 125 ns Instruction Cycle Time at 16 MHz CPU Clock
– 625 ns Multiplication (16 × 16 bit), 1250 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 32 Sources, Sample-Rate down to 62 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input
• On-Chip Memory Modules
– 2 Kbytes On-Chip Internal RAM (IRAM)
– 2 Kbytes On-Chip Extension RAM (XRAM)
– up to 64 Kbytes On-Chip Program Mask ROM
• On-Chip Peripheral Modules
– 8-Channel 10-bit A/D Converter with Programmable Conversion Time
down to 7.8 µs
– 8-Channel General Purpose Capture/Compare Unit (CAPCOM2)
– Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)
(3/6 Capture/Compare Channels and 1 Compare Channel)
– Multi-Functional General Purpose Timer Unit with 3 Timers
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
– On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects
(Full CAN/Basic CAN)
– On-Chip Real Time Clock
• Up to 4 Mbytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Four Optional Programmable Chip-Select Signals
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 59 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
Data Sheet
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C164CI-L16M3V
Low Power
Preliminary
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 80-Pin MQFP Package, 0.65 mm pitch
This document describes several derivatives of the C164 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
Table 1
C164CI-3V Derivative Synopsis
Derivative1)
Program
Memory
SAK-C164CI-8R16M3V
SAF-C164CI-8R16M3V
CAN Interf.
Operating
Frequency
64 Kbytes ROM Full function
CAN1
16 MHz
SAK-C164SI-8R16M3V
SAF-C164SI-8R16M3V
64 Kbytes ROM Full function
---
16 MHz
SAK-C164CL-8R16M3V
SAF-C164CL-8R16M3V
64 Kbytes ROM Reduced fct. CAN1
16 MHz
SAK-C164SL-8R16M3V
SAF-C164SL-8R16M3V
64 Kbytes ROM Reduced fct. ---
16 MHz
SAK-C164CL-6R16M3V
SAF-C164CL-6R16M3V
48 Kbytes ROM Reduced fct. CAN1
16 MHz
SAK-C164SL-6R16M3V
SAF-C164SL-6R16M3V
48 Kbytes ROM Reduced fct. ---
16 MHz
SAK-C164CI-L16M3V
SAF-C164CI-L16M3V
---
16 MHz
1)
CAPCOM6
Full function
CAN1
This Data Sheet is valid for ROM(less) devices starting with and including design step AB, and for OTP devices
starting with and including design step DA.
For simplicity all versions are referred to by the term C164CI-3V throughout this
document.
Data Sheet
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Low Power
Preliminary
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• the derivative itself, i.e. its function set, the temperature range, and the supply voltage
• the package and the type of delivery.
For the available ordering codes for the C164CI-3V please refer to the “Product
Catalog Microcontrollers”, which summarizes all available microcontroller variants.
Note: The ordering codes for Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Introduction
The C164CI-3V derivatives of the Infineon C166 Family of full featured single-chip
CMOS microcontrollers are especially suited for cost sensitive applications. They
combine high CPU performance (up to 8 million instructions per second) with high
peripheral functionality and enhanced IO-capabilities. They also provide clock
generation via PLL and various on-chip memory modules such as program ROM or
OTP, internal RAM, and extension RAM.
VAREF VAGND VDD
Port 0
16 Bit
XTAL1
XTAL2
Port 1
16 Bit
RSTIN
RSTOUT
VSS
C164CI-3V
Port 3
9 Bit
NMI
Port 4
6 Bit
EA
ALE
Port 8
4 Bit
RD
Port 5
8 Bit
WR/WRL
MCL04869
Figure 1
Data Sheet
Logic Symbol
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Preliminary
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VAGND
P5.3/AN3
P5.2/AN2
P5.1/AN1
P5.0/AN0
P8.3/CC19IO/*
P8.2/CC18IO/*
P8.1/CC17IO/*
P8.0/CC16IO/*
NMI
RSTOUT
RSTIN
P1H.7/A15/CC27IO
P1H.6/A14/CC26IO
P1H.5/A13/CC25IO
P1H.4/A12/CC24IO
P1H.3/A11/EXIN/T7IN
P1H.2/A10/CC6POS2/EX2IN
P1H.1/A9/CC6POS1/EX1IN
VDD
Pin Configuration
(top view)
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
C164CI-3V
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P4.3/A19/CS0
*/P4.5/A20
*/P4.6/A21
RD
WR/WRL
ALE
Vpp/EA
P0L.0/AD0
P0L.1/AD1
P0L.2/AD2
P0L.3/AD3
P0L.4/AD4
P0L.5/AD5
P0L.6/AD6
P0L.7/AD7
P0H.0/AD8
P0H.1/AD9
P0H.2/AD10
VDD
VAREF
P5.4/AN4/T2EUD
P5.5/AN5/T4EUD
P5.6/AN6/T2IN
P5.7/AN7/T4IN
VSS
VDD
P3.4/T3EUD
P3.6/T3IN
P3.8/MRST
P3.9/MTSR
P3.10/TxD0
P3.11/RxD0
P3.12/BHE/WRH
P3.13/SCLK
P3.15/CLKOUT/FOUT
P4.0/A16/CS3
P4.1/A17/CS2
P4.2/A18/CS1
VSS
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VSS
P1H.0/A8/CC6POS0/EX0IN
P1L.7/A7/CTRAP
P1L.6/A6/COUT63
VSS
XTAL1
XTAL2
VDD
P1L.5/A5/COUT62
P1L.4/A4/CC62
P1L.3/A3/COUT61
P1L.2/A2/CC61
P1L.1/A1/COUT60
P1L.0/A0/CC60
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
VSS
MCP04870
Figure 2
*) The marked pins of Port 4 and Port 8 can have CAN interface lines assigned to them.
Table 2 on the pages below lists the possible assignments.
The marked input signals are available only in devices with a full-function CAPCOM6.
They are not available in devices with a reduced-function CAPCOM6.
Data Sheet
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Low Power
Preliminary
Table 2
Pin Definitions and Functions
Symbol Pin
No.
Input
Outp.
Function
P5
I
Port 5 is an 8-bit input-only port with Schmitt-Trigger charact.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
AN0
AN1
AN2
AN3
AN4,
T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.
AN5,
T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
AN6,
T2IN
GPT1 Timer T2 Input for
Count/Gate/Reload/Capture
AN7,
T4IN
GPT1 Timer T4 Input for
Count/Gate/Reload/Capture
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
76
77
78
79
2
3
4
I
I
I
I
I
I
I
P5.7
5
I
IO
P3
P3.4
P3.6
P3.8
P3.9
P3.10
P3.11
P3.12
8
9
10
11
12
13
14
P3.13
P3.15
15
16
Data Sheet
I
I
I/O
I/O
O
I/O
O
O
I/O
O
O
Port 3 is a 9-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 3 is
selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
T3EUD
GPT1 Timer T3 External Up/Down Control Input
T3IN
GPT1 Timer T3 Count/Gate Input
MRST
SSC Master-Receive/Slave-Transmit Inp./Outp.
MTSR
SSC Master-Transmit/Slave-Receive Outp./Inp.
TxD0
ASC0 Clock/Data Output (Async./Sync.)
RxD0
ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
External Memory High Byte Enable Signal,
BHE
WRH
External Memory High Byte Write Strobe
SCLK
SSC Master Clock Output / Slave Clock Input.
CLKOUT System Clock Output (= CPU Clock),
FOUT
Programmable Frequency Output
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Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input
Outp.
Function
P4
IO
Port 4 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 4 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 4 is
selectable (TTL or special).
Port 4 can be used to output the segment address lines, the
optional chip select lines, and for serial interface lines:1)
A16
Least Significant Segment Address Line,
CS3
Chip Select 3 Output
A17
Segment Address Line,
CS2
Chip Select 2 Output
A18
Segment Address Line,
CS1
Chip Select 1 Output
A19
Segment Address Line,
Chip Select 0 Output
CS0
A20
Segment Address Line,
CAN1_RxD CAN 1 Receive Data Input
A21
Most Significant Segment Address Line,
CAN1_TxD CAN 1 Transmit Data Output
O
O
O
O
O
O
O
O
O
I
O
O
P4.0
17
P4.1
18
P4.2
19
P4.3
22
P4.5
23
P4.6
24
RD
25
O
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
WR/
WRL
26
O
External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.
ALE
27
O
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
Data Sheet
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Preliminary
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input
Outp.
Function
EA
I
External Access Enable pin.
A low level at this pin during and after Reset forces the
C164CI-3V to latch the configuration from PORT0 and pin
RD, and to begin instruction execution out of external
memory.
A high level forces the C164CI-3V to latch the configuration
from pins RD and ALE, and to begin instruction execution out
of the internal program memory.
“ROMless” versions must have this pin tied to ‘0’.
28
PORT0
IO
P0L.0-7 2936
P0H.0-7 37-39,
42-46
Data Sheet
PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.
Demultiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
D0 – D7
D0 – D7
P0H.0 – P0H.7:
I/O
D8 – D15
Multiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
AD0 – AD7 AD0 – AD7
P0H.0 – P0H.7:
A8 – A15
AD8 – AD15
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Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input
Outp.
IO
PORT1
P1L.0-7 47-52,
57-59
P1H.0-7 59,
62-68
P1L.0
P1L.1
P1L.2
P1L.3
P1L.4
P1L.5
P1L.6
P1L.7
47
48
49
50
51
52
57
58
I/O
O
I/O
O
I/O
O
O
I
P1H.0
59
P1H.1
62
P1H.2
63
P1H.3
64
I
I
I
I
I
I
I
P1H.4
P1H.5
P1H.6
P1H.7
65
66
67
68
I/O
I/O
I/O
I/O
Function
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the
16-bit address bus (A) in demultiplexed bus modes and also
after switching from a demultiplexed bus mode to a
multiplexed bus mode.
The following PORT1 pins also serve for alt. functions:
CC60
CAPCOM6: Input / Output of Channel 0
COUT60 CAPCOM6: Output of Channel 0
CC61
CAPCOM6: Input / Output of Channel 1
COUT61 CAPCOM6: Output of Channel 1
CC62
CAPCOM6: Input / Output of Channel 2
COUT62 CAPCOM6: Output of Channel 2
COUT63 Output of 10-bit Compare Channel
CAPCOM6: Trap Input
CTRAP
CTRAP is an input pin with an internal pullup resistor. A low
level on this pin switches the compare outputs of the
CAPCOM6 unit to the logic level defined by software.
CC6POS0 CAPCOM6: Position 0 Input, **)
EX0IN
Fast External Interrupt 0 Input
CC6POS1 CAPCOM6: Position 1 Input, **)
EX1IN
Fast External Interrupt 1 Input
CC6POS2 CAPCOM6: Position 2 Input, **)
EX2IN
Fast External Interrupt 2 Input
EX3IN
Fast External Interrupt 3 Input,
T7IN
CAPCOM2: Timer T7 Count Input
CC24IO
CAPCOM2: CC24 Capture Inp./Compare Outp.
CC25IO
CAPCOM2: CC25 Capture Inp./Compare Outp.
CC26IO
CAPCOM2: CC26 Capture Inp./Compare Outp.
CC27IO
CAPCOM2: CC27 Capture Inp./Compare Outp.
Note: The marked (**) input signals are available only in
devices with a full function CAPCOM6.
Data Sheet
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Preliminary
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input
Outp.
Function
XTAL2
XTAL1
54
55
O
I
XTAL2:
XTAL1:
RSTIN
69
I/O
Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the C164CI3V. An internal pullup resistor permits power-on reset using
only a capacitor connected to VSS.
A spike filter suppresses input pulses <10 ns. Input pulses
>100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN line is internally pulled low
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.
RST
OUT
70
O
Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
NMI
71
I
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C164CI-3V to go into
power down mode. If NMI is high, when PWRDN is
executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
Data Sheet
Output of the oscillator amplifier circuit.
Input to the oscillator amplifier and input to
the internal clock generator
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.
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Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input
Outp.
Function
P8
IO
I/O
I
I/O
O
I/O
I
I/O
O
Port 8 is a 4-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 8 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 8 is
selectable (TTL or special). Port 8 pins provide inputs/
outputs for CAPCOM2 and serial interface lines.1)
CC16IO
CAPCOM2: CC16 Capture Inp./Compare Outp.,
CAN1_RxD CAN 1 Receive Data Input
CC17IO
CAPCOM2: CC17 Capture Inp./Compare Outp.,
CAN1_TxD CAN 1 Transmit Data Output
CC18IO
CAPCOM2: CC18 Capture Inp./Compare Outp.,
CAN1_RxD CAN 1 Receive Data Input
CC19IO
CAPCOM2: CC19 Capture Inp./Compare Outp.,
CAN1_TxD CAN 1 Transmit Data Output
P8.0
72
P8.1
73
P8.2
74
P8.3
75
VAREF
VAGND
VDD
1
–
Reference voltage for the A/D converter.
80
–
Reference ground for the A/D converter.
7, 21, –
40, 53,
61
Digital Supply Voltage:
+3.3 V during normal operation and idle mode.
≥2.5 V during power down mode.
VSS
6, 20, –
41, 56,
60
Digital Ground.
1)
The CAN interface lines are assigned to ports P4 and P8 under software control. Within the CAN module
several assignments can be selected.
Note: The following behavioural differences must be observed when the bidirectional
reset is active:
• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatically after a reset.
• The reset indication flags always indicate a long hardware reset.
• The PORT0 configuration is treated as if it were a hardware reset. In particular, the
bootstrap loader may be activated when P0L.4 is low.
• Pin RSTIN may only be connected to external reset devices with an open drain output
driver.
• A short hardware reset is extended to the duration of the internal reset sequence.
Data Sheet
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Preliminary
Functional Description
The architecture of the C164CI-3V combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C164CI-3V.
Note: All time specifications refer to a CPU clock of 16 MHz
(see definition in the AC Characteristics section).
C166-Core
16
Data
ROM: 48/64
OTP: 64
KByte
32
16
CPU
Instr. / Data
Data
16
IRAM
Dual Port
ProgMem
Internal
RAM
2 KByte
Osc / PLL
XRAM
PEC
XTAL
External Instr. / Data
2 KByte
Interrupt Controller 16-Level
Priority
RTC
WDT
Rev 2.0B active
6
Port 4
EBC
Interrupt Bus
Peripheral Data Bus
16
ADC
ASC0
SSC
10-Bit
8
Channels
(USART)
(SPI)
16
CCOM2 CCOM6
T2
T7
T12
T3
T8
T13
T4
XBUS Control
External Bus
Control
Port 0
GPT1
BRGen
Port 1
CAN
On-Chip XBUS (16-Bit Demux)
16
BRGen
Port 5
8
Port 3
Port 8
9
4
16
MCB04323_4ci
Figure 3
Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resoures, the X-Peripherals (see Figure 3).
The XBUS resources (XRAM, CAN) of the C164CI-3V can be enabled or disabled during
initialization by setting the general X-Peripheral enable bit XPEN (SYSCON.2). Modules
that are disabled consume neither address space nor port pins.
Data Sheet
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Preliminary
Memory Organization
The memory space of the C164CI-3V is configured in a Von Neumann architecture
which means that code memory, data memory, registers and I/O ports are organized
within the same linear address space which includes 16 Mbytes. The entire memory
space can be accessed bytewise or wordwise. Particular portions of the on-chip memory
have additionally been made directly bitaddressable.
The C164CI-3V incorporates 64/48 Kbytes of on-chip mask-programmable ROM (not in
the ROM-less derivative, of course) for code or constant data. The lower 32 Kbytes of
the on-chip ROM can be mapped either to segment 0 or segment 1.
2 Kbytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.
2 Kbytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks,
or code. The XRAM is accessed like external memory and therefore cannot be used for
the system stack or for register banks and is not bitaddressable. The XRAM permits 16bit accesses with maximum speed.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 4 Mbytes of external RAM and/or ROM can be connected to the
microcontroller.
Data Sheet
12
V1.0, 2003-01
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Low Power
Preliminary
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which are
as follows:
–
–
–
–
16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed
16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed
16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed
16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/
output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses
and data use PORT0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which control the access to different resources with different
bus characteristics. These address windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to
locations not covered by these 4 address windows are controlled by BUSCON0.
Up to 4 external CS signals (3 windows plus default) can be generated in order to save
external glue logic. The C164CI-3V offers the possibility to switch the CS outputs to an
unlatched mode. In this mode the internal filter logic is switched off and the CS signals
are directly generated from the address. The unlatched CS mode is enabled by setting
CSCFG (SYSCON.6).
For applications which require less than 4 Mbytes of external memory space, this
address space can be restricted to 1 Mbyte, 256 Kbyte, or to 64 Kbyte. In this case
Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if an
address space of 4 Mbytes is used.
Note: When the on-chip CAN Module is used with the interface lines assigned to Port 4,
the CAN lines override the segment address lines and the segment address
output on Port 4 is therefore limited to 4 bits i.e. address lines A19 … A16.
Data Sheet
13
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C164CI-3V’s instructions can be
executed in just one machine cycle which requires 2 CPU clocks (4 TCL). For example,
shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 × 16
bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline
optimization, the so-called ‘Jump Cache’, reduces the execution time of repeatedly
performed jumps in a loop from 2 cycles to 1 cycle.
Figure 4
Data Sheet
CPU Block Diagram
14
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Low Power
Preliminary
The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.
A system stack of up to 1024 words is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient C164CI-3V instruction set which
includes the following instruction classes:
–
–
–
–
–
–
–
–
–
–
–
–
Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet
15
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Preliminary
Interrupt System
With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of
internal program execution), the C164CI-3V is capable of reacting very fast to the
occurrence of non-deterministic events.
The architecture of the C164CI-3V supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicity decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The C164CI-3V has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related register, each source can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table 3 shows all of the possible C164CI-3V interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not used by associated peripherals, may be used to
generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).
Data Sheet
16
V1.0, 2003-01
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Preliminary
Table 3
C164CI-3V Interrupt Nodes
Source of Interrupt or Request
PEC Service Request Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
Fast External Interrupt 0 CC8IR
CC8IE
CC8INT
00’0060H
18H
Fast External Interrupt 1 CC9IR
CC9IE
CC9INT
00’0064H
19H
Fast External Interrupt 2 CC10IR
CC10IE
CC10INT
00’0068H
1AH
Fast External Interrupt 3 CC11IR
CC11IE
CC11INT
00’006CH
1BH
GPT1 Timer 2
T2IR
T2IE
T2INT
00’0088H
22H
GPT1 Timer 3
T3IR
T3IE
T3INT
00’008CH
23H
GPT1 Timer 4
T4IR
T4IE
T4INT
00’0090H
24H
A/D Conversion
Complete
ADCIR
ADCIE
ADCINT
00’00A0H
28H
A/D Overrun Error
ADEIR
ADEIE
ADEINT
00’00A4H
29H
ASC0 Transmit
S0TIR
S0TIE
S0TINT
00’00A8H
2AH
ASC0 Transmit Buffer
S0TBIR
S0TBIE
S0TBINT
00’011CH
47H
ASC0 Receive
S0RIR
S0RIE
S0RINT
00’00ACH
2BH
ASC0 Error
S0EIR
S0EIE
S0EINT
00’00B0H
2CH
SSC Transmit
SCTIR
SCTIE
SCTINT
00’00B4H
2DH
SSC Receive
SCRIR
SCRIE
SCRINT
00’00B8H
2EH
SSC Error
SCEIR
SCEIE
SCEINT
00’00BCH
2FH
CAPCOM Register 16
CC16IR
CC16IE
CC16INT
00’00C0H
30H
CAPCOM Register 17
CC17IR
CC17IE
CC17INT
00’00C4H
31H
CAPCOM Register 18
CC18IR
CC18IE
CC18INT
00’00C8H
32H
CAPCOM Register 19
CC19IR
CC19IE
CC19INT
00’00CCH
33H
CAPCOM Register 24
CC24IR
CC24IE
CC24INT
00’00E0H
38H
CAPCOM Register 25
CC25IR
CC25IE
CC25INT
00’00E4H
39H
CAPCOM Register 26
CC26IR
CC26IE
CC26INT
00’00E8H
3AH
CAPCOM Register 27
CC27IR
CC27IE
CC27INT
00’00ECH
3BH
CAPCOM Timer 7
T7IR
T7IE
T7INT
00’00F4H
3DH
CAPCOM Timer 8
T8IR
T8IE
T8INT
00’00F8H
3EH
CAPCOM6 Interrupt
CC6IR
CC6IE
CC6INT
00’00FCH
3FH
CAN Interface 1
XP0IR
XP0IE
XP0INT
00’0100H
40H
PLL/OWD and RTC
XP3IR
XP3IE
XP3INT
00’010CH
43H
Data Sheet
17
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Preliminary
Table 3
C164CI-3V Interrupt Nodes (cont’d)
Source of Interrupt or Request
PEC Service Request Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM 6 Timer 12
T12IR
T12IE
T12INT
00’0134H
4DH
CAPCOM 6 Timer 13
T13IR
T13IE
T13INT
00’0138H
4EH
CC6EIE
CC6EINT
00’013CH
4FH
CAPCOM 6 Emergency CC6EIR
Data Sheet
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C164CI-L16M3V
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Preliminary
The C164CI-3V also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 4 shows all of the possible exceptions or error conditions that can arise during runtime:
Table 4
Hardware Trap Summary
Exception Condition
Trap
Flag
Reset Functions:
– Hardware Reset
– Software Reset
– W-dog Timer Overflow
–
Class A Hardware Traps:
– Non-Maskable Interrupt NMI
– Stack Overflow
STKOF
– Stack Underflow
STKUF
Class B Hardware Traps:
– Undefined Opcode
– Protected Instruction
Fault
– Illegal Word Operand
Access
– Illegal Instruction
Access
– Illegal External Bus
Access
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
RESET
RESET
RESET
00’0000H
00’0000H
00’0000H
00H
00H
00H
III
III
III
NMITRAP 00’0008H
STOTRAP 00’0010H
STUTRAP 00’0018H
02H
04H
06H
II
II
II
UNDOPC BTRAP
PRTFLT BTRAP
00’0028H
00’0028H
0AH
0AH
I
I
ILLOPA
BTRAP
00’0028H
0AH
I
ILLINA
BTRAP
00’0028H
0AH
I
ILLBUS
BTRAP
00’0028H
0AH
I
Reserved
–
–
[2CH –
3CH]
[0BH –
0FH]
–
Software Traps
– TRAP Instruction
–
–
Any
Any
[00’0000H – [00H –
00’01FCH] 7FH]
in steps
of 4H
Data Sheet
19
Current
CPU
Priority
V1.0, 2003-01
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Low Power
Preliminary
The Capture/Compare Unit CAPCOM2
The general purpose CAPCOM2 unit supports generation and control of timing
sequences on up to 8 channels with a maximum resolution of 16 TCL. The CAPCOM
units are typically used to handle high speed I/O tasks such as pulse and waveform
generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software
timing, or time recording relative to external events.
Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for
the capture/compare register array.
Each dual purpose capture/compare register, which may be individually allocated to
either CAPCOM timer and programmed for capture or compare function, has one port
pin associated with it which serves as an input pin for triggering the capture function, or
as an output pin to indicate the occurrence of a compare event.
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘capture’d) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event. The contents of all registers
which have been selected for one of the five compare modes are continuously compared
with the contents of the allocated timers. When a match occurs between the timer value
and the value in a capture/compare register, specific actions will be taken based on the
selected compare mode.
Table 5
Compare Modes (CAPCOM2)
Compare Modes
Function
Mode 0
Interrupt-only compare mode;
several compare interrupts per timer period are possible
Mode 1
Pin toggles on each compare match;
several compare events per timer period are possible
Mode 2
Interrupt-only compare mode;
only one compare interrupt per timer period is generated
Mode 3
Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;
only one compare event per timer period is generated
Double
Register Mode
Two registers operate on one pin; pin toggles on each compare
match;
several compare events per timer period are possible.
Registers CC16 & CC24 ➞ pin CC16IO
Registers CC17 & CC25 ➞ pin CC17IO
Registers CC18 & CC26 ➞ pin CC18IO
Registers CC19 & CC27 ➞ pin CC19IO
Data Sheet
20
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C164CI-L16M3V
Low Power
Preliminary
The Capture/Compare Unit CAPCOM6
The CAPCOM6 unit supports generation and control of timing sequences on up to three
16-bit capture/compare channels plus one 10-bit compare channel.
In compare mode the CAPCOM6 unit provides two output signals per channel which
have inverted polarity and non-overlapping pulse transitions. The compare channel can
generate a single PWM output signal and is further used to modulate the capture/
compare output signals.
In capture mode the contents of compare timer 12 is stored in the capture registers upon
a signal transition at pins CCx.
Compare timers T12 (16-bit) and T13 (10-bit) are free running timers which are clocked
by the prescaled CPU clock.
Mode
Select Register
CC6MSEL
Offset Register
T12OF
Compare
Timer T12
16-Bit
Trap Register
CC Channel 1
CC61
CC Channel 2
CC62
CTRAP
CC60
COUT60
CC Channel 0
CC60
Control
fCPU
Prescaler
Period Register
T12P
Port
Control
Logic
CC61
COUT61
CC62
COUT62
fCPU
Prescaler
Control Register
CTCON
Compare
Timer T13
10-Bit
Compare Register
CMP13
COUT63
Block
Commutation
Control
CC6MCON.H
Period Register
T13P
CC6POS0
CC6POS1
CC6POS2
MCB04109
The timer registers (T12, T13) are not directly accessible.
The period and offset registers are loading a value into the timer registers.
The shaded blocks are available in the full function module only.
Figure 5
CAPCOM6 Block Diagram
For motor control applications both subunits may generate versatile multichannel PWM
signals which are basically either controlled by compare timer 12 or by a typical hall
sensor pattern at the interrupt inputs (block commutation).
Note: Multichannel signal generation is provided only in devices with a full CAPCOM6.
Data Sheet
21
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Low Power
Preliminary
General Purpose Timer (GPT) Unit
The GPT unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT unit incorporates three 16-bit timers. Each timer may operate independently in
a number of different modes, or may be concatenated with another timer.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer
to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 16 TCL.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be used internally to clock timers T2 and T4
for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL.
Data Sheet
22
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Low Power
Preliminary
U/D
T2EUD
fCPU
2n : 1
T2IN
Interrupt
Request
(T2IR)
GPT1 Timer T2
T2
Mode
Control
Reload
Capture
fCPU
Interrupt
Request
(T3IR)
2n : 1
Toggle FF
T3
Mode
Control
T3IN
GPT1 Timer T3
T3OTL
U/D
T3EUD
Other
Timers
Capture
Reload
T4IN
fCPU
2n : 1
T4
Mode
Control
GPT1 Timer T4
U/D
T4EUD
Interrupt
Request
(T4IR)
MCT04825_4
n = 3 … 10
Figure 6
Data Sheet
Block Diagram of GPT1
23
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Preliminary
Real Time Clock
The Real Time Clock (RTC) module of the C164CI-3V consists of a chain of 3 divider
blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer
(accessible via registers RTCH and RTCL). The RTC module is directly clocked with the
on-chip oscillator frequency divided by 32 via a separate clock driver (fRTC = fOSC/32)
and is therefore independent from the selected clock generation mode of the C164CI3V. All timers count up.
The RTC module can be used for different purposes:
• System clock to determine the current time and date
• Cyclic time based interrupt
• 48-bit timer for long term measurements
T14REL
Reload
T14
8:1
f RTC
Interrupt
Request
RTCH
RTCL
MCD04432
Figure 7
RTC Block Diagram
Note: The registers associated with the RTC are not affected by a reset in order to
maintain the correct system time even when intermediate resets are executed.
Data Sheet
24
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Preliminary
A/D Converter
For analog signal measurement, a 10-bit A/D converter with 8 multiplexed input channels
and a sample and hold circuit has been integrated on-chip. It uses the method of
successive approximation. The sample time (for loading the capacitors) and the
conversion time is programmable and can so be adjusted to the external circuitry.
Overrun error detection/protection is provided for the conversion result register
(ADDAT): either an interrupt request will be generated when the result of a previous
conversion has not been read from the result register at the time the next conversion is
complete, or the next conversion is suspended in such a case until the previous result
has been read.
For applications which require less than 8 analog input channels, the remaining channel
inputs can be used as digital input port pins.
The A/D converter of the C164CI-3V supports four different conversion modes. In the
standard Single Channel conversion mode, the analog level on a specified channel is
sampled once and converted to a digital result. In the Single Channel Continuous mode,
the analog level on a specified channel is repeatedly sampled and converted without
software intervention. In the Auto Scan mode, the analog levels on a prespecified
number of channels (standard or extension) are sequentially sampled and converted. In
the Auto Scan Continuous mode, the number of prespecified channels is repeatedly
sampled and converted. In addition, the conversion of a specific channel can be inserted
(injected) into a running sequence without disturbing this sequence. This is called
Channel Injection Mode.
The Peripheral Event Controller (PEC) may be used to automatically store the
conversion results into a table in memory for later evaluation, without requiring the
overhead of entering and exiting interrupt routines for each data transfer.
After each reset and also during normal operation the ADC automatically performs
calibration cycles. This automatic self-calibration constantly adjusts the converter to
changing operating conditions (e.g. temperature) and compensates process variations.
These calibration cycles are part of the conversion cycle, so they do not affect the normal
operation of the A/D converter.
In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital IO or input stages
under software control. This can be selected for each pin separately via register P5DIDIS
(Port 5 Digital Input Disable).
Data Sheet
25
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Preliminary
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces with different functionality, an
Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous
Serial Channel (SSC).
The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to 500 Kbit/s and
half-duplex synchronous communication at up to 2.0 Mbit/s (@ 16 MHz CPU clock).
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
The SSC supports full-duplex synchronous communication at up to 4.0 Mbit/s
(@ 16 MHz CPU clock). It may be configured so it interfaces with serially linked
peripheral components. A dedicated baud rate generator allows to set up all standard
baud rates without oscillator tuning. For transmission, reception and error handling
3 separate interrupt vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and baudrate error detect incorrect serial data.
Data Sheet
26
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Preliminary
CAN-Module
The integrated CAN-Module handles the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.
The module provides Full CAN functionality on up to 15 message objects. Message
object 15 may be configured for Basic CAN functionality. Both modes provide separate
masks for acceptance filtering which allows to accept a number of identifiers in Full CAN
mode and also allows to disregard a number of identifiers in Basic CAN mode. All
message objects can be updated independent from the other objects and are equipped
for the maximum message length of 8 bytes.
The bit timing is derived from the XCLK and is programmable up to a data rate of 1 Mbit/
s. Each CAN-Module uses two pins of Port 4 or Port 8 to interface to an external bus
transceiver. The interface pins are assigned via software.
Note: When the CAN interface is assigned to Port 4, the respective segment address
lines on Port 4 cannot be used. This will limit the external address space.
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip’s start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/
256. The high byte of the Watchdog Timer register can be set to a prespecified reload
value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded. Thus, time intervals between 32 µs and 1049 ms can be
monitored (@ 16 MHz).
The default Watchdog Timer interval after reset is 8.2 ms (@ 16 MHz).
Data Sheet
27
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Parallel Ports
The C164CI-3V provides up to 59 I/O lines which are organized into five input/output
ports and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of three I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs.
The input threshold of Port 3, Port 4, and Port 8 is selectable (TTL or CMOS like), where
the special CMOS like input threshold reduces noise sensitivity due to the input
hysteresis. The input threshold may be selected individually for each byte of the
respective ports.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A21/19/17 … A16 and
the optional chip select signals in systems where segmentation is enabled to access
more than 64 Kbytes of memory.
Ports P1L, P1H, and P8 are associated with the capture inputs or compare outputs of
the CAPCOM units and/or serve as external interrupt inputs.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control
signal BHE/WRH, and the system clock output CLKOUT (or the programmable
frequency output FOUT).
Port 5 is used for the analog input channels to the A/D converter or timer control signals.
The edge characteristics (transition time) and driver characteristics (output current) of
the C164CI-3V’s port drivers can be selected via the Port Output Control registers
(POCONx).
Data Sheet
28
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Oscillator Watchdog
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock/OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.
In direct drive mode the PLL base frequency is used directly (fCPU = 2 … 5 MHz).
In prescaler mode the PLL base frequency is divided by 2 (fCPU = 1 … 2.5 MHz).
Note: The CPU clock source is only switched back to the oscillator clock after a
hardware reset.
The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON.
In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the
CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also
no interrupt request will be generated in case of a missing oscillator clock.
Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD at that time.
Thus the oscillator watchdog may also be disabled via hardware by (externally)
pulling the RD line low upon a reset, similar to the standard reset configuration via
PORT0.
Data Sheet
29
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Power Management
The C164CI-3V provides several means to control the power it consumes either at a
given time or averaged over a certain timespan. Three mechanisms can be used (partly
in parallel):
• Power Saving Modes switch the C164CI-3V into a special operating mode (control
via instructions).
Idle Mode stops the CPU while the peripherals can continue to operate.
Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may
optionally continue running). Sleep Mode can be terminated by external interrupt
signals.
• Clock Generation Management controls the distribution and the frequency of
internal and external clock signals (control via register SYSCON2).
Slow Down Mode lets the C164CI-3V run at a CPU clock frequency of fOSC/1 … 32
(half for prescaler operation) which drastically reduces the consumed power. The PLL
can be optionally disabled while operating in Slow Down Mode.
External circuitry can be controlled via the programmable frequency output FOUT.
• Peripheral Management permits temporary disabling of peripheral modules (control
via register SYSCON3).
Each peripheral can separately be disabled/enabled. A group control option disables
a major part of the peripheral set by setting one single bit.
The on-chip RTC supports intermittend operation of the C164CI-3V by generating cyclic
wakeup signals. This offers full performance to quickly react on action requests while the
intermittend sleep phases greatly reduce the average power consumption of the system.
Data Sheet
30
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Instruction Set Summary
Table 6 lists the instructions of the C164CI-3V in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “C166 Family Instruction Set Manual”.
This document also provides a detailled description of each instruction.
Table 6
Mnemonic
ADD(B)
ADDC(B)
SUB(B)
SUBC(B)
MUL(U)
DIV(U)
DIVL(U)
CPL(B)
NEG(B)
AND(B)
OR(B)
XOR(B)
BCLR
BSET
BMOV(N)
BAND, BOR,
BXOR
BCMP
BFLDH/L
CMP(B)
CMPD1/2
CMPI1/2
PRIOR
SHL / SHR
ROL / ROR
ASHR
Data Sheet
Instruction Set Summary
Description
Add word (byte) operands
Add word (byte) operands with Carry
Subtract word (byte) operands
Subtract word (byte) operands with Carry
(Un)Signed multiply direct GPR by direct GPR (16-16-bit)
(Un)Signed divide register MDL by direct GPR (16-/16-bit)
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)
Complement direct word (byte) GPR
Negate direct word (byte) GPR
Bitwise AND, (word/byte operands)
Bitwise OR, (word/byte operands)
Bitwise XOR, (word/byte operands)
Clear direct bit
Set direct bit
Move (negated) direct bit to direct bit
AND/OR/XOR direct bit with direct bit
Bytes
2/4
2/4
2/4
2/4
2
2
2
2
2
2/4
2/4
2/4
2
2
4
4
Compare direct bit to direct bit
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
Compare word (byte) operands
Compare word data to GPR and decrement GPR by 1/2
Compare word data to GPR and increment GPR by 1/2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
Shift left/right direct word GPR
Rotate left/right direct word GPR
Arithmetic (sign bit) shift right direct word GPR
4
4
31
2/4
2/4
2/4
2
2
2
2
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Table 6
Instruction Set Summary (cont’d)
Mnemonic
MOV(B)
MOVBS
MOVBZ
JMPA, JMPI,
JMPR
JMPS
J(N)B
JBC
JNBS
CALLA, CALLI,
CALLR
CALLS
PCALL
TRAP
PUSH, POP
SCXT
RET
RETS
RETP
RETI
SRST
IDLE
PWRDN
SRVWDT
DISWDT
EINIT
ATOMIC
EXTR
EXTP(R)
EXTS(R)
NOP
Data Sheet
Description
Move word (byte) data
Move byte operand to word operand with sign extension
Move byte operand to word operand with zero extension
Jump absolute/indirect/relative if condition is met
Bytes
2/4
2/4
2/4
4
Jump absolute to a code segment
Jump relative if direct bit is (not) set
Jump relative and clear bit if direct bit is set
Jump relative and set bit if direct bit is not set
Call absolute/indirect/relative subroutine if condition is met
4
4
4
4
4
Call absolute subroutine in any code segment
Push direct word register onto system stack and call
absolute subroutine
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
Push direct word register onto system stack und update
register with word operand
Return from intra-segment subroutine
Return from inter-segment subroutine
Return from intra-segment subroutine and pop direct
word register from system stack
Return from interrupt service subroutine
Software Reset
Enter Idle Mode
Enter Power Down Mode (supposes NMI-pin being low)
Service Watchdog Timer
Disable Watchdog Timer
Signify End-of-Initialization on RSTOUT-pin
Begin ATOMIC sequence
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
Null operation
4
4
32
2
2
4
2
2
2
2
4
4
4
4
4
4
2
2
2/4
2/4
2
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Special Function Registers Overview
Table 7 lists all SFRs which are implemented in the C164CI-3V in alphabetical order.
The following markings assist in classifying the listed registers:
“b” in the “Name” column marks Bit-addressable SFRs.
“E” in the “Physical Address” column marks (E)SFRs within the Extended SFR-Space.
“X” in the “Physical Address” column marks registers within the on-chip X-peripherals.
“m” in the “Physical Address” column marks SFRs without short 8-bit address.
An SFR can be specified via its individual mnemonic name. Depending on the selected
addressing mode, an SFR can be accessed via its physical address (using the Data
Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
Table 7
Name
C164CI-3V Registers, Ordered by Name
Physical
Address
8-Bit Description
Addr.
Reset
Value
ADCIC
b FF98H
CCH
A/D Converter End of Conversion
Interrupt Control Register
0000H
ADCON
b FFA0H
D0H
A/D Converter Control Register
0000H
ADDAT
FEA0H
50H
A/D Converter Result Register
0000H
ADDAT2
F0A0H
E 50H
A/D Converter 2 Result Register
0000H
ADDRSEL1
FE18H
0CH
Address Select Register 1
0000H
ADDRSEL2
FE1AH
0DH
Address Select Register 2
0000H
ADDRSEL3
FE1CH
0EH
Address Select Register 3
0000H
ADDRSEL4
FE1EH
0FH
Address Select Register 4
0000H
b FF9AH
CDH
A/D Converter Overrun Error Interrupt
Control Register
0000H
BUSCON0 b FF0CH
86H
Bus Configuration Register 0
0000H
BUSCON1 b FF14H
8AH
Bus Configuration Register 1
0000H
BUSCON2 b FF16H
8BH
Bus Configuration Register 2
0000H
BUSCON3 b FF18H
8CH
Bus Configuration Register 3
0000H
BUSCON4 b FF1AH
8DH
Bus Configuration Register 4
0000H
ADEIC
C1BTR
EF04H
X ---
CAN1 Bit Timing Register
C1CSR
EF00H
X ---
CAN1 Control / Status Register
C1GMS
EF06H
X ---
CAN1 Global Mask Short
C1LARn
EFn4H
X ---
CAN Lower Arbitration Register (msg. n) UUUUH
C1LGML
EF0AH
X ---
CAN Lower Global Mask Long
Data Sheet
33
UUUUH
XX01H
UFUUH
UUUUH
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C164CI-L16M3V
Low Power
Preliminary
Table 7
C164CI-3V Registers, Ordered by Name (cont’d)
Name
Physical
Address
8-Bit Description
Addr.
Reset
Value
C1LMLM
EF0EH
X ---
CAN Lower Mask of Last Message
C1MCFGn
EFn6H
X ---
CAN Message Configuration Register
(msg. n)
C1MCRn
EFn0H
X ---
CAN Message Control Register (msg. n) UUUUH
C1PCIR
EF02H
X ---
CAN1 Port Control / Interrupt Register
C1UARn
EFn2H
X ---
CAN Upper Arbitration Register (msg. n) UUUUH
C1UGML
EF08H
X ---
CAN Upper Global Mask Long
UUUUH
C1UMLM
EF0CH
X ---
CAN Upper Mask of Last Message
UUUUH
UUUUH
UUH
XXXXH
CC10IC
b FF8CH
C6H
External Interrupt 2 Control Register
0000H
CC11IC
b FF8EH
C7H
External Interrupt 3 Control Register
0000H
FE60H
30H
CAPCOM Register 16
0000H
b F160H
E B0H
CAPCOM Reg. 16 Interrupt Ctrl. Reg.
0000H
FE62H
31H
CAPCOM Register 17
0000H
b F162H
E B1H
CAPCOM Reg. 17 Interrupt Ctrl. Reg.
0000H
FE64H
32H
CAPCOM Register 18
0000H
b F164H
E B2H
CAPCOM Reg. 18 Interrupt Ctrl. Reg.
0000H
FE66H
33H
CAPCOM Register 19
0000H
b F166H
E B3H
CAPCOM Reg. 19 Interrupt Ctrl. Reg.
0000H
CC20
FE68H
34H
CAPCOM Register 20
0000H
CC21
FE6AH
35H
CAPCOM Register 21
0000H
CC22
FE6CH
36H
CAPCOM Register 22
0000H
CC23
FE6EH
37H
CAPCOM Register 23
0000H
CC24
FE70H
38H
CAPCOM Register 24
0000H
b F170H
E B8H
CAPCOM Reg. 24 Interrupt Ctrl. Reg.
0000H
FE72H
39H
CAPCOM Register 25
0000H
b F172H
E B9H
CAPCOM Reg. 25 Interrupt Ctrl. Reg.
0000H
FE74H
3AH
CAPCOM Register 26
0000H
b F174H
E BAH
CAPCOM Reg. 26 Interrupt Ctrl. Reg.
0000H
FE76H
3BH
CAPCOM Register 27
0000H
b F176H
E BBH
CAPCOM Reg. 27 Interrupt Ctrl. Reg.
0000H
CC16
CC16IC
CC17
CC17IC
CC18
CC18IC
CC19
CC19IC
CC24IC
CC25
CC25IC
CC26
CC26IC
CC27
CC27IC
Data Sheet
34
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Table 7
C164CI-3V Registers, Ordered by Name (cont’d)
Name
Physical
Address
8-Bit Description
Addr.
Reset
Value
CC28
FE78H
3CH
CAPCOM Register 28
0000H
CC29
FE7AH
3DH
CAPCOM Register 29
0000H
CC30
FE7CH
3EH
CAPCOM Register 30
0000H
CC31
FE7EH
3FH
CAPCOM Register 31
0000H
CC60
FE30H
18H
CAPCOM 6 Register 0
0000H
CC61
FE32H
19H
CAPCOM 6 Register 1
0000H
CC62
FE34H
1AH
CAPCOM 6 Register 2
0000H
CC6EIC
b F188H
E C4H
CAPCOM 6 Emergency Interrrupt
Control Register
0000H
CC6CIC
b F17EH
E BFH
CAPCOM 6 Interrupt Control Register
0000H
CC6MCON b FF32H
99H
CAPCOM 6 Mode Control Register
00FFH
CC6MIC
b FF36H
9BH
CAPCOM 6 Mode Interrupt Ctrl. Reg.
0000H
F036H
E 1BH
CAPCOM 6 Mode Select Register
0000H
CC8IC
b FF88H
C4H
External Interrupt 0 Control Register
0000H
CC9IC
b FF8AH
C5H
External Interrupt 1 Control Register
0000H
CCM4
b FF22H
91H
CAPCOM Mode Control Register 4
0000H
CCM5
b FF24H
92H
CAPCOM Mode Control Register 5
0000H
CCM6
b FF26H
93H
CAPCOM Mode Control Register 6
0000H
CCM7
b FF28H
94H
CAPCOM Mode Control Register 7
0000H
CMP13
FE36H
1BH
CAPCOM 6 Timer 13 Compare Reg.
0000H
CP
FE10H
08H
CPU Context Pointer Register
FC00H
CSP
FE08H
04H
CPU Code Segment Pointer Register
(8 bits, not directly writeable)
0000H
CTCON
b FF30H
98H
CAPCOM 6 Compare Timer Ctrl. Reg.
1010H
DP0H
b F102H
E 81H
P0H Direction Control Register
00H
DP0L
b F100H
E 80H
P0L Direction Control Register
00H
DP1H
b F106H
E 83H
P1H Direction Control Register
00H
DP1L
b F104H
E 82H
P1L Direction Control Register
00H
DP3
b FFC6H
E3H
Port 3 Direction Control Register
0000H
DP4
b FFCAH
E5H
Port 4 Direction Control Register
00H
CC6MSEL
Data Sheet
35
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Table 7
Name
DP8
C164CI-3V Registers, Ordered by Name (cont’d)
Physical
Address
8-Bit Description
Addr.
Reset
Value
b FFD6H
EBH
Port 8 Direction Control Register
DPP0
FE00H
00H
CPU Data Page Pointer 0 Reg. (10 bits)
0000H
DPP1
FE02H
01H
CPU Data Page Pointer 1 Reg. (10 bits)
0001H
DPP2
FE04H
02H
CPU Data Page Pointer 2 Reg. (10 bits)
0002H
DPP3
FE06H
03H
CPU Data Page Pointer 3 Reg. (10 bits)
0003H
EXICON
b F1C0H
E E0H
External Interrupt Control Register
0000H
EXISEL
b F1DAH
E EDH
External Interrupt Source Select Reg.
0000H
FOCON
b FFAAH
D5H
Frequency Output Control Register
0000H
IDCHIP
F07CH
E 3EH
Identifier
XXXXH
IDMANUF
F07EH
E 3FH
Identifier
1820H
IDMEM
F07AH
E 3DH
Identifier
XXXXH
IDPROG
F078H
E 3CH
Identifier
XXXXH
IDMEM2
F076H
E 3BH
Identifier
XXXXH
ISNC
b F1DEH
E EFH
Interrupt Subnode Control Register
0000H
MDC
b FF0EH
87H
CPU Multiply Divide Control Register
0000H
MDH
FE0CH
06H
CPU Multiply Divide Reg. – High Word
0000H
MDL
FE0EH
07H
CPU Multiply Divide Reg. – Low Word
0000H
ODP3
b F1C6H
E E3H
Port 3 Open Drain Control Register
0000H
ODP4
b F1CAH
E E5H
Port 4 Open Drain Control Register
00H
ODP8
b F1D6H
E EBH
Port 8 Open Drain Control Register
00H
ONES
b FF1EH
8FH
Constant Value 1’s Register (read only)
FFFFH
P0H
b FF02H
81H
Port 0 High Reg. (Upper half of PORT0)
00H
P0L
b FF00H
80H
Port 0 Low Reg. (Lower half of PORT0)
00H
P1H
b FF06H
83H
Port 1 High Reg. (Upper half of PORT1)
00H
P1L
b FF04H
82H
Port 1 Low Reg. (Lower half of PORT1)
00H
P3
b FFC4H
E2H
Port 3 Register
P4
b FFC8H
E4H
Port 4 Register (7 bits)
P5
b FFA2H
D1H
Port 5 Register (read only)
P5DIDIS
b FFA4H
D2H
Port 5 Digital Input Disable Register
P8
b FFD4H
EAH
Port 8 Register (8 bits)
Data Sheet
36
00H
0000H
00H
XXXXH
0000H
00H
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Table 7
C164CI-3V Registers, Ordered by Name (cont’d)
Name
Physical
Address
8-Bit Description
Addr.
PDCR
F0AAH
E 55H
PECC0
FEC0H
PECC1
Reset
Value
Port Driver Control Register
0000H
60H
PEC Channel 0 Control Register
0000H
FEC2H
61H
PEC Channel 1 Control Register
0000H
PECC2
FEC4H
62H
PEC Channel 2 Control Register
0000H
PECC3
FEC6H
63H
PEC Channel 3 Control Register
0000H
PECC4
FEC8H
64H
PEC Channel 4 Control Register
0000H
PECC5
FECAH
65H
PEC Channel 5 Control Register
0000H
PECC6
FECCH
66H
PEC Channel 6 Control Register
0000H
PECC7
FECEH
67H
PEC Channel 7 Control Register
0000H
PICON
b F1C4H
E E2H
Port Input Threshold Control Register
0000H
PSW
b FF10H
88H
CPU Program Status Word
0000H
PTCR
b F0AEH
57H
Port Temperature Compensation Reg.
0000H
RP0H
b F108H
E 84H
System Startup Config. Reg. (Rd. only)
RSTCON
b F1E0H
m ---
Reset Control Register
XXH
00XXH
RTCH
F0D6H
E 6BH
RTC High Register
no
RTCL
F0D4H
E 6AH
RTC Low Register
no
S0BG
FEB4H
5AH
Serial Channel 0 Baud Rate Generator
Reload Register
0000H
S0CON
b FFB0H
D8H
Serial Channel 0 Control Register
0000H
S0EIC
b FF70H
B8H
Serial Channel 0 Error Interrupt Ctrl.
Reg.
0000H
FEB2H
59H
Serial Channel 0 Receive Buffer Reg.
(read only)
S0RIC
b FF6EH
B7H
Serial Channel 0 Receive Interrupt
Control Register
0000H
S0TBIC
b F19CH
E CEH
Serial Channel 0 Transmit Buffer
Interrupt Control Register
0000H
FEB0H
58H
Serial Channel 0 Transmit Buffer Reg.
(write only)
0000H
b FF6CH
B6H
Serial Channel 0 Transmit Interrupt
Control Register
0000H
S0RBUF
S0TBUF
S0TIC
Data Sheet
37
XXXXH
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Table 7
C164CI-3V Registers, Ordered by Name (cont’d)
Name
Physical
Address
8-Bit Description
Addr.
SP
FE12H
09H
SSCBR
F0B4H
E 5AH
SSCCON
b FFB2H
SSCEIC
Reset
Value
CPU System Stack Pointer Register
FC00H
SSC Baudrate Register
0000H
D9H
SSC Control Register
0000H
b FF76H
BBH
SSC Error Interrupt Control Register
0000H
SSCRB
F0B2H
E 59H
SSCRIC
b FF74H
BAH
SSCTB
F0B0H
E 58H
SSCTIC
b FF72H
STKOV
STKUN
SSC Receive Buffer
XXXXH
SSC Receive Interrupt Control Register
0000H
SSC Transmit Buffer
0000H
B9H
SSC Transmit Interrupt Control Register
0000H
FE14H
0AH
CPU Stack Overflow Pointer Register
FA00H
FE16H
0BH
CPU Stack Underflow Pointer Register
FC00H
b FF12H
89H
CPU System Configuration Register
SYSCON1 b F1DCH
E EEH
CPU System Configuration Register 1
0000H
SYSCON2 b F1D0H
E E8H
CPU System Configuration Register 2
0000H
SYSCON3 b F1D4H
E EAH
CPU System Configuration Register 3
0000H
T12IC
b F190H
E C8H
CAPCOM 6 Timer 12 Interrupt Ctrl. Reg.
0000H
T12OF
F034H
E 1AH
CAPCOM 6 Timer 12 Offset Register
0000H
T12P
F030H
E 18H
CAPCOM 6 Timer 12 Period Register
0000H
E CCH
CAPCOM 6 Timer 13 Interrupt Ctrl. Reg.
0000H
0000H
SYSCON
T13IC
b F198H
1)
0xx0H
T13P
F032H
E 19H
CAPCOM 6 Timer 13 Period Register
T14
F0D2H
E 69H
RTC Timer 14 Register
no
T14REL
F0D0H
E 68H
RTC Timer 14 Reload Register
no
T2
FE40H
20H
GPT1 Timer 2 Register
0000H
T2CON
b FF40H
A0H
GPT1 Timer 2 Control Register
0000H
T2IC
b FF60H
B0H
GPT1 Timer 2 Interrupt Control Register
0000H
FE42H
21H
GPT1 Timer 3 Register
0000H
T3CON
b FF42H
A1H
GPT1 Timer 3 Control Register
0000H
T3IC
b FF62H
B1H
GPT1 Timer 3 Interrupt Control Register
0000H
FE44H
22H
GPT1 Timer 4 Register
0000H
T4CON
b FF44H
A2H
GPT1 Timer 4 Control Register
0000H
T4IC
b FF64H
B2H
GPT1 Timer 4 Interrupt Control Register
0000H
T3
T4
Data Sheet
38
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C164CI-L16M3V
Low Power
Preliminary
Table 7
C164CI-3V Registers, Ordered by Name (cont’d)
Name
Physical
Address
T7
F050H
E 28H
T78CON
b FF20H
90H
T7IC
b F17AH
T7REL
T8
T8IC
T8REL
8-Bit Description
Addr.
Reset
Value
CAPCOM Timer 7 Register
0000H
CAPCOM Timer 7 and 8 Ctrl. Reg.
0000H
E BDH
CAPCOM Timer 7 Interrupt Ctrl. Reg.
0000H
F054H
E 2AH
CAPCOM Timer 7 Reload Register
0000H
F052H
E 29H
CAPCOM Timer 8 Register
0000H
b F17CH
E BEH
CAPCOM Timer 8 Interrupt Ctrl. Reg.
0000H
F056H
E 2BH
CAPCOM Timer 8 Reload Register
0000H
TFR
b FFACH
D6H
Trap Flag Register
0000H
TRCON
b FF34H
9AH
CAPCOM 6 Trap Enable Ctrl. Reg.
00XXH
WDT
FEAEH
57H
Watchdog Timer Register (read only)
0000H
WDTCON
FFAEH
D7H
Watchdog Timer Control Register
XP0IC
b F186H
E C3H
CAN1 Module Interrupt Control Register
0000H
XP1IC
b F18EH
E C7H
Unassigned Interrupt Control Reg.
0000H
XP3IC
b F19EH
E CFH
PLL/RTC Interrupt Control Register
0000H
ZEROS
b FF1CH
8EH
Constant Value 0’s Register (read only)
0000H
1)
The system configuration is selected during reset.
2)
The reset value depends on the indicated reset source.
Data Sheet
39
2)
00xxH
V1.0, 2003-01
C164CI-L16M3V
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Preliminary
Absolute Maximum Ratings
Table 8
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
Unit
Notes
min.
max.
TST
TJ
VDD
-65
150
°C
–
-40
150
°C
under bias
-0.5
6.5
V
–
Voltage on any pin with
respect to ground (VSS)
VIN
-0.5
VDD + 0.5 V
–
Input current on any pin
during overload condition
–
-10
10
mA
–
Absolute sum of all input
currents during overload
condition
–
–
|100|
mA
–
Power dissipation
PDISS
–
1.5
W
–
Storage temperature
Junction temperature
Voltage on VDD pins with
respect to ground (VSS)
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the
voltage on VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
40
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C164CI-L16M3V
Low Power
Preliminary
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the C164CI-3V. All parameters specified in the following sections refer to
these operating conditions, unless otherwise noticed.
Table 9
Operating Condition Parameters
Parameter
Symbol
Limit Values
min.
Digital supply voltage
VDD
VSS
Overload current
IOV
Absolute sum of overload Σ|IOV|
Unit Notes
max.
3.0
3.6
V
Active mode,
fCPUmax = 16 MHz
2.51)
3.6
V
PowerDown mode
V
Reference voltage
Digital ground voltage
0
–
±5
mA
Per pin2)3)
–
50
mA
3)
currents
External Load
Capacitance
CL
–
100
pF
Pin drivers in
default mode4)5)
Ambient temperature
TA
0
70
°C
SAB-C164CI-3V
…
-40
85
°C
SAF-C164CI-3V …
-40
125
°C
SAK-C164CI-3V
…
1)
Output voltages and output currents will be reduced when VDD leaves the range defined for active mode.
2)
Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload
currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,
etc.
3)
Not 100% tested, guaranteed by design and characterization.
4)
The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output
current may lead to increased delays or reduced driving capability (CL).
5)
The current version of the C164CI-3V is equipped with port drivers, which provide reduced driving capability
and reduced control. Please refer to the actual errata sheet for details.
Data Sheet
41
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C164CI-L16M3V
Low Power
Preliminary
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C164CI3V and partly its demands on the system. To aid in interpreting the parameters right,
when evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the C164CI-3V will provide signals with the respective characteristics.
SR (System Requirement):
The external system must provide signals with the respective characteristics to the
C164CI-3V.
DC Characteristics
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
min.
max.
Input low voltage (TTL,
all except XTAL1)
VIL
Input low voltage XTAL1
VIL2 SR -0.5
VILS SR -0.5
Input high voltage (TTL,
all except RSTIN, XTAL1)
VIH
Input high voltage RSTIN
(when operated as input)
VIH1 SR 0.6 VDD VDD +
Input high voltage XTAL1
VIH2 SR 0.7 VDD VDD +
Input low voltage
(Special Threshold)
SR -0.5
SR 1.8
Unit Test Conditions
0.8
V
–
0.3 VDD V
–
1.3
V
–
VDD +
V
–
V
–
V
–
V
–
0.5
0.5
0.5
Input high voltage
(Special Threshold)
VIHS SR 0.8 VDD VDD +
Input Hysteresis
(Special Threshold)
HYS
Output low voltage2)
VOL CC –
VOH CC VDD -
Output high voltage4)
- 0.2
0.5
150
–
mV
Series resistance
=0Ω
0.45
V
–
V
IOL ≤ IOLnom3)
IOH ≥ IOHnom3)
±200
nA
0 V < VIN < VDD
±500
nA
0.45 V < VIN <
µA
VDD
VIN = VIH1
0.45
Input leakage current (Port 5)
Input leakage current (all other)
RSTIN inactive current5)
Data Sheet
IOZ1 CC –
IOZ2 CC –
IRSTH6)
–
42
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V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
DC Characteristics (cont’d)
(Operating Conditions apply)1)
Parameter
Symbol
RSTIN active current5)
RD/WR inact. current8)
RD/WR active current8)
8)
ALE inactive current
ALE active current
8)
8)
Port 4 inactive current
Port 4 active current8)
PORT0 configuration current9)
XTAL1 input current
10)
Pin capacitance
(digital inputs/outputs)
IRSTL7)
IRWH 6)
IRWL7)
IALEL6)
IALEH7)
IP4H6)
IP4L7)
IP0H6)
IP0L7)
IIL CC
CIO CC
Limit Values
Unit Test Conditions
min.
max.
-100
–
µA
–
-10
µA
-500
–
µA
–
20
µA
500
–
µA
–
-10
µA
-500
–
µA
–
-5
µA
-100
–
µA
–
±20
µA
–
10
pF
VIN = VIL
VOUT = 2.4 V
VOUT = VOLmax
VOUT = VOLmax
VOUT = 2.4 V
VOUT = 2.4 V
VOUT = VOL1max
VIN = VIHmin
VIN = VILmax
0 V < VIN < VDD
f = 1 MHz
TA = 25 °C
1)
Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications also refer to the specification of the overload current IOV.
2)
For pin RSTIN this specification is only valid in bidirectional reset mode.
3)
As a rule, with decreasing output current the output levels approach the respective supply level (VOL → VSS,
VOH → VDD). However, only the levels for nominal output currents are guaranteed.
See Table 10, Current Limits for Port Output Drivers.
4)
This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
5)
These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.
6)
The maximum current may be drawn while the respective signal line remains inactive.
7)
The minimum current must be drawn in order to drive the respective signal line active.
8)
This specification is valid during Reset and during Adapt-mode. The Port 4 current values are only valid for
pins P4.3-0, which can act as CS outputs.
9)
This specification is valid during Reset if required for configuration, and during Adapt-mode.
10)
Not 100% tested, guaranteed by design and characterization.
Data Sheet
43
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C164CI-L16M3V
Low Power
Preliminary
Table 10
Current Limits for Port Output Drivers
Port Output Driver
Mode
Maximum Output Current
(IOLmax, -IOHmax)1)
Nominal Output Current
(IOLnom, -IOHnom)
(PORT0, PORT1,
Port 2, Port 4, ALE,
RD, WR, BHE,
CLKOUT, RSTOUT,
RSTIN2))
-----
1.6 mA
All other outputs
-----
0.5 mA
1)
An output current above |IOXnom| is not specified for the C164CI-3V.
2)
Valid for VOL in bidirectional reset mode only.
Power Consumption C164CI-3V
(Operating Conditions apply)
Parameter
Symbol
min.
max.
Power supply current (active)
with all peripherals active
IDD
–
1+
mA
1.5 × fCPU
RSTIN = VIL
fCPU in [MHz]1)
Idle mode supply current
with all peripherals active
IIDX
–
1+
mA
0.7 × fCPU
RSTIN = VIH1
fCPU in [MHz]1)
Idle mode supply current
with all peripherals deactivated,
PLL off, SDD factor = 32
IIDO2) –
500 +
µA
50 × fOSC
RSTIN = VIH1
fOSC in [MHz]1)
Sleep and Power-down mode
supply current with RTC running
IPDR2) –
200 +
µA
25 × fOSC
VDD = VDDmax
fOSC in [MHz]3)
VDD = VDDmax3)
Sleep and Power-down mode
IPDO
supply current with RTC disabled
Limit Values
–
30
Unit Test
Conditions
µA
1)
The supply current is a function of the operating frequency. This dependency is illustrated in Figure 9.
These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs
at VIL or VIH.
2)
This parameter is determined mainly by the current consumed by the oscillator (see Figure 8). This current,
however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical
circuitry and may change in case of a not optimized external oscillator circuitry.
3)
This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VDD - 0.1 V to VDD, all outputs (including pins configured as outputs) disconnected.
Data Sheet
44
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C164CI-L16M3V
Low Power
Preliminary
I [µA]
3000
IIDOmax
IIDOtyp
2000
IPDRmax
1000
IPDOmax
10
Figure 8
Data Sheet
20
30
40
fOSC [MHz]
Idle and Power Down Supply Current as a Function of Oscillator
Frequency
45
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C164CI-L16M3V
Low Power
Preliminary
I [mA]
100
80
60
IDD3max
IDD3typ
40
IIDX3max
20
IIDX3typ
10
Figure 9
Data Sheet
15
20
25
fCPU [MHz]
Supply/Idle Current as a Function of Operating Frequency
for ROM Derivatives
46
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C164CI-L16M3V
Low Power
Preliminary
AC Characteristics
Definition of Internal Timing
The internal operation of the C164CI-3V is controlled by the internal CPU clock fCPU.
Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus
cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 10).
Phase Locked Loop Operation
fOSC
TCL
fCPU
TCL
Direct Clock Drive
fOSC
TCL
fCPU
TCL
Prescaler Operation
fOSC
TCL
fCPU
TCL
Figure 10
MCT04338
Generation Mechanisms for the CPU Clock
The CPU clock signal fCPU can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate fCPU. This influence must
be regarded when calculating the timings for the C164CI-3V.
Note: The example for PLL operation shown in Figure 10 refers to a PLL factor of 4.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
Data Sheet
47
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register
RSTCON under software control.
Table 11 associates the combinations of these three bits with the respective clock
generation mode.
Table 11
C164CI-3V Clock Generation Modes
CLKCFG1) CPU Frequency
(RP0H.7-5) fCPU = fOSC × F
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
fOSC × 4
fOSC × 3
fOSC × 2
fOSC × 5
fOSC × 1
fOSC × 1.5
fOSC / 2
fOSC × 2.5
External Clock
Input Range2)
Notes
2.5 to 4 MHz
Default configuration
3.33 to 5.33 MHz
–
5 to 8 MHz
–
2 to 3.2 MHz
–
1 to 16 MHz
Direct drive3)
6.66 to 10.66 MHz
–
2 to 32 MHz
CPU clock via prescaler
4 to 6.4 MHz
–
1)
Please note that pin P0.15 (corresponding to RP0H.7) is inverted in emulation mode, and thus also in EHM.
2)
The external clock input range refers to a CPU clock range of 10 … 16 MHz.
3)
The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation
When prescaler operation is configured (CLKCFG = 001B) the CPU clock is derived from
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of fOSC and the high and low time of fCPU (i.e.
the duration of an individual TCL) is defined by the period of the input clock fOSC.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of fOSC for any TCL.
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see Table 11). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.
fCPU = fOSC × F). With every F’th transition of fOSC the PLL circuit synchronizes the CPU
clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.
Data Sheet
48
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so
it is locked to fOSC. The slight variation causes a jitter of fCPU which also effects the
duration of individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and Figure 11).
For a period of N × TCL the minimum value is computed using the corresponding
deviation DN:
(N × TCL)min = N × TCLNOM - DN; DN [ns] = ±(13.3 + N × 6.3)/fCPU [MHz],
where N = number of consecutive TCLs and 1 ≤ N ≤ 40.
So for a period of 3 TCLs @ 16 MHz (i.e. N = 3): D3 = (13.3 + 3 × 6.3)/16 = 2.013 ns,
and (3TCL)min = 3TCLNOM - 2.013 ns = 91.7 ns (@ fCPU = 16 MHz).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 11).
Max. jitter DN
ns
±30
This approximated formula is valid for
1<
–N<
– 40 and 10 MHz <
– fCPU <
– 25 MHz.
10 MHz
±26.5
±20
16 MHz
20 MHz
25 MHz
±10
±1
1
10
20
30
40
N
MCD04455
Figure 11
Data Sheet
Approximated Maximum Accumulated PLL Jitter
49
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C164CI-L16M3V
Low Power
Preliminary
Direct Drive
When direct drive is configured (CLKCFG = 011B) the on-chip phase locked loop is
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of fCPU directly follows the frequency of fOSC so the high and low time of
fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
fOSC.
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
TCLmin = 1/fOSC × DCmin
(DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of fOSC is compensated
so the duration of 2TCL is always 1/fOSC. The minimum value TCLmin therefore has to
be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that
require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/fOSC.
Data Sheet
50
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C164CI-L16M3V
Low Power
Preliminary
AC Characteristics
External Clock Drive XTAL1
(Operating Conditions apply)
Table 12
External Clock Drive Characteristics
Parameter
Symbol
Direct Drive
1:1
min.
Oscillator period
High time2)
Low time2)
Rise time2)
2)
Fall time
tOSC
t1
t2
t3
t4
Prescaler
2:1
PLL
1:N
Unit
max.
min.
max.
min.
max.
SR 62
1000
31
500
941)
5001)
ns
SR 313)
–
8
–
10
–
ns
SR 313)
–
8
–
10
–
ns
SR –
8
–
6
–
10
ns
SR –
8
–
6
–
10
ns
1)
The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation
mode. Please see respective table above.
2)
The clock input signal must reach the defined levels VIL2 and VIH2.
3)
The minimum high and low time refers to a duty cycle of 50%. The maximum operating freqency (fCPU) in direct
drive mode depends on the duty cycle of the clock input signal.
t1
t3
t4
VIH2
0.5 VDD
VIL
t2
t OSC
MCT02534
Figure 12
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is
limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range (see Table 12). Operation at lower input frequencies is possible but is
guaranteed by design only (not 100% tested).
Data Sheet
51
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Preliminary
A/D Converter Characteristics
(Operating Conditions apply)
Table 13
A/D Converter Characteristics
Parameter
Analog reference supply
Analog reference ground
Analog input voltage range
Basic clock frequency
Conversion time
Symbol
VAREF SR
VAGND SR
VAIN SR
fBC
tC
CC
Limit Values
Unit Test
Conditions
min.
max.
2.6
VSS - 0.1
VAGND
VDD + 0.1 V
VSS + 0.2 V
VAREF
V
–
0.5
6.25
3)
–
40 tBC + –
tS + 2tCPU
4)
3328 tBC
–
5)
MHz
1)
2)
tCPU = 1 / fCPU
Calibration time after reset
tCAL
Total unadjusted error
TUE CC –
±4
LSB
1)
Internal resistance of
reference voltage source
RAREF SR –
tBC / 60
kΩ
tBC in [ns]6)7)
kΩ
tS in [ns]7)8)
pF
7)
CC –
- 0.25
Internal resistance of analog RASRC SR –
source
ADC input capacitance
CAIN CC –
tS / 450
- 0.25
33
1)
TUE is tested at VAREF = VDD + 0.1 V, VAGND = 0 V. It is guaranteed by design for all other voltages within the
defined voltage range.
If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V
(i.e. VAREF = VDD +0.2 V) the maximum TUE is increased to ±5 LSB. This range is not 100% tested.
The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see IOV
specification) does not exceed 10 mA.
During the reset calibration sequence the maximum TUE may be ±8 LSB.
2)
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be X000H or X3FFH, respectively.
3)
The limit values for fBC must not be exceeded when selecting the CPU frequency and the ADCTC setting.
4)
This parameter includes the sample time tS, the time for determining the digital result and the time to load the
result register with the conversion result.
Values for the basic clock tBC depend on programming and can be taken from Table 14.
This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.
5)
During the reset calibration conversions can be executed (with the current accuracy). The time required for
these conversions is added to the total reset calibration time.
6)
During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.
7)
Not 100% tested, guaranteed by design and characterization.
Data Sheet
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Low Power
Preliminary
8)
During the sample time the input capacitance CAIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result.
Values for the sample time tS depend on programming and can be taken from Table 14.
Sample time and conversion time of the C164CI-3V’s A/D Converter are programmable.
Table 14 should be used to calculate the above timings.
The limit values for fBC must not be exceeded when selecting ADCTC.
Table 14
A/D Converter Computation Table
ADCON.15|14
(ADCTC)
A/D Converter
Basic Clock fBC
ADCON.13|12 Sample time
(ADSTC)
tS
00
fCPU / 4
fCPU / 2
fCPU / 16
fCPU / 8
00
01
10
11
01
10
11
tBC × 8
tBC × 16
tBC × 32
tBC × 64
Converter Timing Example:
Assumptions:
Basic clock
Sample time
Conversion time
Data Sheet
fCPU
fBC
tS
tC
= 12.5 MHz (i.e. tCPU = 80 ns), ADCTC = ‘01’, ADSTC = ‘00’.
= fCPU / 2 = 6.25 MHz, i.e. tBC = 160 ns.
= tBC × 8 = 1280 ns.
= tS + 40 tBC + 2 tCPU = (1280 + 6400 + 160) ns = 7.8 µs.
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Preliminary
Testing Waveforms
2.4 V
1.8 V
1.8 V
Test Points
0.8 V
0.45 V
0.8 V
AC inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’.
Timing measurements are made at VIH min for a logic ’1’ and VIL max for a logic ’0’.
MCA04414
Figure 13
Input Output Waveforms
VLoad + 0.1 V
VOH - 0.1 V
Timing
Reference
Points
VLoad - 0.1 V
VOL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded VOH / VOL level occurs (I OH / I OL = 20 mA).
MCA00763
Figure 14
Data Sheet
Float Waveforms
54
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.
Table 15
Memory Cycle Variables
Description
Symbol
Values
ALE Extension
tA
tC
tF
TCL × <ALECTL>
Memory Cycle Time Waitstates
Memory Tristate Time
2TCL × (15 - <MCTC>)
2TCL × (1 - <MTTC>)
Note: Please respect the maximum operating frequency of the respective derivative.
AC Characteristics
Multiplexed Bus
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (187.5 ns at 16 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 16 MHz
1 / 2TCL = 1 to 16 MHz
min.
max.
min.
max.
ALE high time
t5
CC 17 + tA
–
TCL - 14
+ tA
–
ns
Address setup to ALE
t6
CC 11 + tA
–
TCL - 20
+ tA
–
ns
Address hold after ALE
t7
CC 21 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 21 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC -10 + tA –
-10 + tA
–
ns
Address float after RD,
WR (with RW-delay)
t10 CC –
6
–
6
ns
Address float after RD,
WR (no RW-delay)
t11 CC –
37
–
TCL + 6
ns
RD, WR low time
(with RW-delay)
t12 CC 46 + tC
–
2TCL - 16
+ tC
–
ns
Data Sheet
55
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Multiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (187.5 ns at 16 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 16 MHz
1 / 2TCL = 1 to 16 MHz
min.
max.
min.
max.
RD, WR low time
(no RW-delay)
t13 CC 78 + tC
–
3TCL - 16
+ tC
–
ns
RD to valid data in
(with RW-delay)
t14 SR –
35 + tC
–
2TCL - 28
+ tC
ns
RD to valid data in
(no RW-delay)
t15 SR –
66 + tC
–
3TCL - 28
+ tC
ns
ALE low to valid data in
t16 SR –
64 + tA
+ tC
–
3TCL - 30
+ tA + tC
ns
Address to valid data in
t17 SR –
82 + 2tA –
+ tC
4TCL - 43
+ 2tA + tC
ns
Data hold after RD
rising edge
t18 SR 0
–
0
–
ns
Data float after RD
t19 SR –
49 + tF
–
2TCL - 14
+ tF
ns
Data valid to WR
t22 CC 37 + tC
–
2TCL - 26
+ tC
–
ns
Data hold after WR
t23 CC 49 + tF
–
2TCL - 14
+ tF
–
ns
ALE rising edge after RD, t25 CC 49 + tF
WR
–
2TCL - 14
+ tF
–
ns
Address hold after RD,
WR
t27 CC 49 + tF
–
2TCL - 14
+ tF
–
ns
ALE falling edge to CS1)
10 - tA
-8 - tA
10 - tA
ns
CS low to Valid Data In1)
t38 CC -8 - tA
t39 SR –
66
+ tC
+ 2tA
–
3TCL - 28
+ tC + 2tA
ns
CS hold after RD, WR1)
t40 CC 76 + tF
–
3TCL - 18
+ tF
–
ns
ALE fall. edge to RdCS,
WrCS (with RW delay)
t42 CC 25 + tA
–
TCL - 6
+ tA
–
ns
Data Sheet
56
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Multiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2tA + tC + tF (187.5 ns at 16 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 16 MHz
1 / 2TCL = 1 to 16 MHz
min.
max.
min.
max.
–
-6
+ tA
–
ns
Address float after RdCS, t44 CC –
WrCS (with RW delay)
0
–
0
ns
Address float after RdCS, t45 CC –
WrCS (no RW delay)
31
–
TCL
ns
ALE fall. edge to RdCS,
WrCS (no RW delay)
t43 CC -6 + tA
RdCS to Valid Data In
(with RW delay)
t46 SR –
33 + tC
–
2TCL - 30
+ tC
ns
RdCS to Valid Data In
(no RW delay)
t47 SR –
64 + tC
–
3TCL - 30
+ tC
ns
RdCS, WrCS Low Time
(with RW delay)
t48 CC 51 + tC
–
2TCL - 12
+ tC
–
ns
RdCS, WrCS Low Time
(no RW delay)
t49 CC 82 + tC
–
3TCL - 12
+ tC
–
ns
Data valid to WrCS
t50 CC 41 + tC
–
2TCL - 22
+ tC
–
ns
Data hold after RdCS
t51 SR 0
t52 SR –
–
0
–
ns
43 + tF
–
2TCL - 20
+ tF
ns
Address hold after
RdCS, WrCS
t54 CC 43 + tF
–
2TCL - 20
+ tF
–
ns
Data hold after WrCS
t56 CC 43 + tF
–
2TCL - 20
+ tF
–
ns
Data float after RdCS
1)
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Data Sheet
57
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
t5
t16
t25
ALE
t38
t39
t40
CSxL
t17
A21-A16
(A15-A8)
BHE, CSxE
t27
Address
t6
t7
t54
t19
Read Cycle
BUS
t18
Address
t8
Data In
t10
t14
RD
t42
t44
t12
t51
t52
t46
RdCSx
t48
Write Cycle
BUS
t23
Address
t8
WR,
WRL,
WRH
t42
Data Out
t56
t10
t22
t12
t50
t44
WrCSx
t48
Figure 15
Data Sheet
External Memory Cycle:
Multiplexed Bus, With Read/Write Delay, Normal ALE
58
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
t5
t16
t25
t39
t40
t17
t27
ALE
t38
CSxL
A21-A16
(A15-A8)
BHE, CSxE
Address
t6
t7
t54
t19
Read Cycle
BUS
t18
Address
Data In
t10
t8
t14
RD
t4
t42
t12
t51
t52
t46
RdCSx
t48
Write Cycle
BUS
t23
Address
Data Out
t10
t8
WR,
WRL,
WRH
t44
t42
t56
t22
t12
t50
WrCSx
t48
Figure 16
External Memory Cycle:
Multiplexed Bus, With Read/Write Delay, Extended ALE
Data Sheet
59
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
t5
t16
t25
ALE
t38
t39
t40
CSxL
t17
A21-A16
(A15-A8)
BHE, CSxE
t27
Address
t6
t7
t54
t19
Read Cycle
BUS
t18
Address
t9
Data In
t11
t15
RD
t43
t13
t45
t47
RdCSx
t51
t52
t49
Write Cycle
BUS
t23
Address
t9
WR,
WRL,
WRH
t43
Data Out
t56
t11
t22
t45
t13
t50
WrCSx
t49
Figure 17
Data Sheet
External Memory Cycle:
Multiplexed Bus, No Read/Write Delay, Normal ALE
60
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
t5
t16
t25
t39
t40
t17
t27
ALE
t38
CSxL
A21-A16
(A15-A8)
BHE, CSxE
Address
t6
t7
t54
t19
Read Cycle
BUS
t18
Address
Data In
t9
t11
RD
t15
t13
t43
t45
RdCSx
t51
t52
t47
t49
Write Cycle
BUS
t23
Address
Data Out
t56
t9
WR,
WRL,
WRH
t43
t11
t22
t45
t13
t50
WrCSx
t49
Figure 18
External Memory Cycle:
Multiplexed Bus, No Read/Write Delay, Extended ALE
Data Sheet
61
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
AC Characteristics
Demultiplexed Bus
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (125 ns at 16 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 16 MHz
1 / 2TCL = 1 to 16 MHz
min.
max.
min.
max.
ALE high time
t5
CC 17 + tA
–
TCL - 14
+ tA
–
ns
Address setup to ALE
t6
CC 11 + tA
–
TCL - 20
+ tA
–
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 21 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC -10 + tA –
-10
+ tA
–
ns
RD, WR low time
(with RW-delay)
t12 CC 47 + tC
–
2TCL - 16
+ tC
–
ns
RD, WR low time
(no RW-delay)
t13 CC 78 + tC
–
3TCL - 16
+ tC
–
ns
RD to valid data in
(with RW-delay)
t14 SR –
35 + tC
–
2TCL - 28
+ tC
ns
RD to valid data in
(no RW-delay)
t15 SR –
66 + tC
–
3TCL - 28
+ tC
ns
ALE low to valid data in
t16 SR –
64 +
–
3TCL - 30
+ tA + tC
ns
tA + tC
Address to valid data in
t17 SR –
82 +
2tA + tC
–
4TCL - 43
+ 2tA + tC
ns
Data hold after RD
rising edge
t18 SR 0
–
0
–
ns
Data float after RD rising
edge (with RW-delay1))
t20 SR –
49 +
–
1)
2tA + tF
2TCL - 14
+ 2tA
+ tF1)
ns
Data float after RD rising
edge (no RW-delay1))
t21 SR –
21 +
–
1)
2tA + tF
TCL - 10
+ 2tA
+ tF1)
ns
Data Sheet
62
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Demultiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (125 ns at 16 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 16 MHz
1 / 2TCL = 1 to 16 MHz
min.
max.
min.
max.
Data valid to WR
t22 CC 37 + tC
–
2TCL - 26
+ tC
–
ns
Data hold after WR
t24 CC 21 + tF
–
TCL - 10
+ tF
–
ns
ALE rising edge after RD, t26 CC -12 + tF
WR
–
-12 + tF
–
ns
Address hold after WR2)
–
0 + tF
–
ns
10 - tA
-8 - tA
10 - tA
ns
66 +
–
3TCL - 28
+ tC + 2tA
ns
ALE falling edge to CS3)
CS low to Valid Data In3)
t28 CC 0 + tF
t38 CC -8 - tA
t39 SR –
tC + 2tA
CS hold after RD, WR3)
t41 CC 15 + tF
–
TCL - 16
+ tF
–
ns
ALE falling edge to RdCS, t42 CC 25 + tA
WrCS (with RW-delay)
–
TCL - 6
+ tA
–
ns
ALE falling edge to RdCS, t43 CC -6 + tA
WrCS (no RW-delay)
–
-6
+ tA
–
ns
RdCS to Valid Data In
(with RW-delay)
t46 SR –
33 + tC
–
2TCL - 30
+ tC
ns
RdCS to Valid Data In
(no RW-delay)
t47 SR –
64 + tC
–
3TCL - 30
+ tC
ns
RdCS, WrCS Low Time
(with RW-delay)
t48 CC 51 + tC
–
2TCL - 12
+ tC
–
ns
RdCS, WrCS Low Time
(no RW-delay)
t49 CC 82 + tC
–
3TCL - 12
+ tC
–
ns
Data valid to WrCS
t50 CC 41 + tC
–
2TCL - 22
+ tC
–
ns
Data hold after RdCS
t51 SR 0
t53 SR –
–
0
–
ns
43 + tF
–
2TCL - 20 ns
+ 2tA + tF1)
Data float after RdCS
(with RW-delay)1)
Data Sheet
63
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Demultiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2tA + tC + tF (125 ns at 16 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 16 MHz
1 / 2TCL = 1 to 16 MHz
min.
max.
min.
max.
11 + tF
–
TCL - 20
ns
1)
+ 2tA + tF
Data float after RdCS
(no RW-delay)1)
t68 SR –
Address hold after
RdCS, WrCS
t55 CC -16 + tF –
-16 + tF
–
ns
Data hold after WrCS
t57 CC 15 + tF
TCL - 16
+ tF
–
ns
–
1)
RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2)
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3)
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Data Sheet
64
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
t5
t16
t26
ALE
t38
t39
t41
CSxL
t17
A21-A16
A15-A0
BHE, CSxE
t28
Address
t6
t55
t20
t18
Read Cycle
BUS
(D15-D8)
D7-D0
Data In
t8
t14
RD
t12
t42
RdCSx
t51
t53
t46
t48
Write Cycle
BUS
(D15-D8)
D7-D0
WR,
WRL,
WRH
t24
Data Out
t57
t8
t22
t12
t50
t42
WrCSx
t48
Figure 19
Data Sheet
External Memory Cycle:
Demultiplexed Bus, With Read/Write Delay, Normal ALE
65
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
t5
t16
t26
ALE
t38
t39
t41
CSxL
t17
A21-A16
A15-A0
BHE,
CSxE
t28
Address
t6
t55
t20
t18
Read Cycle
BUS
(D15-D8)
D7-D0
Data In
t8
t14
RD
t12
t42
t51
t53
t46
RdCSx
t48
Write Cycle
BUS
(D15-D8)
D7-D0
WR,
WRL,
WRH
t24
Data Out
t57
t8
t22
t12
t50
t42
WrCSx
t48
Figure 20
Data Sheet
External Memory Cycle:
Demultiplexed Bus, With Read/Write Delay, Extended ALE
66
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
t5
t16
t26
ALE
t38
t39
t41
CSxL
t17
A21-A16
A15-A0
BHE, CSxE
t28
Address
t6
Read Cycle
BUS
(D15-D8)
D7-D0
t55
t21
t18
Data In
t9
t15
RD
t43
t13
t47
RdCSx
t51
t68
t49
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data Out
t57
t9
t22
WR,
WRL,WRH
t13
t50
t43
WrCSx
t49
Figure 21
External Memory Cycle:
Demultiplexed Bus, No Read/Write Delay, Normal ALE
Data Sheet
67
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
t5
t16
t26
ALE
t38
t39
t41
CSxL
t17
A21-A16
A15-A0
BHE, CSxE
t28
Address
t6
t55
t21
t18
Read Cycle
BUS
(D15-D8)
D7-D0
Data In
t9
t15
RD
t13
t43
t51
t68
t47
RdCSx
t49
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data Out
t57
t9
t22
WR,
WRL, WRH
t13
t50
t43
WrCSx
t49
Figure 22
Data Sheet
External Memory Cycle:
Demultiplexed Bus, No Read/Write Delay, Extended ALE
68
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
AC Characteristics
CLKOUT
(Operating Conditions apply)
Parameter
Symbol
Max. CPU Clock Variable CPU Clock Unit
= 16 MHz
1 / 2TCL = 1 to 16 MHz
min.
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
t29
t30
t31
t32
t33
t34
max.
min.
max.
CC 63
63
2TCL
2TCL
ns
CC 21
–
TCL - 10
–
ns
CC 19
–
TCL - 12
–
ns
CC –
12
–
12
ns
CC –
8
–
8
ns
CC 0 + tA
8 + tA
0 + tA
8 + tA
ns
MUX/Tristate 3)
Running cycle1)
t32
CLKOUT
t33
t30
t29
t31
t34
ALE
Command
RD, WR
Figure 23
4)
2)
CLKOUT Timing
Notes
1)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2)
The leading edge of the respective command depends on RW-delay.
3)
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
4)
The next external bus cycle may start here.
Data Sheet
69
V1.0, 2003-01
C164CI-L16M3V
Low Power
Preliminary
Package Outlines
0.3 ±0.08
7˚ MAX.
H
0.65
0.88 ±0.15
C
12.35
0.15 +0.08
-0.02
2.45 MAX.
2 +0.1
-0.05
0.25 MIN.
P-MQFP-80-7
(Plastic Metric Quad Flat Package)
0.1
0.12 M A-B D C 80x
17.2
14 1)
0.2 A-B D 4x
0.2 A-B D H 4x
D
14 1)
17.2
B
A
80
1)
1
0.6 x 45˚
Does not include plastic or metal protrusion of 0.25 max. per side
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Data Sheet
70
GPM05249
Index Marking
Dimensions in mm
V1.0, 2003-01
http://www.infineon.com
Published by Infineon Technologies AG