Microcomputer Components 16-Bit CMOS Single-Chip Microcontroller C161RI Preliminary 05.98 Preliminary / e .d s n / e m tor e i s uc . w nd w /:/ w mico th tp se C161RI Revision History: Previous Releases: 1998-05-01 Preliminary 1998-01 Advance Information 1997-12 Advance Information Page Subjects 7 XTAL pin numbers (MQFP) corrected. 34 VDDMIN corrected, special threshold parameters added (VILS, VIHS, HYS). 35, 37 Specification of IIDO improved. 41 ADCTC value in converter timing example timing corrected. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Edition 1998-05-01 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1998. All Rights Reserved. Attention please! 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C166-Family of High-Performance CMOS 16-Bit Microcontrollers C161RI Preliminary C161RI 16-Bit Microcontroller ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● High Performance 16-bit CPU with 4-Stage Pipeline 125 ns Instruction Cycle Time at 16 MHz CPU Clock 625 ns Multiplication (16 × 16 bits), 1.25 µs Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL and Operating Systems Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Clock Generation via Prescaler or via Direct Clock Input Up to 8 MBytes Linear Address Space for Code and Data 1 KByte On-Chip Internal RAM (IRAM) 2 KBytes On-Chip Extension RAM (XRAM) Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/Data Bus 5 Programmable Chip-Select Signals 1024 Bytes On-Chip Special Function Register Area 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System, 11 External Interrupts 4-Channel 8-bit A/D Converter, conversion time down to 7.625 µs 2 Multi-Functional General Purpose Timer Units with five 16-bit Timers Synchronous/Asynchronous Serial Channel (USART) High-Speed Synchronous Serial Channel I2C Bus Interface (10-bit Addressing, 400 KHz) with 2 Channels (multiplexed) Up to 76 General Purpose I/O Lines Programmable Watchdog Timer On-Chip Real Time Clock Idle and Power Down Modes with Flexible Power Management Ambient temperature range – 40 to 85 °C Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstraploader 100-Pin MQFP / TQFP Package This document describes the SAB-C161RI-LM, the SAB-C161RI-LF, the SAF-C161RI-LM and the SAB-C161RI-LF. For simplicity all versions are referred to by the term C161RI throughout this document. Semiconductor Group 3 1998-05-01 C161RI Introduction The C161RI is a new derivative of the Siemens C166 Family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 8 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. The C161RI derivative is especially suited for cost sensitive applications. VDDVSS VAREFVAGND PORT0 16 bit XTAL1 XTAL2 PORT1 16 bit RSTIN RSTOUT NMI Port 2 8 bit C161RI EA Port 3 15 bit Port 4 7 bit ALE RD WR/WRL Port 6 8 bit Port 5 6 bit Figure 1 Logic Symbol Ordering Information The ordering code for Siemens microcontrollers provides an exact reference to the required product. This ordering code identifies: the derivative itself, i.e. its function set the specified temperature range the package the type of delivery. For the available ordering codes for the C161RI please refer to the “Product Information Microcontrollers”, which summarizes all available microcontroller variants. ● ● ● ● Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Semiconductor Group 4 1998-05-01 C161RI 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P5.1/AN1 P5.0/AN0 VAGND VAREF P2.15/EX7IN P2.14/EX6IN P2.13/EX5IN P2.12/EX4IN P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P2.8/EX0IN P6.7/SDA2 P6.6/SCL1 P6.5/SDA1 P6.4/CS4 P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.0/CS0 Pin Configuration MQFP Package (top view) C161RI 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NMI RSTOUT RSTIN VDD VSS P1H.7/A15 P1H.6/A14 P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 VDD VSS P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 P0H.1/AD9 P4.5/A21 P4.6/A22 RD WR/WRL READY ALE EA VSS VDD P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 VSS VDD P0H.0/AD8 P5.2/AN2 P5.3/AN3 P5.14/T4EUD P5.15/T2EUD VSS XTAL1 XTAL2 VDD P3.0/SCL0 P3.1/SDA0 P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TxD0 P3.11/RxD0 P3.12/BHE/WRH P3.13/SCLK P3.15/CLKOUT VSS VDD P4.0/A16 P4.1/A17 P4.2/A18 P4.3/A19 P4.4/A20 Figure 2 Semiconductor Group 5 1998-05-01 C161RI 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P5.3/AN3 P5.2/AN2 P5.1/AN1 P5.0/AN0 VAGND VAREF P2.15/EX7IN P2.14/EX6IN P2.13/EX5IN P2.12/EX4IN P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P2.8/EX0IN P6.7/SDA2 P6.6/SCL1 P6.5/SDA1 P6.4/CS4 P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.0/CS0 NMI RSTOUT RSTIN Pin Configuration TQFP Package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 C161RI 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD VSS P1H.7/A15 P1H.6/A14 P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 VDD VSS P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P4.2/A18 P4.3/A19 P4.4/A20 P4.5/A21 P4.6/A22 RD WR/WRL READY ALE EA VSS VDD P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 VSS VDD P0H.0/AD8 P0H.1/AD9 P0H.2/AD10 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P5.14/T4EUD P5.15/T2EUD VSS XTAL1 XTAL2 VDD P3.0/SCL0 P3.1/SDA0 P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TxD0 P3.11/RxD0 P3.12/BHE/WRH P3.13/SCLK P3.15/CLKOUT VSS VDD P4.0/A16 P4.1/A17 Figure 3 Semiconductor Group 6 1998-05-01 C161RI Pin Definitions and Functions Symbol Pin No. Pin No. Input Function TQFP MQFP Outp P5.0 – P5.3, P5.14 – P5.15 97 – 100, 1– 2 99 – 2, 3– 4 I I I I Port 5 is a 6-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 4) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x, x=0...3). The following pins of Port 5 also serve as timer inputs: P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input P5.15 T2EUD GPT1 Timer T5 Ext.Up/Down Ctrl.Input XTAL1 4 6 I XTAL1: XTAL2 5 7 O P3.0 – P3.13, P3.15 7– 20, 21 9– 22, 23 I/O I/O I/O 7 8 9 10 11 12 9 10 11 12 13 14 I/O I/O I O I I 13 14 15 16 I I 15 16 17 18 19 17 18 19 20 21 20 21 22 23 I/O I/O O I/O O O I/O O Semiconductor Group Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Port 3 is a 15-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The following Port 3 pins also serve for alternate functions: P3.0 SCL0 I2C Bus Clock Line 0 P3.1 SDA0 I2C Bus Data Line 0 P3.2 CAPIN GPT2 Register CAPREL Capture Input P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output P3.4 T3EUD GPT1 Timer T3 Ext.Up/Dwn Ctrl.Input P3.5 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture P3.8 MRST SSC Master-Rec./Slave-Transmit I/O P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I P3.10 T×D0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 R×D0 ASC0 Data Input (Asyn.) or I/O (Syn.) Ext. Memory High Byte Enable Signal, P3.12 BHE WRH Ext. Memory High Byte Write Strobe P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp. P3.15 CLKOUT System Clock Output (=CPU Clock) Note: Pins P3.0 and P3.1 are open drain outputs only. 7 1998-05-01 C161RI Pin Definitions and Functions (cont’d) Symbol Pin No. Pin No. Input Function TQFP MQFP Outp P4.0 – P4.6 24 – 30 26 32 I/O I/O 24 ... 30 26 ... 32 O ... O 31 33 O External Memory Read Strobe. RD is activated for every external instruction or data read access. WR/WRL 32 34 O External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. READY 33 35 I Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. ALE 34 36 O Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. EA 35 37 I External Access Enable pin. A low level at this pin during and after Reset forces the C161RI to begin instruction execution out of external memory. A high level forces execution out of the internal ROM. The C161RI must have this pin tied to ‘0’. Note: This pin is expected to be used to accept the programming voltage for OTP versions of the C161RI. RD Semiconductor Group Port 4 is a 7-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line ... ... ... P4.6 A22 Most Significant Segment Addr. Line 8 1998-05-01 C161RI Pin Definitions and Functions (cont’d) Symbol PORT0: P0L.0 – P0L.7, P0H.0 P0H.7 Pin No. Pin No. Input Function TQFP MQFP Outp 38 – 45, 48 – 55 I/O PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of external bus configurations, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 - D7 P0H.0 – P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7 P0H.0 – P0H.7: A8 - A15 AD8 - AD15 I/O PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. 40 – 47, 50 – 57 PORT1: P1L.0 – P1L.7, P1H.0 P1H.7 56 – 63, 66 – 73 58 65, 68 75 RSTIN 76 78 I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the C161RI. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN line is internally pulled low for the duration of the internal reset sequence upon a software reset, a WDT reset and a hardware reset. 1) RSTOUT 77 79 O Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. NMI 80 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C161RI to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. 78 Semiconductor Group 9 1998-05-01 C161RI Pin Definitions and Functions (cont’d) Symbol Pin No. Pin No. Input Function TQFP MQFP Outp P6.0 – P6.7 79 – 86 81 – 88 I/O I/O 79 ... 83 84 85 86 81 ... 85 86 87 88 O ... O I/O I/O I/O 87 – 94 89 – 96 I/O I/O 87 ... 94 89 ... 96 I ... I Port 2 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The following Port 2 pins also serve for alternate functions: P2.8 EX0IN Fast External Interrupt 0 Input ... ... ... P2.15 EX7IN Fast External Interrupt 7 Input VAREF 95 97 - Reference voltage for the A/D converter. VAGND 96 98 - Reference ground for the A/D converter. VDD 6, 23, 8, 25, 37, 47, 39, 49, 65, 75 67, 77 Digital Supply Voltage: + 5 V during normal operation and idle mode. ≥ 2.5 V during power down mode VSS 3, 22, 5, 24, 36, 46, 38, 48, 64, 74 66, 76 Digital Ground. P2.8 – P2.15 1) The Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The Port 6 pins also serve for alternate functions: Chip Select 0 Output P6.0 CS0 ... ... ... Chip Select 4 Output P6.4 CS4 P6.5 SDA1 I2C Bus Data Line 1 P6.6 SCL1 I2C Bus Clock Line 1 P6.7 SDA2 I2C Bus Data Line 2 Note: Pins P6.5-P6.7 are open drain outputs only. following behavior differences must be observed when the bidirectional reset is active: Bit BDRSTEN in register SYSCON cannot be changed after EINIT. After a reset bit BDRSTEN is cleared. The reset indication flags always indicate a long hardware reset. The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader may be activated when P0L.4 is low. ● Pin RSTIN may only be connected to external reset devices with an open drain output driver. ● A short hardware reset is extended to the duration of the internal reset sequence. ● ● ● ● Semiconductor Group 10 1998-05-01 C161RI Functional Description The C161RI is a low cost downgrade of the high performance microcontroller C167CR with OTP or internal ROM, reduced peripheral functionality and a high performance Capture Compare Unit with an additional functionality. The architecture of the C161RI combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C161RI. Note: All time specifications refer to a CPU clock of 16 MHz (see definition in the AC Characteristics section). QR &&RUH LQWHUQDO 520 'DWD &38&RUH &38 ,QVWU'DWD 'DWD W U R 3 ,QWHUQDO O D 5$0 X ' .%\WH 26& LQSXW0+] ;7$/ SUHVFDOHU 3(& RUGLUHFWGULYH ([WHUQDO,QVWU'DWD ,ð&%XV ,QWHUIDFH ;5$0 .%\WH W U R 3 W U R 3 V H V V H U G G $ D W D ' ,QWHUUXSW&RQWUROOHU :DWFKGRJ H[W,5 ,QWHUUXSW%XV 3HULSKHUDO'DWD ; 8 0 1 2 1 LW E 6 8 %; ([WHUQDO %XV 08; RQO\ ;%86 86$57 6\QF &KDQQHO &KDQQHO ELW 63, $'& &RQWURO &6/RJLF &6 $6& 66& %5* %5* *37 *37 7 7 7 7 57& 7 3RUW 3RUW 3RUW 3RUW 3RUW &5,9 Figure 4 Block Diagram Semiconductor Group 11 1998-05-01 C161RI Memory Organization The memory space of the C161RI is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable. 1 KByte of on-chip Internal RAM is provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C166 family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 8 MBytes of external RAM and/or ROM can be connected to the microcontroller. Semiconductor Group 12 1998-05-01 C161RI External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: – 16-/18-/20-/23-bit Addresses, 16-bit Data, Demultiplexed – 16-/18-/20-/23-bit Addresses, 16-bit Data, Multiplexed – 16-/18-/20-/23-bit Addresses, 8-bit Data, Multiplexed – 16-/18-/20-/23-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which allow to access different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported via a particular ‘Ready’ function. For applications which require less than 8 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines at all. It outputs all 7 address lines, if an address space of 8 MBytes is used. Semiconductor Group 13 1998-05-01 C161RI Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C161RI’s instructions can be executed in just one machine cycle which requires 125 ns at 16 MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. CPU Internal RAM SP STKOV STKUN MDH MDL R15 Exec. Unit Instr. Ptr. Instr. Reg. Mul/Div-HW Bit-Mask Gen General 4-Stage Pipeline R15 Purpose ALU 32 ROM 16 (16-bit) Barrel - Shifter Registers R0 PSW SYSCON Context Ptr. BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Data Page Ptr. Code Seg. Ptr. R0 16 MCB02147 Figure 5 CPU Block Diagram Semiconductor Group 14 1998-05-01 C161RI The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 1024 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C161RI instruction set which includes the following instruction classes: – – – – – – – – – – – – Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. Semiconductor Group 15 1998-05-01 C161RI Interrupt System With an interrupt response time within a range from just 315 ns to 750 ns (in case of internal program execution), the C161RI is capable of reacting very fast to the occurrence of nondeterministic events. The architecture of the C161RI supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C161RI has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number. Semiconductor Group 16 1998-05-01 C161RI The following table shows all of the possible C161RI interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Source of Interrupt or PEC Service Request Request Flag Enable Flag Interrupt Vector Vector Location Trap Number External Interrupt 0 CC8IR CC8IE CC8INT 00’0060H 18H External Interrupt 1 CC9IR CC9IE CC9INT 00’0064H 19H External Interrupt 2 CC10IR CC10IE CC10INT 00’0068H 1AH External Interrupt 3 CC11IR CC11IE CC11INT 00’006CH 1BH External Interrupt 4 CC12IR CC12IE CC12INT 00’0070H 1CH External Interrupt 5 CC13IR CC13IE CC13INT 00’0074H 1DH External Interrupt 6 CC14IR CC14IE CC14INT 00’0078H 1EH External Interrupt 7 CC15IR CC15IE CC15INT 00’007CH 1FH GPT1 Timer 2 T2IR T2IE T2INT 00’0088H 22H GPT1 Timer 3 T3IR T3IE T3INT 00’008CH 23H GPT1 Timer 4 T4IR T4IE T4INT 00’0090H 24H GPT2 Timer 5 T5IR T5IE T5INT 00’0094H 25H GPT2 Timer 6 T6IR T6IE T6INT 00’0098H 26H GPT2 CAPREL Register CRIR CRIE CRINT 00’009CH 27H A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0H 28H A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4H 29H ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8H 2AH ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011CH 47H ASC0 Receive S0RIR S0RIE S0RINT 00’00ACH 2BH ASC0 Error S0EIR S0EIE S0EINT 00’00B0H 2CH SSC Transmit SCTIR SCTIE SCTINT 00’00B4H 2DH SSC Receive SCRIR SCRIE SCRINT 00’00B8H 2EH SSC Error SCEIR SCEIE SCEINT 00’00BCH 2FH I C Data Transfer Event XP0IR XP0IE XP0INT 00’0100H 40H I2C Protocol Event XP1IR XP1IE XP1INT 00’0104H 41H X-Peripheral Node 2 XP2IR XP2IE XP2INT 00’0108H 42H PLL Unlock / RTC XP3IR XP3IE XP3INT 00’010CH 43H 2 Semiconductor Group 17 1998-05-01 C161RI The C161RI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during runtime: Exception Condition Trap Flag Trap Vector Vector Location Trap Number Trap Priority RESET RESET RESET 00’0000H 00’0000H 00’0000H 00H 00H 00H III III III NMI STKOF STKUF NMITRAP 00’0008H STOTRAP 00’0010H STUTRAP 00’0018H 02H 04H 06H II II II UNDOPC PRTFLT BTRAP BTRAP 00’0028H 00’0028H 0AH 0AH I I ILLOPA BTRAP 00’0028H 0AH I ILLINA ILLBUS BTRAP BTRAP 00’0028H 00’0028H 0AH 0AH I I Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved [2CH – 3CH] [0BH – 0FH] Software Traps TRAP Instruction Any [00’0000H – 00’01FCH] in steps of 4H Semiconductor Group 18 Any [00H – 7FH] Current CPU Priority 1998-05-01 C161RI General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 500 ns (@ 16 MHz CPU clock). The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking. In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals, so the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-flow/ underflow. The state of this latch may be output on a port pin (T3OUT) e.g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 are captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. With its maximum resolution of 250 ns (@ 16 MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler. The count direction (up/down) for each timer is programmable by software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5. The overflows/underflows of timer T6 can additionally be used to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin Semiconductor Group 19 1998-05-01 C161RI (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode. U/D T2EUD CPU Clock n 2 n = 3...10 T2 Mode Control T2IN CPU Clock Interrupt Request GPT1 Timer T2 Reload Capture Toggle FF n 2 n = 3...10 T3IN T3 Mode Control GPT1 Timer T3 T3OTL U/D T3EUD Interrupt Request Capture T4 Mode Control T4IN CPU Clock Reload n 2 n = 3...10 GPT1 Timer T4 U/D T4EUD Interrupt Request MCB02141 Figure 6 Block Diagram of GPT1 Semiconductor Group 20 1998-05-01 C161RI CPU Clock 2n n=2...9 T5 Mode Control Interrupt Request GPT2 Timer T5 Clear Capture CAPIN Interrupt Request GPT2 CAPREL Interrupt Request CPU Clock 2n n=2...9 T6 Mode Control GPT2 Timer T6 T6OTL Figure 7 Block Diagram of GPT2 Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 31 µs and 525 ms can be monitored (@ 16 MHz). The default Watchdog Timer interval after reset is 8.2 ms (@ 16 MHz). Semiconductor Group 21 1998-05-01 C161RI Real Time Clock The Real Time Clock (RTC) module of the C161RI consists of a chain of 3 divider blocks, a fixed 8-bit divider, the reloadable 16-bit timer T14 and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver and is therefore independent from the selected clock generation mode of the C161RI. All timers count up. The RTC module can be used for different purposes: ● System clock to determine the current time and date ● Cyclic time based interrupt ● 48-bit timer for long term measurements T14REL Reload T14 8:1 fRTC Interrupt Request RTCL RTCL Figure 7-1 RTC Block Diagram Note: The registers associated with the RTC are not effected by a reset in order to maintain the correct system time even when intermediate resets are executed. Semiconductor Group 22 1998-05-01 C161RI A/D Converter For analog signal measurement, an 8-bit A/D converter with 4 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. Overrun error detection is provided for the conversion result register (ADDAT): an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete. For applications which require less than 4 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the C161RI supports two different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. The 8-bit result can be left-aligned or right-aligned within a 10-bit result area. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. I2C Module The integrated I2C Bus Module handles the transmission and reception of frames over the two-line I2C bus in accordance with the I2C Bus specification. The on-chip I2C Module can receive and transmit data using 7-bit or 10-bit addressing and it can operate in slave mode, in master mode or in multi-master mode. Several physical interfaces (port pins) can be established under software control. Data can be transferred at speeds up to 400 Kbit/sec. Two interrupt nodes dedicated to the I2C module allow efficient interrupt service and also support operation via PEC transfers. Note: The port pins associated with the I2C interfaces feature open drain drivers only, as required by the I2C specification. Semiconductor Group 23 1998-05-01 C161RI Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 500 KBaud and half-duplex synchronous communication at up to 2 MBaud @ 16 MHz CPU clock. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. The SSC supports full-duplex synchronous communication at up to 4 Mbaud @ 16 MHz CPU clock. It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 3 separate interrupt vectors are provided. The SSC transmits or receives characters of 2…16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data. Semiconductor Group 24 1998-05-01 C161RI Parallel Ports The C161RI provides up to 76 IO lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three IO ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. The other IO ports operate in push/pull mode, except for the I2C interface pins which are open drain pins only. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A22/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter or timer control signals. Port 6 provides the optional chip select signals and interface lines for the I2C module. All port lines that are not used for these alternate functions may be used as general purpose IO lines. Semiconductor Group 25 1998-05-01 C161RI Instruction Set Summary The table below lists the instructions of the C161RI in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C166 Family Instruction Set Manual”. This document also provides a detailed description of each instruction. Instruction Set Summary Mnemonic Description Bytes ADD(B) Add word (byte) operands 2/4 ADDC(B) Add word (byte) operands with Carry 2/4 SUB(B) Subtract word (byte) operands 2/4 SUBC(B) Subtract word (byte) operands with Carry 2/4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (word/byte operands) 2/4 OR(B) Bitwise OR, (word/byte operands) 2/4 XOR(B) Bitwise XOR, (word/byte operands) 2/4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/L Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 CMP(B) Compare word (byte) operands 2/4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2/4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2/4 PRIOR Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR 2 SHL / SHR Shift left/right direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2 Semiconductor Group 26 1998-05-01 C161RI Instruction Set Summary (cont’d) Mnemonic Description Bytes MOV(B) Move word (byte) data 2/4 MOVBS Move byte operand to word operand with sign extension 2/4 MOVBZ Move byte operand to word operand. with zero extension 2/4 JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute to a code segment 4 J(N)B Jump relative if direct bit is (not) set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call absolute subroutine 4 TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack and update register with word operand 4 RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine 2 RETP Return from intra-segment subroutine and pop direct word register from system stack 2 RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4 SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT-pin 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2/4 EXTS(R) Begin EXTended Segment (and Register) sequence 2/4 NOP Null operation 2 Semiconductor Group 27 1998-05-01 C161RI Special Function Registers Overview The following table lists all SFRs which are implemented in the C161RI in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-Peripherals (I2C) are marked with the letter “X” in column “Physical Address”. An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). Name Physical 8-Bit Address Address Description Reset Value ADCIC b FF98H CCH A/D Converter End of Conversion Interrupt Control Register 0000H ADCON b FFA0H D0H A/D Converter Control Register 0000H ADDAT FEA0H 50H A/D Converter Result Register 0000H ADDRSEL1 FE18H 0CH Address Select Register 1 0000H ADDRSEL2 FE1AH 0DH Address Select Register 2 0000H ADDRSEL3 FE1CH 0EH Address Select Register 3 0000H ADDRSEL4 FE1EH 0FH Address Select Register 4 0000H b FF9AH CDH A/D Converter Overrun Error Interrupt Control Register 0000H BUSCON0 b FF0CH 86H Bus Configuration Register 0 0000H BUSCON1 b FF14H 8AH Bus Configuration Register 1 0000H BUSCON2 b FF16H 8BH Bus Configuration Register 2 0000H BUSCON3 b FF18H 8CH Bus Configuration Register 3 0000H BUSCON4 b FF1AH 8DH Bus Configuration Register 4 0000H CAPREL FE4AH 25H GPT2 Capture/Reload Register 0000H CC8IC b FF88H C4H External Interrupt 0 Control Register 0000H CC9IC b FF8AH C5H External Interrupt 1 Control Register 0000H CC10IC b FF8CH C6H External Interrupt 2 Control Register 0000H CC11IC b FF8EH C7H External Interrupt 3 Control Register 0000H CC12IC b FF90H C8H External Interrupt 4 Control Register 0000H CC13IC b FF92H C9H External Interrupt 5 Control Register 0000H CC14IC b FF94H CAH External Interrupt 6 Control Register 0000H CC15IC b FF96H CBH External Interrupt 7 Control Register 0000H FE10H 08H CPU Context Pointer Register FC00H ADEIC CP Semiconductor Group 28 1998-05-01 C161RI Name CRIC CSP Physical 8-Bit Address Address Description Reset Value b FF6AH B5H GPT2 CAPREL Interrupt Control Register 0000H FE08H 04H CPU Code Segment Pointer Register (8 bits, not directly writeable) 0000H DP0L b F100H E 80H P0L Direction Control Register 00H DP0H b F102H E 81H P0H Direction Control Register 00H DP1L b F104H E 82H P1L Direction Control Register 00H DP1H b F106H E 83H P1H Direction Control Register 00H DP2 b FFC2H E1H Port 2 Direction Control Register 0000H DP3 b FFC6H E3H Port 3 Direction Control Register 0000H DP4 b FFCAH E5H Port 4 Direction Control Register 00H DP6 b FFCEH E7H Port 6 Direction Control Register 00H DPP0 FE00H 00H CPU Data Page Pointer 0 Register (10 bits) 0000H DPP1 FE02H 01H CPU Data Page Pointer 1 Register (10 bits) 0001H DPP2 FE04H 02H CPU Data Page Pointer 2 Register (10 bits) 0002H DPP3 FE06H 03H CPU Data Page Pointer 3 Register (10 bits) 0003H External Interrupt Control Register 0000H EXICON b F1C0H E E0H ICADR ED06H X --- I2C Address Register 0XXXH ICCFG ED00H X --- I2C Configuration Register XX00H ICCON ED02H X --- I2C Control Register 0000H ICRTB ED08H X --- I2C Receive/Transmit Buffer ICST ED04H X --- I2C Status Register 0000H IDCHIP F07CH E 3EH Identifier 09XXH IDMANUF F07EH E 3FH Identifier 1820H IDMEM F07AH E 3DH Identifier 0000H IDPROG F078H E 3CH Identifier 0000H XXH ISNC b F1DEH E EFH Interrupt Subnode Control Register 0000H MDC b FF0EH 87H CPU Multiply Divide Control Register 0000H MDH FE0CH 06H CPU Multiply Divide Register – High Word 0000H MDL FE0EH 07H CPU Multiply Divide Register – Low Word 0000H ODP2 b F1C2H E E1H Port 2 Open Drain Control Register 0000H ODP3 b F1C6H E E3H Port 3 Open Drain Control Register 0000H ODP6 b F1CEH E E7H Port 6 Open Drain Control Register 00H ONES b FF1EH Constant Value 1’s Register (read only) Semiconductor Group 8FH 29 FFFFH 1998-05-01 C161RI Name Physical 8-Bit Address Address Description Reset Value P0L b FF00H 80H Port 0 Low Register (Lower half of PORT0) 00H P0H b FF02H 81H Port 0 High Register (Upper half of PORT0) 00H P1L b FF04H 82H Port 1 Low Register (Lower half of PORT1) 00H P1H b FF06H 83H Port 1 High Register (Upper half of PORT1) 00H P2 b FFC0H E0H Port 2 Register 0000H P3 b FFC4H E2H Port 3 Register 0000H P4 b FFC8H E4H Port 4 Register (7 bits) P5 b FFA2H D1H Port 5 Register (read only) P5DIDIS b FFA4H D2H Port 5 Digital Input Disable Register P6 b FFCCH E6H Port 6 Register (8 bits) PECC0 FEC0H 60H PEC Channel 0 Control Register 0000H PECC1 FEC2H 61H PEC Channel 1 Control Register 0000H PECC2 FEC4H 62H PEC Channel 2 Control Register 0000H PECC3 FEC6H 63H PEC Channel 3 Control Register 0000H PECC4 FEC8H 64H PEC Channel 4 Control Register 0000H PECC5 FECAH 65H PEC Channel 5 Control Register 0000H PECC6 FECCH 66H PEC Channel 6 Control Register 0000H PECC7 FECEH 67H PEC Channel 7 Control Register 0000H 88H CPU Program Status Word 0000H 00H XXXXH 0000H 00H PSW b FF10H RP0H b F108H E 84H RTCH F0D6H E 6BH RTC High Register no RTCL F0D4H E 6AH RTC Low Register no S0BG FEB4H 5AH Serial Channel 0 Baud Rate Generator Reload Register 0000H S0CON b FFB0H D8H Serial Channel 0 Control Register 0000H S0EIC b FF70H B8H Serial Channel 0 Error Interrupt Control Register 0000H FEB2H 59H Serial Channel 0 Receive Buffer Register (read only) XXXXH S0RIC b FF6EH B7H Serial Channel 0 Receive Interrupt Control Register 0000H S0TBIC b F19CH E CEH Serial Channel 0 Transmit Buffer Interrupt Control Register 0000H Serial Channel 0 Transmit Buffer Register 0000H S0RBUF S0TBUF FEB0H Semiconductor Group 58H System Startup Configuration Register (Rd. only) 30 XXH 1998-05-01 C161RI Name S0TIC Physical 8-Bit Address Address Description Reset Value b FF6CH B6H Serial Channel 0 Transmit Interrupt Control Register 0000H SP FE12H 09H CPU System Stack Pointer Register FC00H SSCBR F0B4H E 5AH SSC Baudrate Register 0000H SSCCON b FFB2H D9H SSC Control Register 0000H SSCEIC b FF76H BBH SSC Error Interrupt Control Register 0000H SSCRB SSCRIC SSCTB F0B2H E 59H b FF74H BAH F0B0H E 58H SSC Receive Buffer (read only) XXXXH SSC Receive Interrupt Control Register 0000H SSC Transmit Buffer (write only) 0000H SSCTIC b FF72H B9H SSC Transmit Interrupt Control Register 0000H STKOV FE14H 0AH CPU Stack Overflow Pointer Register FA00H STKUN FE16H 0BH CPU Stack Underflow Pointer Register FC00H b FF12H 89H CPU System Configuration Register SYSCON 0XX0H1) SYSCON2 b F1D0H E E8H CPU System Configuration Register 2 0000H SYSCON3 b F1D4H E EAH CPU System Configuration Register 3 0000H T14 F0D2H E 69H RTC Timer 14 Register no T14REL F0D0H E 68H RTC Timer 14 Reload Register no T2 FE40H 20H GPT1 Timer 2 Register 0000H T2CON b FF40H A0H GPT1 Timer 2 Control Register 0000H T2IC b FF60H B0H GPT1 Timer 2 Interrupt Control Register 0000H FE42H 21H GPT1 Timer 3 Register 0000H T3CON b FF42H A1H GPT1 Timer 3 Control Register 0000H T3IC b FF62H B1H GPT1 Timer 3 Interrupt Control Register 0000H FE44H 22H GPT1 Timer 4 Register 0000H T4CON b FF44H A2H GPT1 Timer 4 Control Register 0000H T4IC b FF64H B2H GPT1 Timer 4 Interrupt Control Register 0000H FE46H 23H GPT2 Timer 5 Register 0000H T5CON b FF46H A3H GPT2 Timer 5 Control Register 0000H T5IC b FF66H B3H GPT2 Timer 5 Interrupt Control Register 0000H FE48H 24H GPT2 Timer 6 Register 0000H T6CON b FF48H A4H GPT2 Timer 6 Control Register 0000H T6IC b FF68H B4H GPT2 Timer 6 Interrupt Control Register 0000H TFR b FFACH D6H Trap Flag Register 0000H T3 T4 T5 T6 Semiconductor Group 31 1998-05-01 C161RI Name Physical 8-Bit Address Address Description Reset Value WDT FEAEH 57H Watchdog Timer Register (read only) WDTCON b FFAEH D7H Watchdog Timer Control Register 00XXH2) 0000H XP0IC b F186H E C3H I2C Data Interrupt Control Register 0000H XP1IC b F18EH E C7H I2C Protocol Interrupt Control Register 0000H XP2IC b F196H E CBH X-Peripheral 2 Interrupt Control Register 0000H XP3IC b F19EH E CFH RTC Interrupt Control Register 0000H ZEROS b FF1CH Constant Value 0’s Register (read only) 0000H 8EH 1) The system configuration is selected during reset. 2) The reset value depends on the indicated reset source. Semiconductor Group 32 1998-05-01 C161RI Absolute Maximum Ratings Ambient temperature under bias (TA): SAB-C161RI ...................................................................................................................0 to + 70 °C SAF-C161RI ..............................................................................................................– 40 to + 85 °C Storage temperature (TST)........................................................................................– 65 to + 150 °C Voltage on VDD pins with respect to ground (VSS) ..................................................... – 0.5 to + 6.5 V Voltage on any pin with respect to ground (VSS) .................................................– 0.5 to VDD + 0.5 V Input current on any pin during overload condition.................................................. – 10 to + 10 mA Absolute sum of all input currents during overload condition ..............................................|100 mA| Power dissipation..................................................................................................................... 1.5 W Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C161RI and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the C161RI will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the C161RI. Semiconductor Group 33 1998-05-01 C161RI DC Characteristics VDD = 4.5 - 5.5 V; VSS = 0 V; fCPU = 20 MHz TA = 0 to + 70 °C for SAB-C161RI TA = – 40 to + 85 °C for SAF-C161RI Parameter Symbol Limit Values min. max. Unit Test Condition Input low voltage (P3.0, P3.1, P6.5, P6.6, P6.7) VIL1 SR – 0.5 0.3 VDD V – Input low voltage (TTL) VIL SR – 0.5 0.2 VDD – 0.1 V – Input low voltage (Special Threshold) VILS SR – 0.5 2.0 V – Input high voltage RSTIN VIH1 SR 0.6 VDD VDD + 0.5 V – Input high voltage XTAL1, P3.0, P3.1, P6.5, P6.6, P6.7 VIH2 SR 0.7 VDD VDD + 0.5 V – Input high voltage (TTL) VIH SR 0.2 VDD + 0.9 VDD + 0.5 V – Input high voltage (Special Threshold) VIHS SR 0.8 VDD – 0.2 VDD + 0.5 V – Input Hysteresis (Special Threshold) HYS 400 – mV – CC – 0.45 V IOL = 2.4 mA Output low voltage VOL (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (P3.0, P3.1, P6.5, P6.6, P6.7) VOL2 CC – 0.4 V IOL2 = 3 mA Output low voltage (all other outputs) VOL1 CC – 0.45 V IOL1 = 1.6 mA 0.9 VDD 2.4 – V IOH = – 500 µA IOH = – 2.4 mA 0.9 VDD 2.4 – V V IOH = – 250 µA IOH = – 1.6 mA Output high voltage VOH (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) 1) CC VOH1 CC Input leakage current (Port 5) IOZ1 CC – ± 200 nA 0.45 V < VIN < VDD Input leakage current (all other) IOZ2 CC – ± 500 nA 0.45 V < VIN < VDD Overload current IOV SR – ±5 mA 5) 8) RSTIN pullup resistor RRST CC 50 250 kΩ – Output high voltage (all other outputs) Read/Write inactive current Read/Write active current Semiconductor Group 4) 4) IRWH 2) – – 40 µA VOUT = 2.4 V IRWL 3) – 500 – µA VOUT = VOLmax 34 1998-05-01 C161RI Parameter Symbol ALE inactive current ALE active current 4) 4) Port 6 inactive current Port 6 active current 4) 4) PORT0 configuration current 4) Limit Values min. max. Unit Test Condition IALEL 2) – 40 µA VOUT = VOLmax IALEH 3) 500 – µA VOUT = 2.4 V IP6H 2) – – 40 µA VOUT = 2.4 V IP6L 3) – 500 – µA VOUT = VOL1max IP0H 2) – – 10 µA VIN = VIHmin IP0L 3) – 100 – µA VIN = VILmax XTAL1 input current IIL CC – ± 20 µA 0 V < VIN < VDD Pin capacitance 5) (digital inputs/outputs) CIO CC – 10 pF f = 1 MHz TA = 25 °C Power supply current (active) with all peripherals active IDD – 7+ 3 × fCPU mA RSTIN = VIL2 fCPU in [MHz] 6) Idle mode supply current with all peripherals active IIDX – 3+ 1.1 × fCPU mA RSTIN = VIH1 fCPU in [MHz] 6) Idle mode supply current with all peripherals deactivated, PLL off, SDD factor = 32 IIDO – 500 + µA 50 × fOSC 9) RSTIN = VIH1 fOSC in [MHz] 6) Power-down mode supply current with RTC running IPDR – 100 + µA 9) 25 × fOSC VDD = 5.5 V fOSC in [MHz] 7) Power-down mode supply current with RTC disabled IPDO – 50 Semiconductor Group 35 µA VDD = 5.5 V 7) 1998-05-01 C161RI Notes 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2) The maximum current may be drawn while the respective signal line remains inactive. 3) The minimum current must be drawn in order to drive the respective signal line active. 4) This specification is only valid during Reset, or during Adapt-mode. 5) Not 100% tested, guaranteed by design characterization. 6) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VDDmax and 20 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The oscillator also contributes to the total supply current. The given values refer to the worst case, i.e. IPDRmax. For lower oscillator frequencies the respective supply current can be reduced accordingly. 7) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD – 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected. 8) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage (VDD and VSS) must remain within the specified limits. 9) This parameter is determined mainly by the current consumed by the oscillator. This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given for IPDR refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. A typical value for IPDR at room temperature and fCPU = 16 MHz is 300 µA. Semiconductor Group 36 1998-05-01 I [mA] C161RI IDDmax 70 IDDtyp 40 IIDXmax IIDXtyp 10 5 10 15 20 fCPU [MHz] I [µA] Figure 8 Supply/Idle Current as a Function of Operating Frequency 1500 IIDOmax 1250 1000 IIDOtyp 750 IPDRmax 500 250 IPDOmax 4 8 12 16 fOSC [MHz] Figure 9 Power Down Supply Current as a Function of Oscillator Frequency Semiconductor Group 37 1998-05-01 C161RI AC Characteristics Definition of Internal Timing The internal operation of the C161RI is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see figure below). Direct Clock Drive fXTAL fCPU TCL TCL Prescaler Operation fXTAL fCPU TCL TCL Figure 10 Generation Mechanisms for the CPU Clock The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate fCPU. This influence must be regarded when calculating the timings for the C161RI. The used mechanism to generate the CPU clock is selected during reset via the logic levels on pins P0.15-13 (P0H.7-5). Semiconductor Group 38 1998-05-01 C161RI The table below associates the combinations of these three bits with the respective clock generation mode. C161RI Clock Generation Modes P0.15-13 (P0H.7-5) 1) CPU Frequency fCPU = Notes fXTAL × F 1 1 1 Reserved 1 1 0 Reserved 1 0 1 Reserved 1 0 0 Reserved 0 1 1 fXTAL × 1 0 1 0 Reserved 0 0 1 fXTAL / 2 0 0 0 Reserved Default configuration without pull-downs Direct drive 1) CPU clock via prescaler The maximum frequency depends on the duty cycle of the external clock signal. Prescaler Operation When pins P0.15-13 (P0H.7-5) equal ‘001’ during reset the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fXTAL. The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of fXTAL for any TCL. Direct Drive When pins P0.15-13 (P0H.7-5) equal ‘011’ during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: TCLmin = 1/fXTAL × DCmin (DC = duty cycle) For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/fXTAL. Note: The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL × DCmax) instead of TCLmin. Semiconductor Group 39 1998-05-01 C161RI AC Characteristics External Clock Drive XTAL1 VDD = 4.5 - 5.5 V; VSS = 0 V TA = 0 to + 70 °C for SAB-C161RI TA = – 40 to + 85 °C for SAF-C161RI Parameter Symbol Direct Drive 1:1 max. min. max. 8000 31 4000 ns 6 – ns 6 – tOSC SR 62 High time t1 SR 25 1) 2) – 1) 2) – t2 SR 25 1) Rise time t3 SR – 10 Fall time t4 SR – 10 1) 1) 2) Unit min. Oscillator period Low time Prescaler 2:1 ns – 6 1) ns – 6 1) ns The clock input signal must reach the defined levels VIL and VIH2. The specified minimum low and high times allow a duty cycle range of 40...60% at 16 MHz. t1 t3 t4 VIH2 0.5 VDD VIL t2 t OSC MCT02534 Figure 11 External Clock Drive XTAL1 Semiconductor Group 40 1998-05-01 C161RI A/D Converter Characteristics VDD = 4.5 - 5.5 V; VSS = 0 V TA = 0 to + 70 °C for SAB-C161RI TA = – 40 to + 85 °C for SAF-C161RI 4.0 V ≤ VAREF ≤ VDD + 0.1 V; VSS - 0.1 V ≤ VAGND ≤ VSS + 0.2 V Parameter Symbol Limit Values min. Unit Test Condition max. Analog input voltage range VAIN SR VAGND VAREF V 1) Basic clock frequency fBC 4 MHz 2) Sample time tS CC – 6 tBC tBC = 1 / fBC Conversion time tC CC – 30 tBC + 2 tCPU 3) 0.5 tCPU = 1 / fCPU Total unadjusted error TUE CC – ±2 LSB 4) Internal resistance of reference voltage source RAREF SR – tBC / 125 kΩ tBC in [ns] 5) 6) Internal resistance of analog source RASRC SR – kΩ tS in [ns] 6) 7) ADC input capacitance CAIN CC – pF 6) - 0.25 tS / 750 - 0.25 50 The conversion time of the C161RI’s A/D Converter is programmable. The table below should be used to calculate the above timings. The limit values for fBC must not be exceeded when selecting ADCTC. ADCON.15|14 A/D Converter Basic Clock (ADCTC) fBC 2) 00 fCPU / 2 01 fCPU / 4 10 fCPU / 8 11 fCPU / 16 Converter Timing Example: Assumptions: fCPU = 16 MHz (i.e. tCPU = 62.5 ns), ADCTC = ‘01’. Basic clock fBC Sample time tS Conversion time tC Semiconductor Group = fCPU / 4 = 4 MHz, i.e. tBC = 250 ns. = tBC × 6 = 1500 ns. = 30 tBC + 2 tCPU = (7500 + 125) ns = 7.625 µs. 41 1998-05-01 C161RI Notes 1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. 2) The limit values for fBC must not be exceeded when selecting the CPU frequency and the ADCTC setting. 3) This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the basic clock tBC depend on programming and can be taken from the table above. This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. 4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. 5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within each conversion step. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, guaranteed by design. 7) During the sample time the input capacitance CI can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample time tS depend on programming and can be taken from the table above. Semiconductor Group 42 1998-05-01 C161RI Testing Waveforms AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.45 V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 12 Input Output Waveforms For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20 mA). Figure 13 Float Waveforms Semiconductor Group 43 1998-05-01 C161RI Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description Symbol Values ALE Extension tA TCL × <ALECTL> Memory Cycle Time Waitstates tC 2TCL × (15 - <MCTC>) Memory Tristate Time tF 2TCL × (1 - <MTTC>) AC Characteristics Multiplexed Bus VDD = 4.5 - 5.5 V; VSS = 0 V TA = 0 to + 70 °C for SAB-C161RI TA = – 40 to + 85 °C for SAF-C161RI CL = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (186 ns at 16 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 16 MHz Variable CPU Clock 1/2TCL = 1 to 16 MHz min. max. min. Unit max. CC 21 + tA – TCL - 10 + tA – ns Address setup to ALE t5 t6 CC 15 + tA – TCL - 16 + tA – ns Address hold after ALE t7 CC 21 + tA – TCL - 10 + tA – ns ALE falling edge to RD, WR (with RW-delay) t8 CC 21 + tA – TCL - 10 + tA – ns ALE falling edge to RD, WR (no RW-delay) t9 CC – 10 + tA – – 10 + tA – ns Address float after RD, WR (with RW-delay) t10 CC – 6 – 6 ns Address float after RD, WR (no RW-delay) t11 CC – 37 – TCL + 6 ns RD, WR low time (with RW-delay) t12 CC 53 + tC – 2TCL - 10 + tC – ns RD, WR low time (no RW-delay) t13 CC 84 + tC – 3TCL - 10 + tC – ns ALE high time Semiconductor Group 44 1998-05-01 C161RI Parameter Symbol Max. CPU Clock = 16 MHz Variable CPU Clock 1/2TCL = 1 to 16 MHz min. max. min. max. Unit RD to valid data in (with RW-delay) t14 SR – 43 + tC – 2TCL - 20 + tC ns RD to valid data in (no RW-delay) t15 SR – 74 + tC – 3TCL - 20 + tC ns ALE low to valid data in t16 SR – 74 + tA + tC – 3TCL - 20 + tA + tC ns Address to valid data in t17 SR – 95 + 2t A + t C – 4TCL - 30 + 2tA + tC ns Data hold after RD rising edge t18 SR 0 – 0 – ns Data float after RD t19 SR – 49 + tF – 2TCL - 14 + tF ns Data valid to WR t22 CC 43 + tC – 2TCL - 20 + tC – ns Data hold after WR t23 CC 49 + tF – 2TCL - 14 + tF – ns ALE rising edge after RD, WR t25 CC 49 + tF – 2TCL - 14 + tF – ns Address hold after RD, WR t27 CC 49 + tF – 2TCL - 14 + tF – ns ALE falling edge to CS t38 CC – 4 - tA 10 - tA – 4 - tA 10 - tA ns CS low to Valid Data In t39 SR – 74 + tC + 2tA – 3TCL - 20 + tC + 2tA ns CS hold after RD, WR t40 CC 80 + tF – 3TCL - 14 + tF – ns ALE fall. edge to RdCS, WrCS (with RW delay) t42 CC 27 + tA – TCL - 4 + tA – ns ALE fall. edge to RdCS, WrCS (no RW delay) t43 CC – 4 + tA – -4 + tA – ns Address float after RdCS, WrCS (with RW delay) t44 CC – 0 – 0 ns Address float after RdCS, WrCS (no RW delay) t45 CC – 31 – TCL ns RdCS to Valid Data In (with RW delay) t46 SR – 39 + tC – 2TCL - 24 + tC ns Semiconductor Group 45 1998-05-01 C161RI Parameter Symbol Max. CPU Clock = 16 MHz Variable CPU Clock 1/2TCL = 1 to 16 MHz min. max. min. max. Unit RdCS to Valid Data In (no RW delay) t47 SR – 70 + tC – 3TCL - 24 + tC ns RdCS, WrCS Low Time (with RW delay) t48 CC 53 + tC – 2TCL - 10 + tC – ns RdCS, WrCS Low Time (no RW delay) t49 CC 84 + tC – 3TCL - 10 + tC – ns Data valid to WrCS t50 CC 49 + tC – 2TCL - 14 + tC – ns Data hold after RdCS t51 SR 0 – 0 – ns Data float after RdCS t52 SR – 43 + tF – 2TCL - 20 + tF ns Address hold after RdCS, WrCS t54 CC 43 + tF – 2TCL - 20 + tF – ns Data hold after WrCS t56 CC 43 + tF – 2TCL - 20 + tF – ns Semiconductor Group 46 1998-05-01 C161RI t5 t16 t25 ALE t38 t39 t40 CSx t17 A23-A16 (A15-A8) BHE t27 Address t6 t7 t54 t19 Read Cycle BUS t18 Address t8 Data In t10 t14 RD t42 t44 t12 t51 t52 t46 RdCSx t48 Write Cycle BUS t23 Address t8 Data Out t56 t10 t22 WR, WRL, WRH t42 t12 t44 t50 WrCSx t48 Figure 14-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group 47 1998-05-01 C161RI t5 t16 t25 t39 t40 t17 t27 ALE t38 CSx A23-A16 (A15-A8) BHE Address t6 t7 t54 t19 Read Cycle BUS t18 Address Data In t10 t8 t14 RD t44 t42 t12 t51 t52 t46 RdCSx t48 Write Cycle BUS t23 Address Data Out t56 t10 t8 WR, WRL, WRH t44 t42 t22 t12 t50 WrCSx t48 Figure 14-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group 48 1998-05-01 C161RI t5 t16 t25 ALE t38 t39 t40 CSx t17 A23-A16 (A15-A8) BHE t27 Address t6 t7 t54 t19 Read Cycle BUS t18 Address t9 t11 RD t43 Data In t15 t13 t45 RdCSx t51 t52 t47 t49 Write Cycle BUS t23 Address t9 Data Out t56 t11 t22 WR, WRL, WRH t43 t13 t45 t50 WrCSx t49 Figure 14-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group 49 1998-05-01 C161RI t5 t16 t25 t39 t40 t17 t27 ALE t38 CSx A23-A16 (A15-A8) BHE Address t6 t7 t54 t19 Read Cycle BUS t18 Address Data In t9 t11 RD t15 t13 t43 t45 RdCSx t51 t52 t47 t49 Write Cycle BUS t23 Address Data Out t56 t9 t11 WR, WRL, WRH t22 t13 t43 t45 t50 WrCSx t49 Figure 14-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group 50 1998-05-01 C161RI AC Characteristics Demultiplexed Bus VDD = 4.5 - 5.5 V; VSS = 0 V TA = 0 to + 70 °C for SAB-C161RI TA = – 40 to + 85 °C for SAF-C161RI CL = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (125 ns at 16 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 16 MHz Variable CPU Clock 1/2TCL = 1 to 16 MHz min. max. min. Unit max. t5 t6 CC 21 + tA – TCL - 10 + tA – ns CC 15 + tA – TCL - 16 + tA – ns ALE falling edge to RD, WR (with RW-delay) t8 CC 21 + tA – TCL - 10 + tA – ns ALE falling edge to RD, WR (no RW-delay) t9 CC – 10 + tA – – 10 + tA – ns RD, WR low time (with RW-delay) t12 CC 53 + tC – 2TCL - 10 + tC – ns RD, WR low time (no RW-delay) t13 CC 84 + tC – 3TCL - 10 + tC – ns RD to valid data in (with RW-delay) t14 SR – 43 + tC – 2TCL - 20 + tC ns RD to valid data in (no RW-delay) t15 SR – 74 + tC – 3TCL - 20 + tC ns ALE low to valid data in t16 SR – 74 + tA + tC – 3TCL - 20 + tA + tC ns Address to valid data in t17 SR – 95 + 2t A + t C – 4TCL - 30 + 2tA + tC ns Data hold after RD rising edge t18 SR 0 – 0 – ns Data float after RD rising edge (with RW-delay 1)) t20 SR – 49 + 2tA + tF 1) – 2TCL - 14 + 2tA + tF 1) ns Data float after RD rising edge (no RW-delay 1)) t21 SR – 21 + 2tA + tF 1) – TCL - 10 + 2tA + tF 1) ns Data valid to WR t22 CC 43 + tC – 2TCL - 20 + tC – ns Data hold after WR t24 CC 21 + tF – TCL - 10 + tF – ns ALE rising edge after RD, WR t26 CC – 10 + tF – – 10 + tF ns ALE high time Address setup to ALE Semiconductor Group 51 – 1998-05-01 C161RI Parameter Symbol 2) Max. CPU Clock = 16 MHz Variable CPU Clock 1/2TCL = 1 to 16 MHz min. max. min. max. Unit t28 CC 0 + tF – 0 + tF – ns ALE falling edge to CS t38 CC – 4 - tA 10 - tA – 4 - tA 10 - tA ns CS low to Valid Data In t39 SR – 74 + tC + 2tA – 3TCL - 20 + tC + 2tA ns CS hold after RD, WR t41 CC 17 + tF – TCL - 14 + tF – ns ALE falling edge to RdCS, WrCS (with RW-delay) t42 CC 27 + tA – TCL - 4 + tA – ns ALE falling edge to RdCS, WrCS (no RW-delay) t43 CC – 4 + tA – –4 + tA – ns RdCS to Valid Data In (with RW-delay) t46 SR – 39 + tC – 2TCL - 24 + tC ns RdCS to Valid Data In (no RW-delay) t47 SR – 70 + tC – 3TCL - 24 + tC ns RdCS, WrCS Low Time (with RW-delay) t48 CC 53 + tC – 2TCL - 10 + tC – ns RdCS, WrCS Low Time (no RW-delay) t49 CC 84 + tC – 3TCL - 10 + tC – ns Data valid to WrCS t50 CC 49 + tC – 2TCL - 14 + tC – ns Data hold after RdCS t51 SR 0 – 0 – ns Data float after RdCS (with RW-delay) t53 SR – 43 + tF – 2TCL - 20 + tF ns Data float after RdCS (no RW-delay) t68 SR – 11 + tF – TCL - 20 + tF ns Address hold after RdCS, WrCS t55 CC – 10 + tF – – 10 + tF – ns Data hold after WrCS t57 CC 17 + tF – TCL - 14 + tF – ns Address hold after WR 1) 2) RW-delay and tA refer to the next following bus cycle. It is guaranteed by design that read data are latched before the address changes. Semiconductor Group 52 1998-05-01 C161RI t5 t16 t26 ALE t38 t39 t41 CSx t17 A23-A16 A15-A0 BHE t28 Address t6 t55 t20 Read Cycle BUS (D15-D8) D7-D0 t18 Data In t8 t14 RD t12 t42 RdCSx t51 t53 t46 t48 Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH t24 Data Out t57 t8 t22 t12 t42 t50 WrCSx t48 Figure 15-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group 53 1998-05-01 C161RI t5 t16 t26 ALE t38 t39 t41 CSx t17 A23-A16 A15-A0 BHE t28 Address t6 t55 t20 Read Cycle BUS (D15-D8) D7-D0 t18 Data In t8 t14 RD t12 t42 t51 t53 t46 RdCSx t48 Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH t24 Data Out t57 t8 t22 t12 t42 t50 WrCSx t48 Figure 15-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group 54 1998-05-01 C161RI t5 t16 t26 ALE t38 t39 t41 CSx t17 A23-A16 A15-A0 BHE t28 Address t6 t55 t21 Read Cycle BUS (D15-D8) D7-D0 t18 Data In t9 t15 RD t43 t13 t51 t68 t47 RdCSx t49 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t57 t9 t22 WR, WRL, WRH t13 t43 t50 WrCSx t49 Figure 15-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group 55 1998-05-01 C161RI t5 t16 t26 ALE t38 t39 t41 CSx t17 A23-A16 A15-A0 BHE t28 Address t6 t55 t21 Read Cycle BUS (D15-D8) D7-D0 t18 Data In t9 t15 RD t13 t43 t51 t68 t47 RdCSx t49 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t57 t9 t22 WR, WRL, WRH t13 t43 t50 WrCSx t49 Figure 15-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group 56 1998-05-01 C161RI AC Characteristics CLKOUT and READY VDD = 4.5 - 5.5 V; VSS = 0 V TA = 0 to + 70 °C for SAB-C161RI TA = – 40 to + 85 °C for SAF-C161RI CL = 100 pF Parameter Symbol Max. CPU Clock = 16 MHz Variable CPU Clock 1/2TCL = 1 to 16 MHz min. max. min. max. Unit CC 62 62 2TCL 2TCL ns CLKOUT high time t29 t30 CC 25 – TCL – 6 – ns CLKOUT low time t31 CC 21 – TCL – 10 – ns CLKOUT rise time t32 CC – 4 – 4 ns CLKOUT fall time t33 CC – 4 – 4 ns CLKOUT rising edge to ALE falling edge t34 CC 0 + tA 10 + tA 0 + tA 10 + tA ns Synchronous READY setup time to CLKOUT t35 SR 14 – 14 – ns Synchronous READY hold time after CLKOUT t36 SR 4 – 4 – ns Asynchronous READY low time t37 SR 76 – 2TCL + 14 – ns Asynchronous READY setup time 1) t58 SR 14 – 14 – ns Asynchronous READY hold time 1) t59 SR 4 – 4 – ns Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) t60 SR 0 1 + 2tA + tC + tF 2) 0 TCL - 30 ns + 2tA + tC + tF CLKOUT cycle time 2) Notes 1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle. Semiconductor Group 57 1998-05-01 C161RI READY waitstate Running cycle 1) CLKOUT t32 MUX/Tristate 6) t33 t30 t29 t31 t34 ALE 7) Command RD, WR 2) t35 Sync READY t36 t35 3) 3) t58 Async READY t59 t36 t58 t60 4) t59 3) 3) 5) t37 see 6) Figure 16 CLKOUT and READY Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the respective command depends on RW-delay. 3) READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4) READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). 5) If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (eg. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in reponse to the command (see Note 4)). 6) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 7) The next external bus cycle may start here. Semiconductor Group 58 1998-05-01 C161RI Package Outlines Plastic Package, P-MQFP-100-2 (SMD) (Plastic Metric Quad Flat Package) Figure 17 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 59 Dimensions in mm 1998-05-01 C161RI Package Outlines (cont’d) Plastic Package, P-TQFP-100-1 (SMD) (Plastic Thin Metric Quad Flat Package) Figure 18 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 60 Dimensions in mm 1998-05-01