mcu-an-cm25-00103-3

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
CM25-00103-3E
F2MC-8L
8-BIT MICROCONTROLLERS
APPLICATION NOTE
Volume I
Preface
■ Purpose and Readers Intended
The F2MC-8L family is a line of proprietary 8-bit, single-chip microcontrollers that are
configurable as ASICs (application-specific integrated circuits) and capable of operating at low
voltage.
This manual is intended for engineers who develop products using the F2MC-8L family of
microcontrollers. It describes application programs based on the MB89160/160A series. You
should run through this manual if you write application programs for the F2MC-8L family.
*: F2MC stands for FUJITSU Flexible Microcontroller (a registered trademark of FUJITSU
LIMITED in Japan).
■ Organization
This manual consists of seven chapters and an appendix:
Chapter 1 Key Scan
This chapter describes a sample program for key scan.
Chapter 2 Key Scan Using A/D Conversion
This chapter describes a sample program for key scan using the A/D conversion.
Chapter 3 LCD Clock Display
This chapter describes a sample program for LCD clock display.
Chapter 4 Software UART
This chapter describes a sample program for implementing a UART by means of software.
Chapter 5 E2PROM Interface
This chapter describes a sample program for transferring data from/to the E2PROM.
Chapter 6 Remote-Control Signal Transmitting
This chapter describes a sample program for transmitting the remote-control signals.
Chapter 7 Remote-Control Signal Receiving
This chapter describes a sample program for receiving the remote-control signals.
Appendix Resource Definition List
This appendix provides a resource definition list.
1. The products described in this manual and the specifications thereof may be changed without prior notice. To
obtain up-to-date information and/or specifications, contact your Fujitsu sales representative or Fujitsu authorized
dealer.
2. Fujitsu will not be liable for infringement of copyright, industrial property right, or other rights of a third party caused
by the use of information or drawings described in this manual.
3. The contents of this manual may not be transferred or copied without the express permission of Fujitsu.
4. The products contained in this document are not intended for use with equipments which require extremely high
reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for
life support.
5. Some of the products described in this manual may be strategic materials (or special technology) as defined by the
Foreign Exchange and Foreign Trade Control Law. In such cases, the products or portions thereof must not be
exported without permission as defined under the Law.
 1997 FUJITSU LIMITED Printed in Japan
Note before Reading Ahead
•
The sample programs contained in this manual are intended for specific series of
microcontrollers in the F2MC-8L family. Before applying these programs to any other series
of microcontrollers in the F2MC-8L family, therefore, be sure to check the control register
address.
•
The sample programs contained in this manual are coded to be versatile. Before using these
programs, however, be sure to consider the register status prior to program execution as well
as the registers and bits irrelevant to the intended operation of the program on the system
level.
•
The sample programs contained in this manual are provided as valuable aids in developing
the application programs for the F2MC-8L family of microcontrollers. In practice, however,
some of these programs may need be modified depending on the target system. Before
using any of them, therefore, be sure to verify the actual operation of the program.
•
Fujitsu may assume no liability for errors in this manual and no responsibility for correcting
errors immediately even if they are found.
Using This Manual
■ How This Manual is Compiled
In principle, each section of this manual fits on one page or spread, allowing you to view the
entire section without turning the pages.
Since each section begins with its section outline below the section title, you can understand the
outline of this product by browsing through such section outlines.
Also, the higher level section title is shown above the section title, making it easy to know the
context in which the current section is provided.
■ How to Search for Information
In addition to the conventional search method using the table of contents or index, the following
methods are available to search each section of this manual for information as required:
❍ Searching for a section or subsection instead of direct search for an item of information
The "Subtitle" index search is convenient in this case. In principle, each section of this
manual has one or more subtitles. The "Subtitles" index is a listing of subtitles sorted in
alphabetical order by keyword included in the subtitles. If you remember any keyword
included in a subtitle, you can reach the intended subtitle by searching by that keyword.
❍ Searching for a figure or table
The "Figure and Table" index search is convenient in this case. In principle, figures and
tables in this manual have their titles. The "Figures and Tables" index is a listing of these
titles sorted in alphabetical order by keyword included in the titles. You can use the
"Figures and Tables" index for searching in the same way as when using the abovementioned "Subtitles" index.
■ Structure of Spread Layout
Higher level section title
Section title
Section outline





Subtitle
Table/Figure title
Subtitle
CONTENTS
Chapter 1 KEY SCAN .............................................................................................................1
1.1 Specifications of the Key Scan Sample Program .........................................................................................2
1.2 Skeletonized Flowchart for Key Scan ...........................................................................................................4
1.3 Resource Registers and RAM for Key Scan.................................................................................................6
1.4 Resource Register Initialization for Key Scan...............................................................................................8
1.5 RAM Initialization for Key Scan ..................................................................................................................12
1.6 Detailed Flowchart for Key Scan ................................................................................................................14
1.7 Sample Program for Key Scan ...................................................................................................................16
Chapter 2 KEY SCAN USING A/D CONVERSION ..............................................................21
2.1 Specifications of the A/D-Conversion Key Scan Sample Program.............................................................22
2.2 Skeletonized Flowchart for Key Scan Using A/D Conversion.....................................................................24
2.3 Resource Registers and RAM for Key Scan Using A/D Conversion ..........................................................25
2.4 Register Initialization for Key Scan Using A/D Conversion.........................................................................26
2.5 Detailed Flowchart for Key Scan Using A/D Conversion ............................................................................28
2.6 Sample Program for Key Scan Using A/D Conversion ...............................................................................30
Chapter 3 LCD CLOCK DISPLAY ........................................................................................33
3.1 Specifications of the LCD Clock Display Sample Program.........................................................................34
3.2 Segment Layout Drawing for LCD Clock Display .......................................................................................35
3.3 Skeletonized Flowchart for LCD Clock Display ..........................................................................................36
3.4 Resource Registers and RAM for LCD Clock Display ................................................................................37
3.5 Register Initialization for LCD Clock Display ..............................................................................................38
3.6 Detailed Flowchart for LCD Clock Display ..................................................................................................40
3.6.1 Detailed Flowchart for LCD Clock Display (The Watch Update) ...........................................................41
3.6.2 Detailed Flowchart for LCD Clock Display
(Editing Display, LCD Output, and LCD Segment Output) ....................................................................42
3.7 Sample Program for LCD Clock Display.....................................................................................................44
Chapter 4 SOFTWARE UART ..............................................................................................51
4.1 Specifications of the Software UART Sample Program..............................................................................52
4.2 Skeletonized Flowchart for Software UART ...............................................................................................54
4.3 Resource Registers and RAM for Software UART .....................................................................................56
4.4 Register and RAM Initialization for Software UART ...................................................................................58
4.5 Detailed Flowchart for Software UART.......................................................................................................61
4.5.1 Detailed Flowchart for Software UART
(UART Initialization and Transmitting Start Processing) .......................................................................62
4.5.2 Detailed Flowchart for Software UART (Receiving check, external interrupt,
and received data obtainment) ..............................................................................................................63
i
4.5.3 Detailed Flowchart for Software UART (Timer interrupt) ...................................................................... 64
4.6 Sample Program for Software UART......................................................................................................... 66
Chapter 5 E2PROM INTERFACE ......................................................................................... 75
5.1 Specifications of the E2PROM Interface Sample Program ........................................................................ 76
5.2 Skeletonized Flowchart for E2PROM Interface .......................................................................................... 78
5.3 Resource Registers and RAM for E2PROM Interface................................................................................ 79
5.4 Register Initialization for E2PROM Interface .............................................................................................. 80
5.5 RAM Initialization for E2PROM Interface ................................................................................................... 82
5.6 Detailed Flowchart for E2PROM Interface ................................................................................................. 84
5.6.1 Detailed Flowchart for E2PROM Interface (Write Permission/Inhibition OP code Output) ................... 85
5.6.2 Detailed Flowchart for E2PROM Interface (Status Register Read and Block Write Protection) ........... 86
5.6.3 Detailed Flowchart for E2PROM Interface (Data Read)........................................................................ 87
5.6.4 Detailed Flowchart for E2PROM Interface (Data Write)........................................................................ 88
5.7 Sample Program for E2PROM Interface .................................................................................................... 90
Chapter 6 REMOTE-CONTROL SIGNAL TRANSMITTING ................................................ 97
6.1 Specifications of the Remote-Control Signal Transmitting Sample Program............................................. 98
6.2 Skeletonized Flowchart for Remote-Control Signal Transmitting ............................................................ 100
6.3 Resource Registers and RAM for Remote-Control Signal Transmitting .................................................. 102
6.4 Register Initialization for Remote-Control Signal Transmitting ................................................................ 104
6.5 RAM Initialization for Remote-Control Signal Transmitting...................................................................... 106
6.6 Detailed Flowchart for Remote-Control Signal Transmitting.................................................................... 108
6.6.1 Detailed Flowchart for Remote-Control Signal Transmitting (Transmitting data setting
and interrupt activation) ...................................................................................................................... 109
6.6.2 Detailed Flowchart for Remote-Control Signal Transmitting (16-bit timer interrupt) ........................... 110
6.7 Sample Program for Remote-Control Signal Transmitting....................................................................... 112
Chapter 7 REMOTE-CONTROL SIGNAL RECEIVING ..................................................... 123
7.1 Specifications of the Remote-Control Signal Receiving Sample Program............................................... 124
7.2 Skeletonized Flowchart for Remote-Control Signal Receiving ................................................................ 126
7.3 Resource Registers and RAM for Remote-Control Signal Receiving ...................................................... 128
7.4 Register Initialization for Remote-Control Signal Receiving .................................................................... 130
7.5 RAM Initialization for Remote-Control Signal Receiving.......................................................................... 132
7.6 Detailed Flowchart for Remote-Control Signal Receiving ........................................................................ 133
7.6.1 Detailed Flowchart for Remote-Control Signal Receiving (External Interrupt).................................... 134
7.6.2 Detailed Flowchart for Remote-Control Signal Receiving (Time-Base Timer Interrupt) ..................... 135
7.7 Sample Program for Remote-Control Signal Receiving........................................................................... 136
APPENDIX RESOURCE DEFINITION LIST........................................................................ 141
INDEX................................................................................................................................... 147
Keyword Index ................................................................................................................................................ 148
ii
Subtitle Index ...................................................................................................................................................150
Figure and Table Index ....................................................................................................................................152
iii
FIGURES
Figure 1.1a Example of hardware configuration for key scan ............................................................................ 3
Figure 1.1b Timing chart when the "SW6" key is pushed .................................................................................. 3
Figure 1.2
Skeletonized flowchart for key scan................................................................................................ 4
Figure 1.6a Detailed flowchart for key scan ..................................................................................................... 14
Figure 1.6b Detailed flowchart for key scan (interrupt and wake-up)............................................................... 15
Figure 2.1
Circuit diagram for key scan using the A/D conversion ................................................................ 23
Figure 2.2
Skeletonized flowchart for key scan using the A/D conversion..................................................... 24
Figure 2.5a Detailed flowchart for key scan using the A/D conversion ............................................................ 28
Figure 2.5b Detailed flowchart for key scan using the A/D conversion (start and interrupt) ............................ 29
Figure 3.2
Segment layout drawing for LCD clock display............................................................................. 35
Figure 3.3
Skeletonized flowchart for LCD clock display ............................................................................... 36
Figure 3.6
Detailed flowchart for LCD clock display....................................................................................... 40
Figure 3.6.1 Detailed flowchart for LCD clock display (the watch update)........................................................ 41
Figure 3.6.2 Detailed flowchart for LCD clock display (Editing the display, LCD output,
and LCD segment output .............................................................................................................. 42
Figure 4.1a Circuit diagram for the software UART sample program .............................................................. 52
Figure 4.1b Format of data received by the software UART sample program................................................. 53
Figure 4.1c The transmitting data format of the software UART sample program........................................... 53
Figure 4.2a Skeletonized flowchart for software UART ................................................................................... 54
Figure 4.2b Skeletonized flowchart for software UART (External and timer interrupts)................................... 55
Figure 4.5
Detailed flowchart for software UART........................................................................................... 61
Figure 4.5.1 Detailed flowchart for software UART (UART initialization and transmitting start processing) ..... 62
Figure 4.5.2 Detailed flowchart for software UART (Receiving check, external interrupt,
and received data obtainment) ..................................................................................................... 63
Figure 4.5.3 Detailed flowchart for software UART (timer interrupt) ................................................................. 64
Figure 5.1
Circuit diagram for E2PROM interface .......................................................................................... 77
Figure 5.2
Skeletonized flowchart for E2PROM interface.............................................................................. 78
Figure 5.6
Detailed flowchart for E2PROM interface...................................................................................... 84
Figure 5.6.1 Detailed flowchart for E2PROM interface (Write permission/inhibition OP code output) .............. 85
Figure 5.6.2 Detailed flowchart for the E2PROM interface (status register read and block write protection).... 86
Figure 5.6.3 Detailed flowchart for E2PROM interface (data read) ................................................................... 87
Figure 5.6.4 Detailed flowchart for E2PROM interface (data write)................................................................... 88
Figure 6.1a Circuit diagram for the remote-control signal transmitting sample program ................................. 98
Figure 6.1b Data format of the remote-control signal transmitting sample program ........................................ 99
Figure 6.2
Skeletonized flowchart for remote-control signal transmitting..................................................... 100
Figure 6.6
Detailed flowchart for remote-control signal transmitting ............................................................ 108
iv
Figure 6.6.1 Detailed flowchart for remote-control signal transmitting (transmitting data setting
and interrupt start) .......................................................................................................................109
Figure 6.6.2 Detailed flowchart for remote-control signal transmitting (16-bit timer interrupt) .........................110
Figure 7.1a Circuit diagram for the remote-control signal receiving sample program ....................................124
Figure 7.1b Data format of the remote-control signal receiving sample program ...........................................125
Figure 7.2
Skeletonized flowchart for remote-control signal receiving..........................................................126
Figure 7.6
Detailed flowchart for remote-control signal receiving .................................................................133
Figure 7.6.1 Detailed flowchart for remote-control signal receiving (external interrupt)...................................134
Figure 7.6.3 Detailed flowchart for remote-control signal receiving (time-base timer interrupt).......................135
v
TABLES
Table 1.3a Resource registers used for key scan ...................................................................................... 6
Table 1.3b RAM allocations for key scan ................................................................................................... 7
Table 2.1 A/D values corresponding to respective keys......................................................................... 23
Table 2.3a Resource registers ................................................................................................................. 25
Table 2.3b RAM allocations...................................................................................................................... 25
Table 3.4a Resource registers used for LCD clock display ...................................................................... 37
Table 3.4b RAM allocations for LCD clock display ................................................................................... 37
Table 4.3a Resource registers for software UART ................................................................................... 56
Table 4.3b RAM allocations for software UART ....................................................................................... 57
Table 4.3c Contents of flags for software UART ...................................................................................... 57
Table 5.3a Resource registers used for E2PROM interface ..................................................................... 79
Table 5.3b RAM allocations for E2PROM interface .................................................................................. 79
Table 6.3a Resource registers for remote-control signal transmitting .................................................... 102
Table 6.3b RAM allocations for remote-control signal transmitting ......................................................... 103
Table 6.3c Contents of flags at remote-control signal transmitting address 80H .................................... 103
Table 7.3a Resource registers for remote-control signal receiving ........................................................ 128
Table 7.3b RAM allocations for remote-control signal receiving ............................................................ 128
Table 7.3c Flag contents in the register for remote-control signal receiving (80H).................................. 129
vi
CHAPTER 1
KEY SCAN
This chapter describes a sample program for key scan.
The F2MC-8L series provides the three operation modes (main mode, sub-mode and
watch mode) and a sleep status. Return from each mode is achieved by each type of
interrupt request and external interrupt.
For example, if a program is not executed until a signal is entered, the signal is
assumed to be assigned to the external interrupt port. In this case, the system waits in
a low power consumption mode with no processing required. The system is to operate
ordinarily with wake-up by an external interrupt. Compared with ordinary operation,
power consumption can be largely reduced since the system waits again in a low
power consumption mode after the completion of processing.
1.1 Specifications of the Key Scan Sample Program
1.2 Skeletonized Flowchart for Key Scan
1.3 Resource Registers and RAM for Key Scan
1.4 Resource Register Initialization for Key Scan
1.5 RAM Initialization for Key Scan
1.6 Detailed Flowchart for Key Scan
1.7 Sample Program for Key Scan
1
CHAPTER 1 KEY SCAN
1.1
Specifications of the Key Scan Sample Program
Key-scan output and key-data input are performed by 8-bit PWM timer 1 interrupt.
Chattering of an entered key is serviced by the 8-bit PWM timer 1 interrupt routine.
Upon completion of chattering service, the interrupt routine notifies the main routine
that the key entry has been stabilized.
■ Conditions for the key scan sample program
The specifications of the key scan sample program for the F2MC-8L family assume the following
conditions:
❍ Applicable series: MB89160/160A
•
Main clock ............ 4.19 MHz
•
Subclock............... 32.768 KHz
❍ Ports in use (see the circuit drawing)
•
Input ........... P00/INT20 ,P01/INT21, P02/INT22
•
Output......... P20, P21, P22, P23 (Key scan select port)
■ Operation outlines of the key scan sample program
❍ Ordinary operation (key scan mode)
In the key scan mode, "LOW" is selected sequentially for key scan select ports every
972.8 µs and three key states for each of the ports are then entered.
A change in entered-key state removes 38.91-ms chattering and stores the determinedkey state in RAM.
❍ Low power consumption mode (stop mode)
When all keys are set to off, the system waits in the low power consumption mode (stop
mode) for the next key entry (interrupt).
Wake-up by the next key entry (interrupt) releases the low power consumption mode and
then performs the ordinary operation (in the key-scan mode) for processing.
2
CHAPTER 1 KEY SCAN
■ Circuit diagram for the key scan sample program
❍ Example of hardware configuration
Figure 1.1a shows an example of the hardware configuration for key scan.
VCC
MB89160/160A
P00/INT20
VCC
P01/INT21
P02/INT22
VSS
SW9
SW10
SW11
SW12
SW5
SW6
SW7
SW8
SW1
SW2
SW3
SW4
P23
P22
RST
X0A X1A X0
32.768 kHz
P21
P20
X1
4.194 MHz
Figure 1.1a Example of hardware configuration for key scan
❍ Example of timing chart
Figure 1.1b shows an example of the timing chart in the case that the "SW6" key is
pushed.
P23
P22
P21
P20
P00/INT20
P01/INT21
P02/INT22
Figure 1.1b Timing chart when the "SW6" key is pushed
3
CHAPTER 1 KEY SCAN
1.2
Skeletonized Flowchart for Key Scan
Figure 1.2 is a skeletonized flowchart for key scan.
■ Skeletonized flowchart for key scan
Main routine
Key-entry routine
No
Output the scan data
Is key-entry fixed?
Enter the key data
Yes
Process after key-entry fixed
No
Are all key-entries
completed?
Yes
Are all processes
completed?
Is the key-entry fixed?
Yes
Process after key-entry fixed
Yes
Save the key fixed data
Set the key-entry fixed flag
Wake-up
End of processing
Initialize the key-entry area
Release the stop mode
End of processing
Figure 1.2 Skeletonized flowchart for key scan
4
No
No
Memo
5
CHAPTER 1 KEY SCAN
1.3
Resource Registers and RAM for Key Scan
Key scan uses the following three resources to set registers and allocate RAM.
• External interrupt 2 (Wake-up 2) INT20, INT21, INT22
• 8-bit PWM timer 1 (Key scan and key entry)
• Standby control (Stop mode)
■ List of resource registers used for key scan
Table 1.3a lists the resource registers used for key scan.
Table 1.3a Resource registers used for key scan
Address
6
Register
Register contents
00H
PDR0
Port 0 data register
01H
DDR0
Port 0 input/output direction register
04H
PDR2
Port 2 data register
05H
DDR2
Port 2 input/output direction register
07H
SYCC
System clock control register
08H
STBC
Standby control register
1EH
CNTR1
PWM1 control register
1FH
COMP1
PWM1 compare register
32H
EIE2
External interrupt 2 control register
33H
EIF2
External interrupt 2 flag
7DH
ILR2
Interrupt level set register 2
7EH
ILR3
Interrupt level set register 3
CHAPTER 1 KEY SCAN
■ RAM allocations for key scan
Table 1.3b lists RAM allocations for key scan.
Table 1.3b RAM allocations for key scan
Address
Symbol
Function
80H
81H
82H
83H
KEYNEWBF
+1
+2
+3
Current key-entry data storage area
84H
85H
86H
87H
KEYOLDBF
+1
+2
+3
Preceding key-entry data storage area
88H
89H
8AH
8BH
KEYNOWBF
+1
+2
+3
Key-entry fixed data storage area
8CH
KEYCHT
Key-entry chattering counter
8DH
SELCNT
Counter for key scan
8EH
SELOUTBF
Key-selection data output buffer
8FH
STATS
Each type of flag area
7
CHAPTER 1 KEY SCAN
1.4
Resource Register Initialization for Key Scan
This section describes the following seven types of the resource registers initialization
for key scan:
• Initialization for the input/output ports (PDR0, DDR0, PDR2, and DDR2)
• Initialization for the system clock control register (SYCC)
• Initialization for the standby control register (STBC)
• Initialization for the 8-bit PWM1 timer control register (CNTR1)
• Initialization for the 8-bit PWM1 timer compare register (COMR1)
• Initialization for the external interrupt 2 control registers (EIE2 and EIF2)
• Initialization for the interrupt level set registers (ILR2 and ILR3)
■ Resource register initialization for key scan
❍ Initializing the input/output ports (PDR0, DDR0, PDR2, DDR2)
PDR0
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
P00 to P07: 'H' output
DDR0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
*
PDR2
*
*
*
*
P00 to P02: Sets to input port
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
P20 to P27: 'H' output
DDR2
7 6 5 4 3 2 1 0
0 0 0 0 1 1 1 1
*
*
*
*
P20 to P22: Sets to input port
* The port is set to input because of an unused port.
❍ Initializing the system clock control register (SYCC)
DDR2
7 6 5 4 3 2 1 0
0 0 0 1 0 1 1 1
*
*
*
CS1, CS0: System operation clock 4/fch=0.95Js
SCS: Sets the system clock to the main clock.
WT1, WT0: Oscillation stabilization time 216/fch=15.6ms
* Unused bits are set to 0.
8
CHAPTER 1 KEY SCAN
❍ Initializing the standby control register (STBC)
STBC
7 6 5 4 3 2 1 0
0 0 0 1 0 0 0 0
* *
* * * *
RST: Clears the software reset bit
SPL: Holds the port status in the stop mode
* Unused bits are set to 0.
❍ Initializing the 8-bit PWM1 timer control register (CNTR1)
7 6 5 4 3 2 1 0
CNTR1 0 0 1 0 1 0 0 1
*
TIE: Enables the timer 1 interrupt
OE: Sets P27/P31 to general port
TIR: Clears the timer 1 interrupt request flag
TPE: Starts the timer 1 count operation
P1, P0: Count clock 60.8 µs
P/TX: Timer operation mode
* Unused bits are set to 0.
❍ Initializing the 8-bit PWM1 timer compare register (COMR1)
7 6 5 4 3 2 1 0
COMR1 0 0 0 0 1 1 1 1
Sets the count value of the timer 1 interrupt cycle
Clock gear selection
Clock selection
64/fch
1(P1, P0 =0, 0)
Interrupt cycle =
16/fch
×
16 (P1, P0=0, 1)
8/fch
64 (P1, P0=1, 0)
4/fch
8 bits (P1, P0=1, 1)
COMR1
× (Compare register set value +1)
Example: [fch = 4.2 MHz (main clock)]
972.8 µs = 0.95 µs(4/fch)
×
64
× 16 (COMR1=0FH)
9
CHAPTER 1 KEY SCAN
❍ Initializing the external interrupt 2 control register (EIE2, EIF2)
EIE2
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
*
EIF2
*
*
*
*
IE20 to IE22: Disables the interrupt INT0 to INT2
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
*
*
*
*
*
*
*
IF20: Clears the low level detection flag
* Unused bits are set to 0.
❍ Initializing the interrupt level set registers (ILR2, ILR3)
ILR2
7 6 5 4 3 2 1 0
1 1 1 1 1 1 0 0
*
ILR3
*
*
*
*
*
L41, L40: Sets the external interrupt 2 level to "1"
7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1
*
*
*
*
*
*
* Unused bits are set to 0.
10
L91, L90: Sets the PWM timer 1 interrupt level to "1"
Memo
11
CHAPTER 1 KEY SCAN
1.5
RAM Initialization for Key Scan
This section describes the following six types of RAM initialization for key scan:
• Initialization for the current key-entry data storage area (KEYNEWBF)
• Initialization for the preceding key-entry data storage area (KEYOLDBF)
• Initialization for the key-entry fixed data storage area (KEYNOWBF)
• Initialization for the key-entry chattering counter (KEYCHT)
• Initialization for the key-scan counter (SELCNT)
• Initialization for the key-selection data output buffer (SELOUTBF)
■ RAM initialization for key scan
❍ Initializing the current key-entry data storage area (KEYNEWBF)
KEYNEWBF
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
*
*
*
*
*
7 6 5 4 3 2 1 0
KEYNEWBF+1 1 1 1 1 1 1 1 1
* * * * *
SW9, SW5, SW1: Sets the key-off data
SW10, SW6, SW2: Sets the key-off data
* Unused bits are set to 1.
7 6 5 4 3 2 1 0
KEYNEWBF+2 1 1 1 1 1 1 1 1
*
*
*
*
*
7 6 5 4 3 2 1 0
KEYNEWBF+3 1 1 1 1 1 1 1 1
* * * * *
SW11, SW7, SW3: Sets the key-off data
SW12, SW8, SW4: Sets the key-off data
* Unused bits are set to 1.
❍ Initializing the preceding key-entry data storage area
KEYOLDBF
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
*
KEYOLDBF+1
*
*
*
SW9, SW5, SW1: Sets the key-off data
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
*
12
*
*
*
*
*
SW10, SW6, SW2: Sets the key-off data
CHAPTER 1 KEY SCAN
KEYOLDBF+3
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
*
KEYOLDBF+4
*
*
*
*
SW11, SW7, SW3: Sets the key-off data
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
*
*
*
*
*
SW12, SW8, SW4: Sets the key-off data
* Unused bits are set to 1.
❍ Initializing the key-entry storage area
KEYNOWBF
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
*
*
*
*
*
SW9, SW5, SW1: Sets the key-off data
7 6 5 4 3 2 1 0
KEYNOWBF+1 1 1 1 1 1 1 1 1
* * * * *
SW10, SW6, SW2: Sets the key-off data
7 6 5 4 3 2 1 0
KEYNOWBF+2 1 1 1 1 1 1 1 1
*
*
*
*
*
SW11, SW7, SW3: Sets the key-off data
7 6 5 4 3 2 1 0
KEYNOWBF+3 1 1 1 1 1 1 1 1
* * * * *
SW12, SW8, SW4: Sets the key-off data
* Unused bits are set to 1.
❍ Initializing the key-entry chattering counter
KEYCHT
Sets the chattering count value (0AH) when the
key-entry status changes
❍ Initializing the counter for key scan
SELCNT
Sets the count value (00H) for key-scan/
-selection output data
❍ Initializing the key-selection data output buffer
SELCNT
Sets the initial value (FEH) for key-selection
output data
13
CHAPTER 1 KEY SCAN
1.6
Detailed Flowchart for Key Scan
Figure 1.6a shows the detailed flowchart for key scan; Figure 1.6b shows the detailed
flowchart for key-scan interrupt and wake-up.
■ Detailed flowchart for Key Scan
A
RESET
MAIN
Set the system control register
Is the key-entry fixed?
Set the stack pointer
Yes
Set the input/output port
Processing after key fixed
Initialize the RAM area
Set the interrupt cycle for key scan
Set the key scan interrupt level
No
Are all processes
completed?
Yes
Enter the stop mode
Set the interrupt level for wake-up
Enable the key scan interrupt
A
Figure 1.6a Detailed flowchart for key scan
14
No
CHAPTER 1 KEY SCAN
Key-scan interrupt
Wake-up
KEYINT
WAKE_UP
Save the A, T and IX registers
Save the A/T register
Output data for key scan
Clear the interrupt request
Enter the key data
Disable the wake-up interrupt
Is the entry of all key
status completed?
Return the A/T register
No
Yes
No
RETI
Is the key-entry fixed?
Yes
Store the key fixed data
Set the key-entry fixed flag
Return the A, T and IX registers
RETI
Figure 1.6b Detailed flowchart for key scan (interrupt and wake-up)
15
CHAPTER 1 KEY SCAN
1.7
Sample Program for Key Scan
This section provides a sample program for key scan.
■ Sample program for key scan
NAME
KEYSCAN
;***************************************************************
;*
*
;*
Key scan sample program
*
;*
*
;***************************************************************
&INCLUDE
R160.INC
;********************************
;*
RAM definition
*
;********************************
RAM
DIRSEG ABS
ORG
0080H
KEYNEWBF
RB
4
; Current key-entry data storage area
KEYOLDBF
RB
4
; Preceding key-entry data storage area
KEYNOWBF
RB
4
; Key-entry fixed data storage area
KEYCHT
RB
1
; Key-chattering counter
SELCNT
RB
1
; Key-scan counter
SELOUTBF
RB
1
; Key-scan selection data output buffer
;
STATS
RB
0
; Each type of flag area
KEYCNG
RBIT 1
; Key-entry status change flag
KEYINFG
RBIT 1
; Key-entry completion flag
STOPINREQ
RBIT 1
; Request flag to the stop mode
RAM
ENDS
PROG
CSEG
EXTRN KEYREAD
;********************************
;*
Initialization
*
;********************************
RESET:
MOV
SYCC,#00010111B
; Set the highest speed mode
MOVW
SP,#0180H
; Set the stack pointer
MOV
STBC,#00010000B
; Set the standby control register
;
MOV
DDRO,#00000000B
; Set ports (P00 to P07) to input ports
MOV
PDRO,#11111111B
; Output the initial data to ports (P00 to P07)
;
MOV
DDR2,#11111111B
; Set ports (P20 to P27) to output ports
MOV
PDR2,#11111111B
; Output the initial data to ports (P20 to P27)
;
MOVW
A,#OFFFFH
; Set the key initialization data
MOVW
KEYNEWBF,A
MOVW
KEYNEWBF+2,A
MOVW
KEYOLDBF,A
MOVW
KEYOLDBF+2,A
MOVW
KEYNOWBF,A
MOVW
KEYNOWBF+2,A
;
MOV
KEYCHT,#0AH
; Set the key-entry chattering counter
;
MOV
SELCNT,#00H
; Set the counter for key scan
;
MOV
SELOUTBF,#11111110B
; Set the key-scan selection data
;
MOV
CNTR1,#00100001B
; Set the PWM1 timer control register
MOV
COMR1,#0FH
; 16*60.8 µsec = 972.8 µsec
;
MOV
EIE2,#OOOOOOOOB
; Initialize the external interrupt 2 control
register
MOV
EIF2,#OOOOOOOOB
; Clear the low detection flag for external
interrupt 2
;
MOV
ILR2,#11111100B
; Set the interrupt level
MOV
ILR3,#11110011B
;
MOVW
A,#0070H
; Enable interrupt
MOVW
PS,A
; Enable the interrupt level 1
;
SETB
TPE
; Start the PWM timer 1
16
CHAPTER 1 KEY SCAN
;********************************
;*
Main routine
*
;********************************
MAIN:
BBC
KEYINFG,MAIN_020
;
CALL
KEYREAD
;
MAIN_020:
BBC
STOPINREQ,MAIN
;
CLRB
STOPINREQ
CLRB
TPE
CLRB
TIR
CLRB
IF20
MOV
EIE2,#00000111B
;
MOV
SELCNT,#00H
MOV
SELOUTBF,#11111110B
MOV
PDR2,#11110000B
;
SETB
STP
NOP
NOP
NOP
;
JMP
MAIN
;***********************************
;*Processing for key scan interrupt*
;***********************************
KEYINT:
;
PUSHW
A
XCHW
A,T
PUSHW
A
PUSHW
IX
;
CLRB
TIR
MOVW
A,#0000H
MOV
A,SELCNT
MGVW
A,#KEYNEWBF
CLRC
ADDCW
A
; Key-entry fixed?
No
; Processing after key fixed
; Is there a request to enter the stop mode?
;
;
;
;
;
No
Clear the request to enter the stop mode
Disable the key-scan interrupt
Clear the key-scan interrupt flag
Clear the wake-up interrupt flag
Enable the wake-up interrupt
; Enter the stop mode
; Save register
; Clear the interrupt flag
; Calculate the destination address for storing
the key-entry data
MOVW
IX,A
MOV
AND
MOV
OR
MOV
A,#11110000B
A,PDR2
A,SELOUTBF
A
PDR2,A
; Output the selection data for key scan
MOV
OR
MOV
A,PDRO
A,#11111000B
@IX,A
; Enter the key data
; Mask the higher 5 bits
; Set the key-entry data at the storage address
MOV
SETC
ROLC
OR
MOV
A,SELOUTBF
; Creates the next data for scanning
A
A,#11110000B
SELOUTBF,A
; Mask the higher 4 bits
MOV
INCW
MOV
CMP
BNZ
A,SELCNT
A
SELCNT,A
A,#04H
KEYINT_EXT
; Is all scan completed?
; No
MOV
MOV
SELCNT,#00H
SELOUTBF,#11111110B
; Initialize the key-scan counter
; Initialize the selection data for key scan
MOVW
A,KEYNEWBF
; Is there a change of the current key data from
the preceding one?
MOVW
CMPW
BNZ
A,KEYOLDBF
A
KEYINT_20
MOVW
A,KEYNEWBF+2
;
;
;
;
; Update the key-scan counter
;
;
; Yes
;
; Is there a change of the current key data from
the preceding one?
17
CHAPTER 1 KEY SCAN
MOVW
CMPW
BNZ
A,KEYOLDBF+2
A
KEYINT_020
; Yes
BBC
KEYCNG,KEYINT_EXT
; Is there a change of the key-entry status?
MOV
CLRC
SUBC
MOV
BNZ
A,KEYCHT
; Chattering count processing
A,#01H
KEYCHT,A
KEYINT_EXT
; Is the chattering completed?
CLRB
KEYCNG
; Clear the key-entry status change flag
MOVW
MOVW
CMPW
BNZ
A,KEYNEWBF
A,KEYNOWBF
A
KEYINT_010
; Same as the preceding key fixed data?
MOVW
MOVW
CMPW
BZ
A,KEYNEWBF+2
A,KEYNOWBF+2
A
KEYINT_EXT
; Same as the preceding key fixed data?
;
;
No
;
;
; No
;
;
KEYINT_010:
MOVW
A,KEYNEWBF
MOVW
KEYNOWBF,A
MOVW
A,KEYNEWBF+2
MOVW
KEYNOWBF+2,A
;
SETB
KEYINFG
;
KEYINT_EXT:
POPW
IX
POPW
A
XCHW
A,T
POPW
A
;
RETI
;
KEYINT_020:
MOVW
A,KEYNEWBF
MOVW
KEYOLDBF,A
MOVW
A,KEYNEWBF+2
MOVW
KEYOLDBF+2,A
;
MOV
KEYCHT,#0AH
;
SETB
KEYCNG
;
JMP
KEYINT_EXT
;
;********************************
;*
Wake-up processing
*
;********************************
WAIKE_UP:
PUSHW
A
XCHW
A,T
PUSHW
A
;
CLRB
IF20
MOV
EIE2,#00000000B
;
MOV
PDR2,#11111111B
;
CLRB
TIR
SETB
TPE
;
POPW
A
XCHW
A,T
POPW
A
;
RETI
PROG
ENDS
18
; Yes
; Change in the key-entry data
; Set the latest fixed data
; Set the key-entry fixation flag
; Return register
; Update the key-entry data
; Set the key chattering counter
; Set the key-entry status change flag
; Save register
; Clear the wake-up interrupt flag
; Disable the wake-up interrupt
; Initialize ports (P00 to P02)
; Clear the key-scan interrupt flag
; Enable the key-scan interrupt
; Return register
No
CHAPTER 1 KEY SCAN
;********************************
;*
Vector address
*
;********************************
VECTOR CSEG
ABS
ORG
0FFE8H
DW
KEYINT
ORG
0FFF2H
DW
WAIKE_UP
ORG
0FFFCH
DB
00H
DB
00H
DW
RESET
;
VECTOR ENDS
END
; PWM timer 1 (process for key-entry interrupt)
; Reset mode
; Reset vector
19
Memo
20
CHAPTER 2
KEY SCAN USING A/D CONVERSION
This chapter describes a sample program for key scan using A/D conversion.
Some of the F2MC-8L series is equipped with an A/D converter. Use of this A/D
converter for key entry gives a merit, i.e., the number of ports can be less than that
required for key entry in the ordinary dynamic scan.
2.1 Specifications of the A/D-Conversion Key Scan Sample Program
2.2 Skeletonized Flowchart for Key Scan Using A/D Conversion
2.3 Resource Registers and RAM for Key Scan Using A/D Conversion
2.4 Register Initialization for Key Scan Using A/D Conversion
2.5 Detailed Flowchart for Key Scan Using A/D Conversion
2.6 Sample Program for Key Scan Using A/D Conversion
21
CHAPTER 2 KEY SCAN USING A/D CONVERSION
2.1
Specifications of the A/D-Conversion Key Scan Sample Program
A/D conversion is used by enabling the A/D conversion interrupt in the A/D mode.
A/D-conversion data is read by the A/D conversion interrupt routine.
■ Specifications of the Key Scan Sample Program using the A/D conversion
The specifications of the A/D-conversion key scan sample program for the F2MC-8L family
assume the following conditions:
❍ Applicable series: MB89160/160A
•
Main clock ............ 4.194 MHz
•
Subclock............... 32.768 KHz
❍ Ports in use
•
Input ........... P57/AN7 (Used as A/D input port "AN7")
•
Output......... P56/AN6 (Used as key-entry permission port "P56")
[Active 'L']
■ Operation outlines of the key scan sample program using the A/D conversion
❍ Starting A/D conversion
Prior to the start of A/D conversion, "L" level is output to the P56 port.
This allows the voltage levels corresponding to respective keys to be entered
❍ Terminating A/D conversion
After the termination of A/D conversion, 'H' level is output to the P56 port.
This saves the excessive consumption of current.
22
CHAPTER 2 KEY SCAN USING A/D CONVERSION
■ Circuit diagram for the key scan sample program using the A/D conversion
Figure 2.1 shows a circuit diagram for key scan using the A/D conversion; Table 2.1 list the A/D
values corresponding to respective keys.
VCC
MB89160/160A
VCC
+15V
AN7
SW13
VSS
SW14
SW15
SW16
SW17
SW18
R11
1.5 kΩ
R12
1.1 kΩ
R13
1.3 kΩ
R14
2 kΩ
R11
3 kΩ
R11
5.1 kΩ
R11
11 kΩ
R28
6.2 kΩ
P56
RST
+5V
AVCC
AVR
AVSS
X0A X1A X0
X1
32.768 kHz
4.194 MHz
Figure 2.1 Circuit diagram for key scan using the A/D conversion
Table 2.1 A/D values corresponding to respective keys
Key
A/D value (HEX)
All off
36
SW13
D1
SW14
B5
SW15
9E
SW16
85
SW17
6C
SW18
51
23
CHAPTER 2 KEY SCAN USING A/D CONVERSION
2.2
Skeletonized Flowchart for Key Scan Using A/D Conversion
Figure 2.2 shows a skeletonized flowchart for key scan using the A/D conversion.
■ Skeletonized flowchart for key scan using the A/D conversion
Main routine
Start of A/D conversion
Start of A/D conversion
Is the A/D conversion
requested?
No
No
Is A/D entered?
Yes
Clear the A/D conversion request
Yes
Clear the A/D entry flag
Set the A/D conversion
Perform processing after
key-entry fixed
Start the A/D conversion
End of processing
Set the A/D conversion request
A/D Interrupt
Read the A/D value
Read the A/D conversion data
Set the A/D entry flag
End of processing
Figure 2.2 Skeletonized flowchart for key scan using the A/D conversion
24
CHAPTER 2 KEY SCAN USING A/D CONVERSION
2.3
Resource Registers and RAM for Key Scan Using A/D
Conversion
Key scan using the A/D conversion uses the following resource to set registers and
allocate RAM.
• 8-bit A/D converter (channel 7: AN7)
■ Resource registers for key scan using the A/D conversion
Table 2.3a lists the resource registers for key scan using A/D conversion.
Table 2.3a Resource registers
Address
Register
Register contents
0FH
PDR5
Port 5 data register
2DH
ADC1
A/D converter control register 1
2EH
ADC2
A/D converter control register 2
2FH
ADCD
A/D data register
7EH
ILR3
Interrupt level set register 3
■ RAM allocations for key scan using the A/D conversion
Table 2.3b lists RAM allocations for key scan using the A/D conversion.
Table 2.3b RAM allocations
Address
Symbol
Function
90H
AD_KEY
A/D entry data area
91H
ADKEY_FLAG
A/D entry flag area
25
CHAPTER 2 KEY SCAN USING A/D CONVERSION
2.4
Register Initialization for Key Scan Using A/D Conversion
Initializations for the registers for key scan using the A/D conversion are divided into
the following four types:
• Initialization for the input/output port (PDR5)
• Initialization for the A/D converter control register 1 (ADC1)
• Initialization for the A/D converter control register 2 (ADC2)
• Initialization for the interrupt level set register (ILR3)
The Initializing RAM for key scan using the A/D conversion are divided into the
following two types:
• Initialization for the A/D input data area (AD_KEY)
• Initialization for the A/D input flag area (ADKEY_FLAG)
■ Register initialization for key scan using the A/D conversion
❍ Initializing the input/output port (PDR5)
PDR5
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
*
*
*
*
*
*
P56/AN6: Key scan inhibition output
P57/AN6: Sets to "1" for using as analog.
* The port is set to 'H' output because of an unused port.
❍ Initializing the A/D converter control register 1 (ADC1)
ADC1
7 6 5 4 3 2 1 0
0 1 1 1 0 0 0 0
*
* Unused bits are set to 0.
26
AD: Stops the A/D conversion
ADMV: Sets the converting flag to '0'
ADI: Clears the interrupt flag
ANS3 to 0: Selects AN7
CHAPTER 2 KEY SCAN USING A/D CONVERSION
❍ Initializing the A/D converter control register 2 (ADC2)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1
ADC2
*
*
*
*
TEST: Sets the test bit to '1'
EXT: Inhibits the continuous conversion
ADMD: Sets to the A/D mode
ADIE: Inhibits the A/D interrupt
* Unused bits are set to 0.
❍ Initializing the interrupt level set register
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
ILR3
*
*
*
*
*
*
LB1, LB0: Sets the A/D interrupt level to 1
* Unused bits are set to 1.
■ RAM initialization for key scan using the A/D conversion
❍ Initializing the A/D entry data area (AD_KEY)
AD_KEY
Clear with '00H'
❍ Initializing the flag area for A/D entry (AD_KEY_FLAG)
7 6 5 4 3 2 1 0
AD_KEY_FLAG 1 1 1 1 1 1 1 1
*
*
*
*
*
*
* Unused bits are set to 0.
F_ADIN: A/D entry flag
F_ADREQ: A/D conversion request flag
27
CHAPTER 2 KEY SCAN USING A/D CONVERSION
2.5
Detailed Flowchart for Key Scan Using A/D Conversion
Figure 2.5a shows a detailed flowchart for key scan using the A/D conversion; Figure
2.5b shows a detailed flowchart for A/D conversion start and interrupt.
■ Detailed flowchart for key scan using the A/D conversion
MAIN
A
RESET
Set the system control register
Start the A/D converter
Set the stack pointer
Initialize P50 to P57
Set the A/D converter control register
Initialize the RAM area
Set the A/D interrupt level
Enable the interrupt
No
Is A/D entered?
Yes
Clear the A/D entry flag
Processing for A/D key
fixed
Set the A/D conversion request
Set the A/D conversion request
A
Figure 2.5a Detailed flowchart for key scan using the A/D conversion
28
CHAPTER 2 KEY SCAN USING A/D CONVERSION
Start of A/D conversion
A/D interrupt
AD_EN
Is the A/D conversion
requested?
AD_READ_INT
No
Yes
Clear the A/D conversion request
Save the A/T register
Clear the A/D interrupt
request flag
PDR5 : 6 ← “1”
Set the A/D converter
PDR5 : 7 ← “1”
Read and store the A/D
conversion data
PDR5 : 6 ← “0”
Set the A/D entry flag
Start the A/D converter
Return the A/T register
RET1
RET1
Figure 2.5b Detailed flowchart for key scan using the A/D conversion (start and interrupt)
29
CHAPTER 2 KEY SCAN USING A/D CONVERSION
2.6
Sample Program for Key Scan Using A/D Conversion
This section provides a sample program for key scan using the A/D conversion.
■ Sample program for key scan using the A/D conversion
NAME
AD_KEY
;***************************************************************
;*
*
;*
A/D key entry sample program
*
;*
*
;***************************************************************
&INCLUDE
R160.INC
;********************************
;*
RAM definition
*
;********************************
RAM
DIRSEG PUBLIC
;
AD_KEY
RB
1
; A/D key data buffer
AD_KEY_FLAG
RB
0
; A/D key flag area
F_ADIN
RBIT
1
; A/D entry flag
F_ADREQ
RBIT
1
; A/D conversion request flag
;
RAM
ENDS
;
AD_KEY
CSEG
PUBLIC
;
EXTRN
AD_KEY_VAL
; Routine processing for A/D key fixed
;********************************
;*
Initialization
*
;********************************
RESET:
MOV
SYCC,#1000111B
; Set the highest speed mode of main clock
;
MOVW
SP,#0180H
; Set the stack pointer
’
;
MOV
PDR5,#0FFH
; Initialize P50 to P57 ("H" output)
MOV
MOV
ADC1,#01110000B
ADC2,#00000001B
; Set the A/D converter control register
MOV
MOV
AD_KEY,#00H
AD_KEY_FLAG,#00H
; Clear the A/D key data buffer
; Clear the A/D key flag area
MOV
ILR3,#00111111B
; Set the A/D interrupt level
MOVW
MOVW
A,#0070H
PS,A
; Enable the interrupt
;
;
;
;
SETB
F_ADREQ
;********************************
;*
Main routine
*
;********************************
MAIN:
CALL
AD_EN
;
BBC
F_ADIN,MAIN
;
CLRB
F_ADIN
;
CALL
AD_KEY_VAL
;
SETB
F_ADREQ
;
JMP
MAIN
;********************************
;* Activation of A/D conversion *
;********************************
AD_EN:
BBC
F_ADREQ,AD_EN_EXT
;
CLRB
F_ADREQ
MOV
ADC2,#00001001B
SETB
PDR5:7
CLRB
PDR5:6
MOV
ADC1,#01110001B
AD_EN_EXT:
RET
30
; Set the A/D conversion request flag
; Start the A/D conversion
; A/D entry flag = 1?
; Clear the A/D entry flag
; Processing for A/D key fixed
; Set the A/D conversion request flag
; A/D conversion request flag = 1?
;
;
;
;
;
Clear the A/D conversion request flag
Set the A/D converter
Output "H" to PDR5:7 (P57)
Output "L" to PDR5:6 (P56)
Start the A/D converter
CHAPTER 2 KEY SCAN USING A/D CONVERSION
;*****************************
;*
A/D interrupt
*
;*****************************
AD READ INT:
PUSHW
A
XCHW
A,T
PUSHW
A
;
CLRB
ADI
;
SETB
PDR5:6
;
MOV
A,ADCD
MOV
AD_KEY,A
;
;
SETB
F_ADIN
POPW
XCHW
POPW
RETI
A
A,T
A
;
AD_KEY
ENDS
;********************************
;*
Vector address
*
;********************************
VECTOR
CSEG
ABS
ORG
0FFE4H
DW
AD_READ_INT
;
ORG
0FFFCH
DB
00H
DB
00H
DW
RESET
VECTOR
ENDS
END
; Save register
; Clear the A/D interrupt request flag
; Output "H" to PDR5:6(P56)
; Read the A/D conversion data
; Store the A/D conversion data
; Set the A/D entry flag
; Return register
; A/D interrupt vector
; Reset mode
; Reset vector
31
Memo
32
CHAPTER 3
LCD CLOCK DISPLAY
This chapter describes a sample program for LCD clock display.
The F2MC-8L series provides the watch mode as an operation mode to restrain the
power consumption.
With the system put in this mode, all operations stop until the system is waken up by
an interrupt of the watch pre-scaler cycle using a subclock or an external interrupt.
3.1 Specifications of the LCD Clock Display Sample Program
3.2 Segment Layout Drawing for LCD Clock Display
3.3 Skeletonized Flowchart for LCD Clock Display
3.4 Resource Registers and RAM for LCD Clock Display
3.5 Register Initialization for LCD Clock Display
3.6 Detailed Flowchart for LCD Clock Display
3.7 Sample Program for LCD Clock Display
33
CHAPTER 3 LCD CLOCK DISPLAY
3.1
Specifications of the LCD Clock Display Sample Program
LCD clock display uses 24-hour clock measure to display the time in hours, minutes,
and seconds.
■ Specifications of the LCD Clock Display Sample Program
The specifications of the LCD clock display sample program for the F2MC-8L family assume the
following conditions:
❍ Applicable series: MB89160/160A
•
Main clock ............ 4.194 MHz
•
Subclock............... 32.768 KHz
❍ LCD display ports
•
P32, P33............... C0, C1 capacity terminals
•
P40 to P47............ Segment output ports
•
P40 to P67............ Segment output ports
•
P70, P71............... Common output ports
•
COM0, COM1....... Common output ports
•
The transistors of ports for LCD control should be set to ‘off’ in advance.
■ Operation outline of the LCD clock display sample program
❍ Ordinary mode
The ordinary operation is to be under the watch mode to maintain the low-power
consumption.
❍ Wake-up from the watch mode
The watch pre-scaler wakes up the system every second to switch to the main mode.
In the main mode, the time is updated and LDC display is edited and output.
34
CHAPTER 3 LCD CLOCK DISPLAY
3.2
Segment Layout Drawing for LCD Clock Display
Figure 3.2 shows a segment layout drawing for LCD clock display.
■ Segment layout drawing for LCD clock display
1/3 duty, 1/3 bias driving system
Display RAM
Address
COM3
COM2
COM1
COM0
—
0
1
1
seg0
—
0
1
1
seg1
—
1
1
0
seg2
—
1
1
1
seg3
—
1
1
0
seg4
—
1
1
0
seg5
—
1
1
1
seg6
—
1
1
1
seg7
—
1
0
0
seg8
—
1
1
1
seg9
—
1
1
1
seg10
—
1
1
0
seg11
—
1
1
1
seg12
—
1
0
0
seg13
—
1
0
0
seg14
—
0
1
1
seg15
—
1
1
1
seg16
—
1
1
0
seg17
—
0
1
1
seg18
—
1
1
1
seg19
—
1
0
0
seg20
—
1
1
1
seg21
—
0
1
0
seg22
—
1
0
0
seg23
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
COM0 to COM2: Terminal Nos.57 to 59
SEG0 to SEG19: Terminal Nos.61 to 80
SEG20 to SEG23: Terminal Nos.1 to 4
Figure 3.2 Segment layout drawing for LCD clock display
35
CHAPTER 3 LCD CLOCK DISPLAY
3.3
Skeletonized Flowchart for LCD Clock Display
Figure 3.3 shows a skeletonized flowchart for LCD clock display.
■ Skeletonized flowchart for LCD clock display
The watch interrupt (to be set to 1-sec cycle)
No
Main routine
Wake-up
Go to the watch mode
Transition to the main mode
Does the 1-sec
time-out occur?
Inform the 1-sec time-out
End of processing
Yes
Update time
Output LCD
Transition to the subclock mode
Figure 3.3 Skeletonized flowchart for LCD clock display
36
CHAPTER 3 LCD CLOCK DISPLAY
3.4
Resource Registers and RAM for LCD Clock Display
LCD clock display uses the following resources to set registers and allocate RAM.
• The watch interrupt (wake-up)
• The standby control (the watch mode)
• The LCD controller
■ Resource registers used for LCD clock display
Table 3.4a lists the resource registers used for LCD clock display.
Table 3.4a Resource registers used for LCD clock display
Address
Register
Register contents
07H
SYCC
The system clock control register
08H
STBC
The standby control register
0BH
WPCR
The watch pre-scaler control register
0CH
PDR3
The port 3 data register
0EH
PDR4
The port 4 data register
12H
PDR6
The port 6 data register
13H
PDR7
The port 7 data register
60H to 6BH
VRAM
The LCD display data RAM register
72H
LCDR
The LCD control register
7EH
ILR3
The interrupt level set register 3
■ RAM allocations for LCD clock display
Table 3.4b lists RAM allocations for LCD clock display.
Table 3.4b RAM allocations for LCD clock display
Address
Symbol
Function
80H
FLAGS
Each type of flag area
81H
82H
to
86H
CLOCK
+1
to
+5
The watch time management
87H
88H
to
92H
LCD_EDT
+1
to
+11
The LCD display edit area
37
CHAPTER 3 LCD CLOCK DISPLAY
3.5
Register Initialization for LCD Clock Display
This section describes the following types of initializing the registers used for the LCD
clock display sample program:
• Initialization for the system clock control register (SYCC)
• Initialization for the standby control register (STBC)
• Initialization for the watch prescaler control register (WPCR)
• Initialization for the input/output ports (PDR4/6/7)
• Initialization for the LCD control register (LCDR)
• Initialization for the interrupt level set register (ILR3)
■ Register and RAM initialization for the LCD clock display sample program
❍ Initializing the system clock control register (SYCC)
SYCC
7 6 5 4 3 2 1 0
1 0 0 1 0 1 1 1
* *
CS1, CS0: System operation clock 4/fch = 0.95 µs
SCS: Sets the system clock to the main clock
WT1, WT0: Oscillation stabilization time 212/fch = 0.97 ms
SCM: System clock monitor bit
(When selecting the main clock)
* Unused bits are set to 0.
❍ Initializing the standby control register (STBC)
STBC
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
*
* *
*
*
*
*
TMD: Sets the watch bit to the ordinary mode.
* Unused bits are set to 0.
❍ Initializing the watch prescaler control register (WPCR)
SYCC
7 6 5 4 3 2 1 0
0 1 0 0 0 1 1 0
*
*
*
* Unused bits are set to 0.
38
WCLR: Clears the watch prescaler
WS1, WS0: The watch interval time 215/fc1 = 1sec
WIE: Enables the watch interrupt
WIF: Clears the watch interrupt request flag
CHAPTER 3 LCD CLOCK DISPLAY
❍ Initializing the input/output ports (PDR/6/7)
PDR4
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
PDR6
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
PDR7
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 1
Initializes the LCD control ports
(Sets the transistor of port in use to off.)
* * * * * *
* Unused bits are set to 0.
❍ Initializing the LCD control register (LCDR)
LCDR
7 6 5 4 3 2 1 0
1 1 1 0 1 0 0 0
*
*
*
MS1, MS0: Selects 1/3 duty
VSEL: Continuity of the internal division resistance
LCEN: Operation even in the watch mode
CSS: Generates the frame frequency by subclock
* Unused bits are set to 0.
❍ Initializing the interrupt level set register (ILR3)
ILR3
7 6 5 4 3 2 1 0
1 1 1 1 1 1 0 0
*
*
*
*
*
*
L81, L80: Sets the watch interrupt level to ‘1’
* Unused bits are set to 1.
39
CHAPTER 3 LCD CLOCK DISPLAY
3.6
Detailed Flowchart for LCD Clock Display
Figure 3.6 shows a detailed flowchart for LCD clock display.
See also Sections 3.6.1 and 3.6.2 for the detailed flowcharts for the following two
processes:
• The watch update (See Section 3.6.1.)
• The display editing, LCD output, and LCD segment output (See Section 3.6.2.)
■ Detailed flowchart for LCD clock display
Reset
CLKINT
Initialization respectively such
as RAM area
MAIN
WIF ← “0”
SCS ← “0”
TMD ← “1”
SCM=0?
No
T1SOUT=1?
Yes
T1SOUT ← “0”
Yes
T1SOUT ← “0”
RETI
Update the CLOCKSB time
Edit the DSP_EDT display
Output the OUTPUT LCD
SCS ← “0”
SCM=0?
No
Yes
Figure 3.6 Detailed flowchart for LCD clock display
40
No
3.6 Detailed Flowchart for LCD Clock Display
3.6.1 Detailed Flowchart for LCD Clock Display (The Watch Update)
Figure 3.6.1 shows a detailed flowchart for the LCD clock update.
■ Detailed flowchart for LCD clock display (the watch update)
The watch update
CLOCKSB
(CLOCK+5) INC.
(CLOCK+5)=#0AH
Yes
(CLOCK+5) ←#0
(CLOCK+4) INC.
(CLOCK+4)=#06H
Yes
(CLOCK+4) ←#0
(CLOCK+3) INC.
(CLOCK+3)=#0AH
Yes
(CLOCK+3) ←#0
(CLOCK+2) INC.
(CLOCK+2)=#06H
Yes
(CLOCK+2) ←#0
(CLOCK+1) INC.
(CLOCK+1)=#0AH
Yes
(CLOCK+1) ←#0
(CLOCK) INC.
No
(CLOCK)=#0BH
Yes
(CLOCK) ←#1
No
No
No
No
No
(CLOCK+1, 0)=#0A00H
Yes
(CLOCK+1, 0) ←#0A00H
(CLOCK+3, 2) ←#0
(CLOCK+5, 4) ←#0
No
RET
Figure 3.6.1 Detailed flowchart for LCD clock display (the watch update)
41
3.6 Detailed Flowchart for LCD Clock Display
3.6.2 Detailed Flowchart for LCD Clock Display
(Editing the Display, LCD Output, and LCD Segment Output)
Figure 3.6.2 shows a detailed flowchart for editing the LCD clock display, LCD output,
and LCD segment output.
■ Detailed flowchart for LCD clock display (Editing the display, LCD output, and LCD segment output)
Editing the display
DSP_EDT
LCD output
OUTPUT
Clear DSP_EDT+0 to 11
(VRAM + 0 to 11)←
DSP_EDT + 0 to 11
Output of the SEG_EDT
LCD segment
LCDR ← #0E8H
RET
RET
Output of the LCD segment
SEG_EDT
Search for SEGTBL1 with (CLOCK+5)
(LCD_EDT+1, 0) ← The search data or (LCD_EDT+1, 0)
Search for SEGTBL2 with (CLOCK+4)
(LCD_EDT+2, 1) ← The search data or (LCD_EDT+1, 0)
Search for SEGTBL1 with (CLOCK+3)
(LCD_EDT+4, 3) ← The search data or (LCD_EDT+4, 3)
Search for SEGTBL2 with (CLOCK+2)
(LCD_EDT+5, 4) ← The search data or (LCD_EDT+5, 4)
Search for SEGTBL1 with (CLOCK+1)
(LCD_EDT+7, 6) ← The search data or (LCD_EDT+7, 6)
Search for SEGTBL2 with (CLOCK+0)
(LCD_EDT+8, 7) ← The search data or (LCD_EDT+8, 7)
RET
Figure 3.6.2 Detailed flowchart for LCD clock display
(Editing the display, LCD output, and LCD segment output)
42
Memo
43
CHAPTER 3 LCD CLOCK DISPLAY
3.7
Sample Program for LCD Clock Display
This section provides a sample program for LCD clock display.
■ Sample program for LCD clock display
NAME
LCD DISP
;***************************************************************
;*
*
;*
LCD watch display sample program
*
;*
*
;***************************************************************
&INCLUDE
R160.INC
;********************************
;*
RAM definition
*
;********************************
RAM
DIRSEG ABS
;
ORG
0080H
;
FLAGS
RB
0
TlS_OUT
RBIT
1
; 1-sec time OUT notification flag
RBIT
1
; Unused
RBIT
1
; Unused
RBIT
1
; Unused
RBIT
1
; Unused
RBIT
1
; Unused
RBIT
1
; Unused
RBIT
1
; Unused
;
CLOCK
RB
6
; Time count area
;
LCD_EDT
RB
12
; LCD display edit area
RAM
ENDS
;
;
LCD_DISP
CSEG
PUBLIC
;********************************
;*
Initialization
*
;********************************
RESET:
MOV
SYCC,#10010lllb
;
MOVW
SP,#0180H
MOVW
A,#0070H
MOVW
PS,A
;
MOVW
EP,#080H
RAMCLR:
MOVW
A,#0
MOV
@EP,A
MOVW
A,EP
INCW
EP
MOVW
A,#180H
CMPW
A
BNZ
RAMCLR
;
MOV
PDR4,#llllllllb
;
MOV
PDR6,#Illlllllb
;
MOV
PDR7,#0000001lb
;
MOV
A,#0AH
MOV
CLOCK,A
;
MOV
ILR3,#11111100B
;
MOV
WPCR,#01000110B
;
44
; Set the system clock
; Set the stack pointer
; Set PS
; Clear RAM (80h to 180h)
; Set the LCD control port
; Set the LCD control port
; Set the LCD control port
;
; Set the interrupt level
; Set the watch prescaler control register
CHAPTER 3 LCD CLOCK DISPLAY
;********************************
;*
Main routine
*
;********************************
MAIN:
SETB
TMD
;
NOP
NOP
NOP
;
BBC
TLS_OUT,MAIN
;
CLRB
TlS_CUT
;
CALL
CLOCKSB
;
CALL
DSP_EDT
;
CALL
OUTPUT
;
MAIN20:
CLRB
SCS
;
NOP
NOP
NOP
;
MAIN30:
BBS
SCM,MAIN30
;
JMP
MAIN
;********************************
;*
Time update processing *
;********************************
CLOCKSB:
MOV
A,CLOCK+5
INCW
A
MOV
CLOCK+5,A
CMP
CLOCK+5,#10
BNZ
CLOCK_EXT
;
MOV
CLOCK+5,#0
;
MOV
A,CLOCK+4
INCW
A
MOV
CLOCK+4,A
CMP
CLOCK+4,#6
BNZ
CLOCK+EXT
;
MOV
CLOCK+4,#0
;
MOV
A,CLOCK+3
INCW
A
MOV
CLOCK+3,A
CMP
CLOCK+3,#10
BNZ
CLOCK_EXT
;
MOV
CLOCK+3,#0
;
MOV
A,CLOCK+2
INCW
A
MOV
CLOCK+2,A
CMP
CLOCK+2,#6
BNZ
CLOCK_EXT
;
MOV
CLOCK+2,#0
;
MOV
A,CLOCK+L
INCW
A
MOV
CLOCK+1,A
CMP
CLOCK+l,#10
BNZ
CLOCK_100
;
MOV
CLOCK+l,#0
; Start the clock mode
; Is 1-sec time-out notified?
; Clear the 1-sec time-out notification flag
; Time update processing
; LCD display edit processing
; LCD display output processing
; Select the subclock
; Is the subclock completely switched?
; Update the 1-second place
; Update the 10-second place
; Update the 1-minute place
; Update the 10-minute place
; Update the 1-hour place
45
CHAPTER 3 LCD CLOCK DISPLAY
;
MOV
INCW
CMP
BNZ
A,CLOCK
A
A,#0BH
CLOCK_050
;
MOV
A,#l
;
CLOCK_050:
MOV
CLOCK,A
;
CLOCK_EXT:
RET
;
CLOCK_100:
MOVW
A,CLOCK
MOVW
A,#0204H
CMPW
A
BNZ
CLOCK_EXT
;
MOVW
A,#0A00H
MOVW
CLOCK,A
;
MOVW
A,#0
MOVW
CLOCK+2,A
MOVW
CLOCK+4,A
;
RET
;
;
;********************************
;* LCD display edit processing *
;********************************
DSP_EDT:
MOVW
IX,#LCD_EDT
;
DSP_000:
MOV
A,#0
MOV
@IX,A
INCW
IX
MOVW
A,IX
MOVW
A,#LCD_EDT+12
CMPW
A
BNZ
DSP_000
;
CALL
SEG_EDT
;
RET
;********************************
;*
Segment data set
*
;********************************
SEG_EDT:
MOVW
EP,#CLOCK+5
MOVW
IX,#LCD_EDT
;
SEG_020:
MOVW
A,#0
CLRC
MOV
A,@EP
ROLC
A
CLRC
MOVW
A,#SEG_TBL1
ADDCW
A
MOVW
A,@A
MOVW
@IX,A
;
INCW
IX
DECW
EP
;
MOVW
A,#0
CLRC
MOV
A,@EP
ROLC
A
46
; Update the 10-hour place
; 24 hours?
; Set the display data to 0:00
; Clear the LCD display edit RAM
; Are all areas completely cleared?
; Set the segment data
CHAPTER 3 LCD CLOCK DISPLAY
MOVW
CLRC
ADDCW
MOVW
MOVW
ORW
MOVW
A,#SEG_TBL2
DECW
INCW
INCW
EP
IX
IX
MOVW
MOVW
CMPW
BNZ
A,EP
A,#CLOCK-1
A
SEG_020
A
A,@A
A,@IX
A
@IX,A
;
;
;
RET
;
;
;********************************
;* LCD display output processing*
;********************************
OUTPUT:
MOVW
IX,#LCD_EDT
MOVW
EP,#VRAM
;
OUT_010:
MOV
MOV
A,@IX
@EP,A
INCW
INCW
IX
EP
MOVW
MOVW
CMPW
BNZ
A,IX
A,#LCD_EDT+12
A
OUT_P10
MOV
72H,#11101000b
; Transfer the LCD display edit area to the LCD
display register
;
;
; Are all areas completely transferred?
;
;
;
;
;
;
RET
;
;
;*****************************
;* Watch interrupt processing*
;*****************************
CLKINT:
CLRB
WIF
;
SETB
SCS
;
NOP
NOP
NOP
;
CLKINT_001
BBC
SCM,CLKINT_001
;
SETB
T1S_OUT
;
RETI
;
;
;
;**********************************
;*LCD display segment data table 1*
;**********************************
SEG TBL1:
DB
56H
DB
06H
1/3 duty
Enable the built-in division resistance
Operate in the watch mode
Start the subclock
; Clear the watch interrupt request flag
; Select the main mode
; Is the main mode completely switched?
; Set the 1-sec time-out notification flag
; (0)
47
CHAPTER 3 LCD CLOCK DISPLAY
;
DB
DB
06H
00H
; (1)
DB
DB
74H
02H
; (2)
DB
DB
76H
00H
; (3)
DB
DB
26H
04H
; (4)
DB
DB
72H
04H
; (5)
DB
DB
72H
06H
; (6)
DB
DB
46H
04H
; (7)
DB
DB
76H
06H
; (8)
DB
DB
76H
04H
; (9)
DB
DB
00H
00H
; (10)
;
;
;
;
;
;
;
;
;
;
;
;**********************************
;*LCD display segment data table 2*
;**********************************
SEG_TBL2:
DB
60H
DB
65H
;
DB
60H
DB
00H
;
DB
40H
DB
27H
;
DB
60H
DB
07H
;
DB
60H
DB
42H
;
DB
20H
DB
47H
;
DB
20H
DB
67H
;
DB
60H
DB
44H
;
DB
60H
DB
67H
;
DB
60H
DB
47H
;
DB
00H
DB
00H
;
;
;
ENDS
;
48
; (0)
; (1)
; (2)
;(3)
;(4)
;(5)
;(6)
;(7)
;(8)
;(9)
;(10)
CHAPTER 3 LCD CLOCK DISPLAY
;*********************************
;*
Each type of vector
*
;*********************************
VECTOR
CSEG
ABS
;
ORG
0FFEAH
DW
CLKINT
ORG
DB
DB
DW
;
VECTOR
;
0FFFCH
00H
00H
RESET
; The watch interrupt;
; Reset mode
; Reset vector
ENDS
END
49
Memo
50
CHAPTER 4
SOFTWARE UART
This chapter describes a sample program for implementing a UART by means of
software.
Some of F2MC-8L series include the UART resources, but others don’t include or don’t
have sufficient UART resources.
In these cases, this software UART is available, and realizes a transmission-reception
type of UART such as RS-232C that prevails as a personal computer communication
port.
4.1 Specifications of the Software UART Sample Program
4.2 Outline of Flowchart for Software UART
4.3 Resource Registers and RAM for Software UART
4.4 Register and RAM Initialization for Software UART
4.5 Detailed Flowchart for Software UART
4.6 Sample Program for Software UART
51
CHAPTER 4 SOFTWARE UART
4.1
Specifications of the Software UART Sample Program
The software UART can transmit and receive 7- or 8-bit data using the half-duplex
communications protocol. It also has the functions for transmitting and receiving the
stop and parity bits.
■ Conditions for the Software UART Sample Program
The specifications of the software UART sample program for the F2MC-8L series assume the
following conditions:
❍ Applicable series: MB89160/160A
•
Main clock ............ 4.194 MHz
•
Subclock............... 32.768 KHz
❍ Resources in use
•
External interrupt1 .......... INT10
•
8-bit PWM timer 1
❍ Ports in use
•
Input ................ P10/INT10
•
Output.............. P11/INT11 (Used as P11)
❍ Features of software UART
•
Transmission speed ....... 2400 bps
•
Protocol .......................... Half-duplex communication
•
Data bit length ................ 7/8 bits selectable
•
Stop bit ........................... 1/2 bits selectable
•
Parity bit ......................... Non/odd/even selectable
■ Circuit diagram for the software UART sample program
Figure 4.1a shows a circuit diagram for the software UART sample program.
VCC
MB89160/160A
P10/INT10
VCC
P11/INT11
VSS
RST
X0A X1A X0
32.768 kHz
Received data
Transmitting data
X1
4.194 MHz
Figure 4.1a Circuit diagram for the software UART sample program
52
CHAPTER 4 SOFTWARE UART
■ Data received by the software UART sample program
Figure 4.1b illustrates the format of data received by the software UART sample program.
Setting: 2 stop bits with parity
1 2 3 4 5 6 7 8 9 P S S
Enter the data every 2nd timer interrupt.
Complete the reception after checking the stop bit.
Occurrence of the external interrupt
Start the 1/2-bit cycle timer interrupt in the external interrupt routine.
Figure 4.1b Format of data received by the software UART sample program
■ Data transmitted by the software UART sample program
Figure 4.1c illustrates the format of data transmitted by the software UART sample program.
Setting: 2 stop bits with parity
1 2 3 4 5 6 7 8 9 P S S
Output data every 2nd timer interrupt.
Complete the transmission after transmitting the stop bit.
If no transmission is currently performed, start the 1/2-bit cycle timer interrupt.
If transmission is currently performed, wait for transmission to be completed.
Figure 4.1c The transmitting data format of the software UART sample program
53
CHAPTER 4 SOFTWARE UART
4.2
Skeletonized Flowchart for Software UART
Figure 4.2a shows a skeletonized flowchart for software UART; Figure 4.2b shows an
skeletonized flowchart for external and timer interrupts.
■ Skeletonized flowchart for software UART
Main routine
Initialization
UART initialization
Check the reception
No
Is data received?
Yes
Obtainment of the received data
Transmission start processing
UART initialization
Transmission start processing
Clear the transmitting/receiving buffer
Create the data
(add the start bit and parity)
Check the reception
No
Is data received?
Set the each data
Yes
Disable the external interrupts
Set the interrupt
Convert the data
Start the timer interrupt
End of processing
Check the error
End of processing
End of processing
Obtainment of the received data
Return receiving buffer
Clear the error flag and so on
End of processing
Figure 4.2a Skeletonized flowchart for software UART
54
CHAPTER 4 SOFTWARE UART
External interrupt
(for reception)
Start the timer interrupt
Clear the transmitting/receiving
buffer and so on
End of processing
Timer interrupt
Yes
Under receiving?
Store the received data
No
Output data
Check the reception to be completed.
Check the overrun error.
Is the reception completed?
No
Yes
Waiting for transmission?
Yes
Yes
Is the transmission
completed?
No
No
Stop the timer.
Enable the external interrupts
End of processing
Figure 4.2b Skeletonized flowchart for software UART
(External and timer interrupts)
55
CHAPTER 4 SOFTWARE UART
4.3
Resource Registers and RAM for Software UART
Software UART uses the following two resources to set the registers and allocate RAM.
• External interrupt 1 (UART receiving port for the start bit detection interrupt and
the timer interrupt)
• 8-bit PWM timer 1 (UART transmission and reception)
■ Resource registers used for software UART
Table 4.3a lists the resource registers used for software UART.
Table 4.3a Resource registers for software UART
Address
56
Register
Register contents
02H
PDR1
Port 1 data register
03H
DDR1
Port 1 input/output direction register
07H
SYCC
System clock control register
1EH
CNTR1
PWM1 control register
1FH
COMP1
PWM1 compare register
30H
EIE1
External interrupt 1 control register 1
31H
EIF1
External interrupt 1 flag 1
7CH
ILR1
Interrupt level set register 1
7EH
ILR3
Interrupt level set register 3
CHAPTER 4 SOFTWARE UART
■ RAM allocations for software UART
Table 4.3b lists RAM allocations for software UART.
Table 4.3b RAM allocations for software UART
Address
Symbol
Function
80H
UMODE
Data area for mode
81H
FLAG_ERROR
Error flag area
82H
FLAG
Flag area
83H
BITC
Bit counter
84H
85H
TMBUF
86H
TMDTBUF
Transmitting data buffer
87H
TMBITC
Transmitting bit counter
88H
89H
RCVBUF
+1
Receiving buffer
8AH
8BH
RCVDTBUF
+1
Received data buffer
8CH
RCVBITCT
Received bit counter
Transmitting buffer
+1
■ Contents of flags for software UART
Table 4.3c lists the contents of flags for software UART.
Table 4.3c Contents of flags for software UART
Address
Bit
Symbol
Function
0
F_DT1
Data length 0: 7 bits
1
F_PRTY0
Parity 0
2
F_PRTY1
Parity 1
3
F_STOP
Stop bit
0
F_RCVDTRDY
Normal receiving flag
1: Normal
1
F_EROVR
Overrun error flag
1: Overrun error
2
F_ERFR
Framing error flag
1: Framing error
3
F_ERPRTY
Parity error flag
1: Parity error
0
F_MDTRN
Transmittng mode
1: Under transmitting
1
F_MDRCV
Receiving mode
1: Under receiving
2
F_RCVTIMING
Receiving timing bit
1: Entry of received data
3
F_TRNTIMING
Transmission timing bit 1: Output of transmitting data
4
F_RCVDT
Received data present/not present
5
F_PARITY
Parity storing bit
6
F_CNVRQ
Received data conversion request bit 1: Conversion
requested
1: 8 bits
0: No parity when parity 1 = 0
80H
1: Odd number
0: 1 stop bit 1: 2 stop bits
81H
82H
1: Data present
57
CHAPTER 4 SOFTWARE UART
4.4
Register and RAM Initialization for Software UART
This section describes the following initializations of the registers and RAM for
software UART:
• Initialization for the input/output ports (PDR1 and DDR1)
• Initialization for the system clock control register (SYCC)
• Initialization for the 8-bit PWM1 timer control register (CNTR1)
• Initialization for the 8-bit PWM1 timer compare register (COMP1)
• Initialization for the external interrupt 1 control registers (EIE1 and EIF1)
• Initialization for the interrupt level set registers (ILR1 and ILR3)
■ Register and RAM initialization for software UART
❍ Initializing the input/output ports (PDR1, DDR1)
7 6 5 4 3 2 1 0
PDR1 0 0 0 0 0 0 1 –
*
*
*
*
*
*
P10: For received data input ('0' or '1')
P11: For transmitting data output ('H' output)
7 6 5 4 3 2 1 0
PDR2 0 0 0 0 0 0 1 0
* * * *
P10: Set to input port
P11: Set to output port
* Ports are set to input ports because of unused ports.
❍ Initializing the system clock control register (SYCC)
7 6 5 4 3 2 1 0
SYCC 0 0 0 0 1 1 1 1
*
*
*
CS1, CS0: System operation clock 4/fch = 0.95 µs
SCS: Set the system clock to the main clock
WT1, WT0: Oscillation stabilization time 216/fch = 15.6 ms
* Unused bits are set to 0.
58
CHAPTER 4 SOFTWARE UART
❍ Initializing the 8-bit PWM1 timer control register (CNTR1)
•
For reset (stops the timer 1 count operation and disables the timer interrupt)
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
CNTR1
*
•
When starting to transmit/receive
7 6 5 4 3 2 1 0
0 0 0 0 1 0 0 1
CNTR1
*
TIE: Enables the timer 1 interrupt
OE: Sets P27/P31 to general ports
TIR: Clears the timer 1 interrupt request flag
TPE: Starts the timer 1 count operation
P1, P0: Sets the count clock to 1 instruction cycle
P/TX: Timer operation mode
* Unused bits are set to 0.
❍ Initializing the 8-bit PWM1 timer compare register (COMP1)
COMP1
7 6 5 4 3 2 1 0
1 1 0 1 1 0 1 0
Sets H' D9 (D'217)
fch = 4.2 MHz (main clock)
1 instruction cycle = 0.95µs (4/fch)
1[sec] ÷ (2400[bps]X0.954[µS]X2)-1 = 217
❍ Initializing the external interrupt 1 control register (EIE1, EIF1)
EIE1
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
*
*
*
*
*
*
IE10: Permits INT10
SIV0: Start interrupt at the rising edge
EIF1
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
*
*
*
*
*
*
*
IF10: Clears the interrupt factor flag
* Unused bits are set to 0.
59
CHAPTER 4 SOFTWARE UART
❍ Initializing the interrupt level set register (ILR1, ILR3)
ILR1
7 6 5 4 3 2 1 0
1 1 1 1 1 1 0 0
*
ILR3
*
*
*
*
*
L01, L00: Sets the external interrupt 1 level to 1
7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1
*
*
*
*
*
*
* Unused bits are set to 1.
60
L91, L90: Sets the PWM timer 1 interrupt level to 1
CHAPTER 4 SOFTWARE UART
4.5
Detailed Flowchart for Software UART
Figure 4.5 shows a detailed flowchart for software UART.
See also "Sections 4.5.1 to 4.5.3" for the detailed flowcharts for the following
processes:
• Software UART initialization and transmitting start processing (See "Section
4.5.1.")
• Receiving check, external interrupt (for reception), and received-data
obtainment (See "Section 4.5.2.")
• Timer interrupt (See "Section 4.5.3.")
■ Detailed flowchart for software UART
RESET
Initialization
_INITIAL
Set the stack pointer
Disable the interrupt
_INITIAL
Initialization
Clear the Flag area
_SUART_INITIAL
UART initialization
MAIN
_SUART_RCVCHK
Receiving check
Set the system operation clock
(4/fch = 0.95µs)
Clear RAM
Set the register bank pointer
RET
No
Is the data received?
Yes
_SUART_RECEIVE
Obtainment of the received data
_SUART_TRANS
Transmitting start processing
Figure 4.5 Detailed flowchart for software UART
61
4.5 Detailed Flowchart for Software UART
4.5.1 Detailed Flowchart for Software UART
(UART Initialization and Transmission Start Processing)
Figure 4.5.1 shows a detailed flowchart for initialization and transmitting start
processing of software UART.
■ Detailed flowchart for software UART (UART initialization and transmitting start processing)
UART Initialization
_SUART_INITIAL
Transmitting start processing
_SUART_TRANS
Clear the transmitting/receiving buffer
Edit the transmitting data
Clear the Flag area
Yes
Being transmitted?
Transmitting output signal 'H'
No
Set the bit length
Clear the transmitting timing flag
Set the parity
Disable the external interrupt
Set the stop bit
Output the transmitting request
Enable the external interrupt
No
Is the reception completed?
Stop the PWM timer
RET
Yes
Start the timer interrupt
RET
Figure 4.5.1 Detailed flowchart for software UART
(UART initialization and transmitting start processing)
62
4.5 Detailed Flowchart for Software UART
4.5.2 Detailed Flowchart for Software UART (Receiving check,
external interrupt, and received data obtainment)
Figure 4.5.2 shows a detailed flowchart for receiving check, external interrupt for
reception, and received data obtainment of software UART.
■ Detailed flowchart for software UART (receiving check, external interrupt, and received data obtainment)
Receiving check
_SUART_RCVCHK
External interrupt (for reception)
_SUART_INTERRUPT
Start the PWM timer, interrupt
No
Is the conversion requested?
Clear the external interrupt source
Yes
Clear the conversion request flag
Disable the external interrupt
Check for framing error
Save the A/T register
Create the parity
Clear the receiving buffer
Check the bit length
Clear the receiving bit counter
Check the parity
Set the mode to reception
Return the received results
Return the A/T register
RET
RET
Obtainment of the received data
_SUART_RECEIVE
Clear the receiving error flag
Return the received data
RET
Figure 4.5.2 Detailed flowchart for software UART
(Receiving check, external interrupt, and received data obtainment)
63
4.5 Detailed Flowchart for Software UART
4.5.3 Detailed Flowchart for Software UART (Timer interrupt)
Figure 4.5.3 shows a detailed flowchart for timer interrupt of software UART.
■ Detailed flowchart for software UART (timer interrupt)
Timer interrupt
_SUART_TIMER
Save the A/T register
Yes
Receiving mode?
No
Does the transmitting
timing coincide with?
Does the receiving
timing coincide with?
No
No
Yes
Store the received data
Yes
Output the data
Is the reception completed?
No
Is the transmission
completed?
No
Yes
Clear the receiving mode
Yes
Clear the transmitting mode
Does the overrun
error occur?
Stop the timer
Yes
Clear the receiving flag
Enable the external interrupt
Yes
No
Set the receiving flag
Wait for transmission?
No
Stop the timer interrupt
Enable the external interrupt
Return the A/T register
RET I
Figure 4.5.3 Detailed flowchart for software UART (timer interrupt)
64
Memo
65
CHAPTER 4 SOFTWARE UART
4.6
Sample Program for Software UART
This section provides a sample program for software UART.
■ Sample program for software UART
NAME
SUART
;********************************************************
;*
Software UART sample program
*
;********************************************************
$INCLUDE
R160.INC
;********************************
;*
RAM definition
*
;********************************
SSEG
PUBLIC STACK_TOP
; Stack definition
RW
32
STACK_TOP
RW
0
ENDS
;
RAM
DIRSEG ABS
ORG
80H
UMODE
RB
0
; Data area for mode
F_DTL
RBIT 1
; Data length
F_PRTY0
RBIT 1
; Parity
F_PRTY1
RBIT 1
; Parity
F_$TOP
RBIT 1
; Stop bit
RBIT 1
; Dummy bit
RBIT 1
; Dummy bit
RBIT 1
; Dummy bit
RBIT 1
; Dummy bit
;
PLAG_ERROR
RB
0
; Error flag area
F_RCVDTRDY
RBIT 1
; The received data is present
F_ERORR
RBIT 1
; Overrun error
F_ERFR
RBIT 1
; Framing error
F_ERPRTY
RBIT 1
; Parity error
RBIT 1
; Dummy bit
RBIT 1
; Dummy bit
RBIT 1
; Dummy bit
RBIT 1
; Dummy bit
;
FLAG
RB
0
; Flag area
F_MDTRN
RBIT 1
; Transmitting mode
F_MDRCV
RBIT 1
; Receiving mode
F_RCVTIMING
RBIT 1
; Receiving timing bit
F_TRNTIMING
RBIT 1
; Transmitting timing bit
F_RCVDT
RBIT 1
; Received data presence flag
F_PARITY
RBIT 1
; For storing parity
F_CNVRQ
RBIT 1
; Received data conversion
request
RBIT 1
; Dummy bit
;
BITCT
RB
1
; Bit counter
;
TRNBUFF
RW
1
; Transmitting buffer
TRNDTBUFF
RB
1
; Transmitting data buffer
TRNBITCT
RB
1
; Transmitting bit counter
;
RCVBUFF
RW
1
; Receiving buffer
RCVDTBUFF
RW
1
; Received data buffer
RCVBITCT
RB
1
; Receiving bit counter
;
RAM
ENDS
PROG
CSEG
PUBLIC RESET
;********************************
;*
Initialization
*
;********************************
RESET:
MOVW
SP,#STACK_TOP
;
MOVW
A,#H'0030
MOVW
PS,A
66
UMODE:0
UMODE:1
UMODE:2
UMODE:3
UMODE:4
UMODE:5
UMODE:6
UMODE:7
FLAG_ERROR:0
FLAG_ERROR:l
FLAG_ERROR:2
FLAG_ERROR:3
FLAG_ERROR:4
FLAG_ERROR:5
FLAG_ERROR:6
FLAG_RROR:7
FLAG:0
FLAG:1
FLAG:2
FLAG:3
FLAG:4
FLAG:5
FLAG:6
FLAG:7
CHAPTER 4 SOFTWARE UART
;
CALL
_INITIAL
; Processing for initialization
;Setting interrupt level
MOV
ILR1,#B'11111100
MOV
ILR3,#B'11110011
; External interrupt: LEVEL = 0
; PWM timer: LEVEL = 0
;
;Initialization of software UART
MOV
A,#l
; Data = 8 bits, stop bit = 1, no parity
CALL
_SUART_INITIAL
;
SETI
;********************************
;*
Main routine
*
;********************************
MAIN:
CALL
_SUART_RCVCHK
CMP
A,#l
BZ
MAIN
;
CALL
_SUART_RECEIVE
;
CALL
_SUART_TRANS
JMP
MAIN
PROG
ENDS
;
;********************************
;* Processing for initialization*
;********************************
CSEG
PUBLIC _INITIAL
_INITIAL:
CLRI
;
MOV
STBC,#B'00010000
MOV
SYCC,#B'10000111
; Receiving check
; Is the data received?
; No
; Obtainment of the received data
; Transmitting the start processing
; Disable the interrupt
; Set the system operation clock (4/FCH =
0.95µS)
;
MOV
MOV
PDRI,#B'llllllll
DDRI,#B'00000000
;
MOVW
A,#H'0080
; Clear RAM
_INITIAL_10:
VW
A,#H'0000
XCHW
A,T
MOVW
@A,T
INCW
A
INCW
A
MOVW
A,#H'00FF
XCHW
A,T
CMPW
A
BNC
_INITIAL_010
;
RET
ENDS
;
;*********************************************
;* Name _SUART_INITIAL
*
;* Function Initialization of software UART *
;* Input parameter A: Initialization data
*
;* Output parameter None
*
;* Register in use A
*
;*********************************************
SUART
CSEG
PUBLIC _SUART_INITIAL
SUART INITIAL:
PUSHW
A
; Save the A register (store set data)
MOVW
MOVW
MOV
MOVW
MOVW
A,#0
TRNBUFF,A
TRNDTBUFF,A
RCVBUFF,A
RCVDTBUFF,A
; Clear the transmitting/receiving buffer
MOV
FLAG,A
; Clear the flag area
;
67
CHAPTER 4 SOFTWARE UART
;
MOV
MOV
PDR1,#11111111B
DDR1,#00000010B
; Initialize the port 1
; Transmitting output signal "H"
POPW
MOV
A
UMODE,A
; Extract and store the data
;
;
; Sets bit length
MOVW
A,#9
BBC
F_DTL,SU_INIT_010
INCW
A
SU_INIT 0l0:
;
; Sets parity
BBS
F_PRTY0,SU_INIT_020
BBC
F_PRTY1,SU_INIL_030
SU_INIT 020:
INCW
A
SU_INIT 030:
;
; Sets stop bit
BBC
F_STOP,SU_INIT_040
INCW
A
SU_INIT 040:
MOV
BITCT,A
;
; Sets external interrupt
CLRB
SIV0
CLRB
IF10
SETB
IE10
;
; Sets PWM timer
MOV
CNTRI,#B'00000000
;
SETI
;
RET
SUART
ENDS
;***************************************
;* Name _SUART_TRANS
*
;* Function
Transfer data set
*
;* Input parameter A: Transfer data
*
;* Output parameter None
*
;* Registers in use A, R0, R1
*
;***************************************
SUART
CSEG
PUBLIC
_SUARL_TRANS
_SUART_TRANS:
MOV
TRNDTBUFF,A
;
; Create transmission data
MOV
A,#H'FF
BBS
F_PRTY0,SU_TRN_010
BBC
F_PRTY1,SU_TRN_050
SU_TRN_010:
;
; Create parity
MOV
RO,#8
MOV
Rl,#0
MOV
A,TRNDTBUFF
SU_TRN_020:
RORC
A
BNC
SU_TRN_030
INC
Rl
SU_TRN_030:
DEC
RO
BNZ
SU_TRN_020
BBC
F_PRTY1,SU_TRN_040
INC
Rl
SU_TRN_040:
MOV
A,Rl
OR
A,#H'FE
;
68
; Is the data length 8 bits? → No
; Is the parity given?
; No
; 2 stop bits?
; Start the interrupt at the falling edge
; Clear the external interrupt request flag
; Enable the external interrupt
; Set the PWM timer stop
; Enable the interrupt
; Store the data
; Initialize the A register
; Is the parity given?
; No
; For the bit count
; For the parity data
; Create the parity
; Odd parity?
CHAPTER 4 SOFTWARE UART
SU_TRN_050:
SWAP
MOV
A,TRNDTBUFF
;
; Add start bit
CLRC
ROLC
A
BBC
F_DTL,SU_RN_060
; Is the data length 7 bits? → Yes
;
SWAP
ROLC
A
SWAP
;
; Wait for transmission completed
SU_TRN_060:
BBS
F_MDTRN,SU_TRN_060
; Wait for the transmission to be completed
;
MOVW
TRNBUFF,A
; Store the data
;
CLRB
F_TRNTIMING
; Clear the transmission counter
;
MOV
A,BITCT
; Initialize the bit counter
INCW
A
MOV
TRNBITCT,A
;
CLRB
IE10
; Disable the external interrupt
CLRB
IF10
; Clear the external interrupt request flag
;
SETB
F.IMDTRN
; Set the transmitting mode
;
; Waits for receiving to be completed
SU_TRN_070:
BBS
F_MDRCV, SU_TRN_070
; Waits for the reception to be completed
;
MOV
COMP1,#217
; Set the timer value
MOV
CNTR1,#B'00001001
; Start the PWM timer
;
RET
SUART
ENDS
;*********************************
;* Name
_SUART_RCVCHK
*
;* Function
Receiving check *
;* Input parameter
None
*
;* Output parameter A register *
;*
B'00000000: None
*
;*
B'00000001: Normal receive *
;*
B'00000010: Overrun error *
;*
B'00000100: Framing error *
;*
B'00001000: Parity error
*
;*
The above error flags may
*
;*
be overlapped.
*
;* Registers in use A, R0, R1
*
;*********************************
SUART
CSEG
PUBLIC _SUART_RCVCHK
_SUART_RCVCHK:
BBS
F_CNVRQ, SU_RCVCHK_010
; Is conversion requested?
JMP
SU_RCVCHK_130
SU_RCVCHK_010:
CLRB
F_CNVRQ
; Clear the conversion request flag.
;
; Converts received data
MOVW
A,RCVDTBUFF
;
; Checks for framing error
ROLC
A
SWAP
ROLC
A
SWAP
;
CLRB
F_ERFR
BC
SU_CVCHK_020
SETB
F_RFR
; Framing error
SU_RCVCHK_020:
69
CHAPTER 4 SOFTWARE UART
;
; Check parity
BBS
F_PRTY0,SU_RCVCHK_030
; Is the parity given?
BBC
F_PRTY1,SU_RCVCHK_040
; NO
SU_RCVCH_030:
ROLC
A
SWAP
ROLC
A
SWAP
CLRB
F_PARITY
; Store the parity bit
BNC
SU_RCVCHK_040
SETB
F_PARITY
;
SU_RCVCHK_040:
SWAP
BBS
F_DTL,SU_RCVCHK_050
; 7-bit data? No
CLRC
RORC
A
SU_RCVCHK.050:
MOV
RCVDTBUFF,A
; Store the data
;
BBS
F_PRTY0,SU_RCVCHK_060
; Is the parity given?
BBC
F_PRTY1,SU_RCVCHK_120
; NO
SU_RCVCHK_060:
;
; Create parity
MOV
R0,#8
; Initialize the bit counter
MOV
Rl,#0
; Initialize the parity data
MOV
A,RCVDTBUFF
; Create the parity
SU_FCVCHK_070:
RORC
A
BNC
SU_RCVCHK_080
INC
Rl
SU_RCVCHK_080:
DEC
R0
BNZ
SU_RCVCHK_070
BBC
F_PARITY,SU_RCVCHK_090
; Is the parity bit set to "1"?
INC
Rl
SU_RCVCHK_090:
MOV
A,Rl
RORC
A
BBS
F_PRTY1,SU_RCVCHK_100
; Even parity?
BC
S@RCVCHK-110
; Error if carry is "1"
JMP
SU_RCVCHK_120
SU_CVCHK_100:
BC
SU_CVCHK_120
; Error if carry is "0"
SU_RCVCHK_110:
SETB
F_ERPRTY
; Parity error
SU_RCVCHK_120:
;
CLRB
F_RCVDTRDY
; Clear the data normal receiving flag
MOV
A,FLAG_ERROR
; Check the error status
BNZ
SU_CVCHK_130
; Branch if no error
SETB
F_RCVDTRDY
; Normal
SU_RCVCHK_130:
MOVW
A,#0
MOV
A,FLAG@ERROR
; Return the error status
RET
SUART
ENDS
;******************************************
;* Name _SUART_RECEIVE
*
;* Function Obtainment of receiving data *
;* Input parameter None
*
;* Output parameter A: receiving data
*
;* Register in use A
*
;******************************************
SUART CSEG
PUBLIC
_SUART_RECEIVE
_SUART_RECEIVE:
CLRB
F_RCVDT
;
MOV
FLAG_ERROR,#0
; Clear the error flag
;
MOV
A,RCVDTBUFF
; Received data
70
CHAPTER 4 SOFTWARE UART
;
RET
SUART
ENDS
;****************************************************
;* Name _SUART_INTERRUPT
*
;* Function
External interrupt processing to
*
;*
start the reception
*
;* Usage
Used within SUART software
*
;* Input parameter
*
;* Output parameter
*
;* Register in use
The contents is not destroyed.*
;****************************************************
SUART
CSEG
PUBLIC -SUART_INTERRUPT
_SUART_INTERRUPT:
MOV
COMP1,#217
; Set the timer value
MOV
CNTR1,#B'00001001
; Start the PWM timer
;
CLRB
IF10
; Clear the external interrupt request flag
CLRB
IE10
; Disable the external interrupt
;
PUSHW
A
; Save the registers
XCHW
A,T
PUSHW
A
;
MOVW
A,#O
MOVW
RCVBUFF,A
; Clear the receiving buffer
;
CLRB
F_RCVTIMING
; Clear the receiving counter
;
MOV
A,BITCT
BBC
F_STOP,SU_INT_010
; 2 stop bits?
DECW
A
SU_INT_010:
MOV
RCVBITCT,A
; Initialize the bit counter
;
SETB
F_MDRCV
; Set the mode to reception
;
POPW
A
; Return the A/T register
XCHW
A,T
POPW
A
;
RETI
SUART ENDS
;*****************************************************
;* Name _SUART_TIMER
*
;* Function
Timer interrupt processing
*
;* Usage
Used within SUART software
*
;* Input parameter
*
;* Output parameter
*
;* Register in use
The contents is not destroyed.*
;*****************************************************
SUART
CSEG
PUBLIC SUARTTIMER
_SUART_TIMER:
PUSHW
A
; Save the A/T register
XCHW
A,T
PUSHW
A
;
CLRB
TIR
; Clear the interrupt factor flag
;
BBC
F_MDRCV,SU_TM_060
; Is it the receiving mode?
; Receiving processing
BBC
F_RCVTIMING,SU_TM_010
CLRB
F_RCVTIMING
JMP
SU_TM_050
SU_TM_010:
SETB
F_RCVTIMING
;
CLRC
BBC
PDR1:0_SU_TM20
; Does the receiving timing coincide with?
; NO
; Enter the data
71
CHAPTER 4 SOFTWARE UART
SETC
SU_TM_020:
MOVW
A,RCVBUFF
SWAP
RORC
A
;
SWAP
RORC
A
MOVW
RCVBUFF,A
;
MOV
A,RCVBITCT
CLRC
SUBC
A,#l
MOV
RCVBITCT,A
BNZ
SU_TM_050
;
CLRB
F_MDRCV
;
; Overrun error check
CLRB
F_EROVR
BBC
F_RCVDT,SU_030
SETB
F_EROVR
;
CLRB
F_RCVDTRDY
SU_TM_030:
SETB
F_RCVDT
SETB
F_CNVRQ
MOVW
A,RCVBUFF
MOVW
RCVDTBUFF,A
SU_TM_040:
BBS
F_MDTRN_SU_TK_050
;
MOV
CNTR1,#B'00000000
;
CLRB
IF10
SETB
IE10
SU_TM_050:
JMP
SU_TM_RET
;
SU_TM_060:
; Transmission processing
;
BBC
F_TRNTIMING,SU_TM_070
CLRB
F_TRNTIMING
JMP
SU_TM_RET
SU_TM_070:
SETB
F_TRNTIMING
;
MOVW
A,TRNBUFF
CLRC
SWAP
RORC
A
SWAP
RORC
A
MOVW
TRNBUFF,A
BNC
SU_TM_080
;
SETB
PDR1:1
JMP
SU_TM_090
SU_TM_080:
CLRB
PDR1:1
SU_TM_090:
MOV
A,TRNBITCT
CLRC
SUBC
A,#l
MOV
TRNBITCT,A
BNZ
SU_TM_RET
;
; Completes transmission
CLRB
F_MDTRN
;
MOV
CNTRI,#B'00000000
;
CLRB
IF10
SETB
IE10
72
; Store the data
; Update the bit counter
; Is the reception completed?
→
No
; Release the receiving mode
; Was the data read previously?
; Set the overrun error flag in advance
;
; Set the receiving data flag
; Set the conversion request flag
; The receiving buffer → The receiving data
buffer
; Wait for transmission?
; Stop the timer operation
; Clear the external interrupt request flag
; Enable the external interrupt
; Transmitting timing?
; No
; Start the transmission
; What bit is to be output this time?
; Return the updated data
; "L"
; Output "H"
; Output "L"
; Update the bit counter
; Is the transmission completed?
→
No
; Release the transmitting mode
; Stop the timer operation
; Clear the external interrupt request flag
; Enable the external interrupt
CHAPTER 4 SOFTWARE UART
SU_TM_RET:
POPW
A
XCHW
A,T
POPW
A
RETI
;
SUART
ENDS
;********************************
;*
Vector address
*
;********************************
VECTOR CSEG
ABS
ORG
0FFE8H
DW
_SUART_TIMER
ORG
0FFFAH
DW
_SUART_INTERRUPT
DB
H'00
DB
H'0l
DW
RESET
VECTOR ENDS
END
; Return the A/T register
; IRQ9 (8BIT PWM TIMER)
;
;
;
;
IRQ0 (external interrupt No.1)
Vacancy
Mode data (permit the external access)
Reset vector
73
Memo
74
CHAPTER 5
E2PROM INTERFACE
This chapter describes a sample program for exchanging data with the E2PROM.
The F2MC-8L series has a serial I/O capable of serial 8-bit data transfer via clock
synchronization method.
In data transfer, the transfer directions (LSB first/MSB first) and shift clocks (4 types)
can be selected.
This function enables transferring data with other ICs at high speed.
5.1 Specifications of the E2PROM Interface Sample Program
5.2 Skeletonized Flowchart for E2PROM Interface
5.3 Resource Registers and RAM for E2PROM Interface
5.4 Register Initialization for E2PROM Interface
5.5 RAM Initialization for E2PROM Interface
5.6 Detailed Flowchart for E2PROM Interface
5.7 Sample Program for E2PROM Interface
75
CHAPTER 5 E2PROM INTERFACE
5.1
Specifications of the E2PROM Interface Sample Program
The E2PROM interface sample program can transmit and receive the data to and from
E2PROM (Xicore, X25020) using a clock-synchronous, 8-bit serial I/O resource.
■ Specifications of the E2PROM Interface Sample Program
The specifications of the E2PROM interface sample program for the F2MC-8L family assume the
following conditions:
❍ Applicable series: MB89160/160A
•
Main clock ............ 4.194 MHz
•
Subclock............... 32.768 kHz
❍ E2PROM in use : Xicore, X25020
•
Clock rate of 1 MHz
•
256 X 8 bit configuration
•
8-bit OP code/E2PROM address is used.
❍ Access
MSB is to be accessed first according to the E2PROM (Xicore, X25020) specifications.
❍ Specification ports
76
•
Input ........... P23/SI: Serial data input from E2PROM
•
Output......... P20/EC: CS of E2PROM (low active)
P24/SO: Serial data output to E2PROM
P25/SCK: Serial clock output
CHAPTER 5 E2PROM INTERFACE
■ Circuit diagram for the E2PROM interface
Figure 5.1 is a circuit diagram for the E2PROM interface.
VCC
MB89160/160A
VCC
VSS
X25020
P20/EC
SC
P25/SCK
SCK
P24/SO
SI
SO
P23/SI
VCC
VSS
WP
HOLD
RST
X0A X1A X0
32.768 kHz
X1
4.194 MHz
Figure 5.1 Circuit diagram for E2PROM interface
77
CHAPTER 5 E2PROM INTERFACE
5.2
Skeletonized Flowchart for E2PROM Interface
Figure 5.2 shows a skeletonized flowchart for the E2PROM interface.
■ Skeletonized flowchart for E2PROM interface
Main routine
Processing for supervising
E2PROM access
Key entry routine
No
Is
a
request
for
E2PROM access made?
No
Is E2PROM access
processing completed?
Yes
Access processing by commands
Yes
Processing after completion
of E2PROM access
Set the E2PROM access end flag
End of processing
Figure 5.2 Skeletonized flowchart for E2PROM interface
78
CHAPTER 5 E2PROM INTERFACE
5.3
Resource Registers and RAM for E2PROM Interface
The E2PROM interface uses an 8-bit serial I/O resource.
■ Resource registers used for the E2PROM interface
Table 5.3a lists the resource registers used for the E2PROM interface.
Table 5.3a Resource registers used for E2PROM interface
Address
Register
Register contents
04H
PDR2
Port 2 data register
05H
DDR2
Port 2 input/output direction register
07H
SYCC
System clock control register
1CH
SMR
Serial mode register
1DH
SDR
Serial data register
■ RAM allocations for E2PROM interface
Table 5.3b lists RAM allocations for the E2PROM interface
Table 5.3b RAM allocations for E2PROM interface
Address
Symbol
Function
80H
EROMADRS
Storage area of address indicating E2PROM access
81H
OPECODEDT
Storage area of command indicating E2PROM access
82H
83H
SETDATADRS
+1
Storage area of write data source address
84H
ACSCNTF
Counter of bytes indicating E2PROM access
85H
86H
87H
88H
89H
8AH
EROMACSBF
+1
+2
+3
+4
+5
Buffer for E2PROM access
8BH
8CH
DATSETADRS
+1
Storage area of destination address at which read data is to be set
8DH
STATS
Each type of flag area
79
CHAPTER 5 E2PROM INTERFACE
5.4
Register Initialization for E2PROM Interface
The E2PROM interface uses the following four types of registers.
This section summarizes the bit configuration for initializing each of the registers.
• Initialization for the input/output ports (PDR2 and DDR2)
• Initialization for the system clock control register (SYCC)
• Initialization for the serial mode register (SMR)
• Initialization for the serial data register (SDR)
■ Register initialization for E2PROM interface
❍ Initializing the input/output port (PDR2, DDR2)
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
PDR2
*
*
*
*
P20: Outputs 'H' to CS of E2PROM
P23/SI: SO of E2PROM (input)
P24/SO: Outputs 'H' to SI of E2PROM
P25/SCK: Outputs 'H' to SCK of E2PROM
7 6 5 4 3 2 1 0
0 0 1 1 0 0 0 1
DDR2
*
*
*
*
P20: Sets to an output port
P23/SI: Sets to an input port
P24/SO: Sets to an output port
P25/SCK: Sets to an output port
* Set to an input because of unused port.
❍ Initializing the system clock control register (SYCC)
SYCC
7 6 5 4 3 2 1 0
0 0 0 0 1 1 1 1
*
* *
* Unused bits are set to 0.
80
CS1, CS0: System operation clock 4/fch = 0.95µs
SCS: Sets the system clock to the main clock
WT1, WT0: Oscillation stabilization time 24/fch = 0 ms
CHAPTER 5 E2PROM INTERFACE
❍ Initializing the serial mode register (SMR)
SMR
7 6 5 4 3 2 1 0
0 0 1 1 0 0 1 0
SST: Inhibits the serial I/O transfer
BDS: Sets the serial data direction to "MSB first"
CKS1, CKS0: Serial clock 4/fch × 2
SOE: SO (serial data) output of P24 port
SCKE: SCK (serial clock) output of P25 port
SIOE: Disables the serial I/O interrupt
SIOF: Clears the serial I/O interrupt
❍ Initializing the serial data register (SDR)
SDR
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
Initializes the serial data register
81
CHAPTER 5 E2PROM INTERFACE
5.5
RAM Initialization for E2PROM Interface
The E2PROM interface uses the following seven types of areas of RAM.
This section summarizes the bit configuration for initializing each of the areas.
• Initialization for the E2PROM access indication address storage area
(EROMADRS)
• Initialization for the E2PROM access indication command storage area
(OPECODEDT)
• Initialization for the write data source address storage area (SETDAT ADRS)
• Initialization for the E2PROM access indication byte counter (ACSCNT)
• Initialization for the E2PROM access buffer (EROMACSBF)
• Initialization for the read data destination address storage area (DATSET)
• Initialization for each type of flag areas (STATS)
■ RAM initialization for E2PROM interface
❍ Initializing the E2PROM access indication address storage area (EROMADRS)
7 6 5 4 3 2 1 0
EROMADRS
Area in which E2PROM address is to be
written for E2PROM access
Initial value = 'H'00
❍ Initializing the E2PROM access indication command storage area (OPECODEDT)
7 6 5 4 3 2 1 0
EROMADRS
Area in which the command indicating
E2PROM access is to be stored for E2PROM
access
Initial value = 'H'00
H'01: The set code to protect
from writing block
H'02: Data write code
H'03: Data read code
H'04: Data write disable code
H'05: Status register read code
H'06: Write enable code
❍ Initializing the write data source address storage area (SETDAT ADRS)
SETDAT ADRS
+1
7 6 5 4 3 2 1 0
High order
Low order
Area in which the address for storing the
write data is to be set when data is written
into E2PROM
Initial value = 'H'00
❍ Initializing the E2PROM access indication byte counter (ACSCNT)
7 6 5 4 3 2 1 0
ACSCNT
82
Area for indicating the number of bytes of the
data to be read/written from/into E2PROM
Initial value = H'00
CHAPTER 5 E2PROM INTERFACE
❍ Initializing the E2PROM access buffer (EROMACSBF)
EROMACSBF
7 6 5 4 3 2 1 0
High order
+1
+2
+3
+4
+5
Storage area of output data for E2PROM
access
Store the OP code address data from the
higher order address
Initial value = 'H'00
Low order
❍ Initializing the read data destination address storage area (DATSET)
7 6 5 4 3 2 1 0
Storage area of the address in which the
data read from E2PROM is to be stored
Initial value = 'H'00
SETDAT ADRS
+1
❍ Initializing the each type of flag areas (STATS)
7 6 5 4 3 2 1 0
STATS 0 0 0 0 0 0 0 0
*
*
*
*
*
*
* Unused bits are set to 0.
ACSRSREQ: E2PROM access request flag
0: No request
ACSEND: E2PROM access process completion flag
0: Not completed
83
CHAPTER 5 E2PROM INTERFACE
5.6
Detailed Flowchart for E2PROM Interface
Figure 5.6 shows a detailed flowchart for the E2PROM interface.
See also Sections 5.6.1 to 5.6.4 for the detailed flowcharts for the following processes:
• Write permission/inhibition OP code output (See Section 5.6.1.)
• Status register read and block write protection (See Section 5.6.2.)
• Data read (See Section 5.6.3.)
• Data write (See Section 5.6.4.)
■ Detailed flowchart for E2PROM interface
RESET
Processing for supervising
E2PROM access
EROMCTL
Set the system control register
Set the stack pointer
Set the input/output port
Initialize the RAM area
Initialize the serial mode register
MAIN
EROMCTL
Processing for supervising
E2PROM access
No
Is the E2PROM access
processing
completed?
Yes
EPROM_PRC
Processing after completion
of E2PROM access
Is a request for
access made?
No
Yes
JMP with the access
processing code
=H’06
WREN_ACS
Write permission
=H’04
WRDI_ACS
Write inhibition
=H’05
RDSR_ACS
Read status register
=H’01
WRSR_ACS
Set the block write protection
=H’03
READ_ACS
Read data
=H’02
WRITE_ACS
Write data
Processing after completion of
E2PROM access
EPROM_PRC
RET1
External module
RET
Figure 5.6 Detailed flowchart for E2PROM interface
84
5.6 Detailed Flowchart for E2PROM Interface
5.6.1 Detailed Flowchart for E2PROM Interface
(Write Permission/Inhibition OP code Output)
Figure 5.6.1 shows a detailed flowchart for the write permission and write inhibition OP
code outputs of the E2PROM interface.
■ Detailed flowchart for E2PROM interface (write permission/inhibition OP code outputs)
Output of write permission OP code
Output of write inhibition OP code
WREN_ACS
Set the output data in the
serial data register
WRDI_ACS
Set the output data in the
serial data register
Output 'L' to CS
Output 'L' to CS
Start the serial
Start the serial
No
No
The serial completed?
Yes
Output 'H' to CS
Set the E2PROM access
process completion flag
EXIT
The serial completed?
Yes
Output 'H' to CS
Set the E2PROM access
process completion flag
EXIT
Figure 5.6.1 Detailed flowchart for E2PROM interface
(Write permission/inhibition OP code output)
85
5.6 Detailed Flowchart for E2PROM Interface
5.6.2 Detailed Flowchart for E2PROM Interface
(Status Register Read and Block Write Protection)
Figure 5.6.2 shows a detailed flowchart for the status register read and block write
protection of the E2PROM interface.
■ Detailed flowchart for E2PROM interface (status register read and block write protection)
Read the status register
Set the block write protection
RDSD_ACS
WRSRI_ACS
Set the output data in the
serial data register
Output 'L' to CS
Set the indication OP code in
output buffer
Set the write protection set
value in the output buffer
Start the serial
Set the output data in the
serial data register
No
The serial completed?
Output 'L' to CS
Yes
Start the serial
Start the serial
No
No
The serial completed?
The serial completed?
Yes
Yes
Output 'H' to CS
Set the output data in the
serial data register
Save the read data
Start the serial
2
Set the E PROM access
process completion flag
No
The serial completed?
EXIT
Yes
Output 'H' to CS
Set the E2PROM access
process completion flag
EXIT
Figure 5.6.2 Detailed flowchart for the E2PROM interface
(status register read and block write protection)
86
5.6 Detailed Flowchart for E2PROM Interface
5.6.3 Detailed Flowchart for E2PROM Interface (Data Read)
Figure 5.6.3 shows a detailed flowchart for the data read of the E2PROM interface.
■ Detailed flowchart for E2PROM interface (data read)
Data read
READ_ACS
1
Start the serial
Set the indication OP code in
the output buffer
No
2
Set the E PROM address in
the output buffer
The serial completed?
Yes
Set the output data in the
serial data register
Output 'L' to CS
Set the read data in the
storage destination address
Update and set the data
storage destination address
Start the serial
Update the data read byte counter
No
The serial completed?
No
The read completed?
Yes
Set the output data in the
serial data register
Start the serial
Yes
1
Output 'H' to CS
Set the E2PROM access
process completion flag
No
The serial completed?
EXIT
Yes
Set the read data pointer
1
Figure 5.6.3 Detailed flowchart for E2PROM interface (data read)
87
5.6 Detailed Flowchart for E2PROM Interface
5.6.4 Detailed Flowchart for E2PROM Interface (Data Write)
Figure 5.6.4 shows a detailed flowchart for the data write of the E2PROM interface.
■ Detailed flowchart for E2PROM interface (data write)
Data write
WRITE_ACS
Set the indication OP code in
the output buffer
1
Set the write data in the serial
data register
Start the serial
Set the E2PROM address in
the output buffer
No
Set the write data in the output buffer
Set the output data in the
serial data register
The serial completed?
Yes
Update and set the data
storage source address
Output 'L' to CS
Update the write byte counter
Start the serial
No
The write completed?
No
The serial completed?
Yes
Yes
Set the output data in the
serial data register
Output 'H' to CS
Set the E2PROM access
process completion flag
Start the serial
EXIT
No
The serial completed?
Yes
1
Figure 5.6.4 Detailed flowchart for E2PROM interface (data write)
88
1
Memo
89
CHAPTER 5 E2PROM INTERFACE
5.7
Sample Program for E2PROM Interface
This section provides a sample program for the E2PROM interface.
■ Sample program for E2PROM interface
NAME
EEPROM
;********************************************************
;*
EEPROM interface sample program
*
;********************************************************
$INCLUDE
R160.INC
;********************************
;*
RAM definition
*
;********************************
RAM
DIRSEG ABS
ORG
0080H
EROMADRS
RB
1
; Storage area of the EEPROM access indication
address
OPECODEDT
RB
1
; Storage area of the EEPROM access indication
command
SETDTADRS
RB
2
; Storage area of the write data source address
ACSCNT
RB
1
; EEPROM access indication byte counter
EROMACSBF
RB
6
; Buffer for EEPROM access
DATSETADRS
RB
2
; Storage area of address in which the read data
is set
STATS
RB
0
; Each type of the flag area
ACSREQ
RBIT 1
; EEPROM access request flag
ACSEND
RBIT 1
; EEPROM access process completion flag
RAM
ENDS
PROG
CSEG
EXTRN
EROM_PRC
;********************************
;*
Initialization
*
;********************************
RESET:
MOV
SYCC,#10000111B
; Set the highest speed mode
MOVW
SP,#0180H
; Set the stack pointer
MOVW
A,#0030H
; Set the PS
MOVW
PS,A
;
MOV
DDR2,#00110001B
; Set the input/output status of P20 to P27
MOV
PDR2,#11111111B
;
MOVW
A,#0000H
; Initialize the storage area of the EEPROM
access indication address
MOV
EROMADRS,A
; Initialize the storage area of the EEPROM
access indication command
MOV
OPECODEDT,A
; Initialize the storage area of the write data
source address
MOVW
SETDTADRS,A
; Initialize the EEPROM access indication byte
counter
MOV
ACSCNT,A
; Initialize the buffer for EEPROM access
MOVW
EROMACSBF,A
MOVW
EROMACSBF+2,A
MOVW
EROMACSBF+4,A
MOVW
DATSETADRS,A
; Initialize the storage area of address at
which the read data is to be set
MOV
STATS,A
; Initialize each type of the flag area
;
MOV
SDR,A
; Initialize the serial data register
MOV
SMR,#00110010B
; Initialize the serial mode register
;
SETI
; Enable the interrupt
;********************************
;*
Main routine
*
;********************************
MAIN:
CALL
EROMCTL
; EEPROM access supervisory processing
;
BBC
ACSEND,MAIN
; End of the EEPROM access process? No
;
CALL
EROM_PRC
; Processing after completing the EEPROM access
;
JMP
MAIN
90
CHAPTER 5 E2PROM INTERFACE
;****************************************
;* EEPROM access supervisory processing *
;****************************************
EROMCTL:
BBC
ACSREQ, EROM_EXT
; Is the EEPROM access requested? No
;
CLRB
ACSREQ
; Clear the EEPROM access request flag
;
MOVW
A,#000H
MOV
A,DPECODEDT
CLRC
ROLC
A
MOVW
A,#JMP_TBL
CLRC
ADDCW
A
MOVW
A,@A
JMP
@A
; Jump to the each process with the access
process code
;
EROM_EXT:
RET
;
;====== Setting the block write protection ======
;
WRSR_ACS:
MOV
A,OPECODEDT
; Set the write protection OP code in the output
buffer
MOV
EROMACSBF,A
MOV
EROMACSBF+l,#0CH
; Set the all area indication code in the output
buffer
;
MOVW
IX,#EROMACSBF
MOV
A,@IX
MOV
SDR,A
; Set the output data in the serial data
register
;
CLRB
PDR2:0
; CS <-- "LOW"
;
SETB
SST
; Start the serial
;
WRSR_020:
BBC
SIOF,WRSR_020
; End of the serial? No
;
CLRB
SIOF
; Clear the serial completion flag
;
INCW
IX
MOV
A,@IX
MOV
SDR,A
; Set the output data in the serial data
register
;
SETB
SST
; Start the serial
;
WRSR_040:
BBC
SIOF,WRSR_040
; End of the serial? No
;
CLRB
SIOF
; Clear the serial completion flag
SETB
PDR2:0
; CS<--0"HI"
;
SETB
ACSEND
; Set the EEPROM access process completion flag
;
JMP
EROM_EXT
;
;
;====== Data write process ======
;
WRITE_ACS:
MOV
A,OPECODEDT
; Set the write OP code in the output buffer
MOV
EROMACSBF,A
;
MOV
A,EROMADRS
; Set the EEPROM write address in the output
buffer
MOV
EROMACSBF+I,A
;
MOVW
A,SETDTADRS
; Set the write data source address
MOVW
IX,A
MOVW
EP,#EROMACSBF+2
;
MOV
A,ACSCNT
; Set the write data byte counter
MOV
R0,A
;
91
CHAPTER 5 E2PROM INTERFACE
WRITE_020:
MOV
MOV
INCW
INCW
;
DEC
BNZ
;
MOVW
MOV
MOV
A, @IX
@EP, A
IX
EP
R0
WRITE_020
IX,#EROMACSBF
A,@IX
SDR,A
; Set the write data in the output buffer
; Have the data been set completly?
No
; Set the output data in the serial data
register
;
CLRB
PDR2:0
; CS<--"LOW"
SST
; Start the serial
SIOF,WRITE_040
; End of the serial?
SIOF
; Clear the serial completion flag
;
SETB
;
WRITE_040:
BBC
;
CLRB
;
INCW
MOV
MOV
IX
A,@IX
SDR,A
No
; Set the output data in the serial data
register
;
SETB
SST
;
WRITE_060:
BBC
SIOF,WRITE_060
;
CLRB
SIOF
INCW
IX
MOV
A,ACSCNT
MOV
R0,A
;
;
Write data output process
;
WRITE_080:
MOV
A,@IX
MOV
SDR,A
;
SETB
SST
;
WRITE_100:
BBC
SIOF,WRITE_100
;
CLRB
SIOF
;
INCW
IX
DEC
R0
BNZ
WRITE_080
;
SETB
PDR2:0
;
SETB
ACSEND
;
JMP
EROM_EXT
;
;
;====== Data read process ======
;
READ_ACS:
MOV
A,OPECODEDT
MOV
EROMACSBF,A
;
MOV
A,EROMADRS
MOV
EROMACSBF+L,A
MOV
MOV
A,ACSCNT
R0,A
MOVW
MOV
IX,#EROMACSBF
A,@IX
; Start the serial
; End of the serial?
No
; Clear the serial completion flag
; Set the write data byte counter
; Set the write data in the serial data register
; Start the serial
; End of the serial?
No
; Clear the serial completion flag
; Update the write data byte counter
; End of writing? No
; CS<--"HI"
; Set the EEPROM access process completion flag
; Set the read OP code in the output buffer
; Set the EEPROM read address in the output
buffer
;
;
92
; Set the read data byte counter
CHAPTER 5 E2PROM INTERFACE
MOV
SDR, A
; Set the output data in the serial data
register
CLRB
PDR2:0
; CS<--"LOW"
SST
; Start the serial
;
;
SETB
;
READ_020:
BBC
;
CLRB
;
INCW
MOV
MOV
SIOF,
READ_020
SIOF
IX
A,@IX
SDR,A
; End of the serial?
No
; Clear the serial end flag
; Set the output data to the serial data
register
;
SETB
;
READ_040:
BBC
;
CLRB
;
MOVW
MOVW
SST
; Start the serial
SIOF,READ_040
; End of the serial?
SIDF
; Clear the serial completion flag
A,DATSETADRS
IX,A
;
;
Data read process
;
READ_080:
;
SETB
SST
;
READ_100:
BBC
SIOF,READ_100
;
CLRB
SIOF
;
MOV
A,SDR
No
; Set the address at which the read data is to
be set
; Start the serial
; End of the serial?
No
; Clear the serial completion flag
; Set the read data at the storage destination
address
MOV
@IX,A
INCW
DEC
BNZ
IX
R0
READ_080
; Update the data read byte counter
; The read completed? No
SETB
PDR2:0
; CS<--"HI"
SETB
ACSEND
; Set the EEPROM access process completion flag
;
;
;
;
JMP
EROM_EXT
;
;
;====== Write inhibition set process ======
;
WRDI_ACS:
MOV
A,OPECODEDT
; Set the write inhibition OP code in the serial
data register
MOV
SDR,A
;
CLRB
PDR2:0
; CS<--"LOW"
;
SETB
SST
; Start the serial
;
WRDI_020:
BBC
SIOF,WRDI_020
; End of the serial? No
;
CLRB
SIOF
; Clear the serial completion flag
;
SETB
PDR2:0
; CS<--"HI"
;
SETB
ACSEND
; Set the EEPROM access process completion flag
;
JMP
EROM_EXT
;
;====== Status register read process code: 05 ======
;
93
CHAPTER 5 E2PROM INTERFACE
RDSR_ACS:
MOV
MOV
;
CLRB
;
SETB
;
RDSR_020:
BBC
;
CLRB
;
MOV
;
;
;
SETB
;
RDSR_040:
BBC
;
CLRB
;
SETB
;
MOVW
MOVW
A,OPECODEDT
SDR,A
; Set OP code into the serial data register
PDR2:0
; CS<--"LOW"
SST
; Start the serial
SIDF,RDSR_020
; End of the serial?
SIOF
; Clear the serial completion flag
No
SDR,#0FF
SST
; Start the serial
SIOF,RDSR_040
; End of the serial?
SIOF
; Clear the serial completion flag
PDR2:0
; CS<--"HI"
A,DATSETADRS
IX,A
No
; Set the address at which the read data is to
be set
MOV
MOV
A,SDR
@IX,A
; Set the read data
SETB
ACSEND
; Set the EEPROM access process completion flag
;
;
JMP
EROM_EXT
;
;====== Write permission process ======
;
WREN_ACS:
MOV
A,OPECODEBT
MOV
SDR,A
CLRB
PDR2:0
; Set the write permission OP code in the serial
data register
;
; CS<--"LOW"
;
SETB
SST
;
WREN_020:
BBC
SIOF,WREN_020
;
CLRB
SIOF
;
SETB
PDR2:0
;
SETB
ACSEND
;
JMP
EROM_EXT
;
;
;////////// JAMP TABLE //////////
;
JMP_TBL:
DW
ERONC_EXT
DW
WRSR_ACS
DW
WRITE_ACS
DW
READ_ACS
DW
WRDI_ACS
DW
RDSR_ACS
DW
WREN_ACS
;
;
;PROG
ENDS
94
; Start the serial
; End of the serial?
No
; End of the serial?
No
; CS<--"HI"
; Set the EEPROM access process completion flag
;
;
;
;
;
;
;
(00)
(01)
(02)
(03)
(04)
(05)
(06)
CHAPTER 5 E2PROM INTERFACE
;********************************
;*
Vector address
*
;********************************
VECTOR CSEG
ABS
ORG
0FFFCH
DB
00H
DB
00H
DW
RESET
VECTOR ENDS
END
; Reset mode
; Reset vector
95
Memo
96
CHAPTER 6
REMOTE-CONTROL SIGNAL TRANSMITTING
This chapter describes a sample program for transmitting remote-control signals.
Some of F2MC-8L series include a remote-control frequency generation circuit.
In many cases, the basic remote-control 0/1 signal represents the L to H pulse width
ratio/period, and the carrier frequency is generally output for either L or H period of
this 0/1 signal.
The remote-control frequency generation circuit outputs the carrier frequencies.
6.1 Specifications of the Remote-Control Signal Transmitting Sample Program
6.2 Skeletonized Flowchart for Remote-Control Signal Transmitting
6.3 Resource Registers and RAM for Remote-Control Signal Transmitting
6.4 Register Initialization for Remote-Control Signal Transmitting
6.5 RAM Initialization for Remote-Control Signal Transmitting
6.6 Detailed Flowchart for Remote-Control Signal Transmitting
6.7 Sample Program for Remote-Control Signal Transmitting
97
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
6.1
Specifications of the Remote-Control Signal Transmitting
Sample Program
The remote-control signal transmitting sample program is used to output the remotecontrol signals on the data format illustrated in Figure 6.1b, with the remote-control
frequency generator circuit.
■ Conditions for the remote-control signal transmitting sample program
The specifications of the remote-control signal transmitting sample program for the F2MC-8L
family assume the following conditions:
❍ Applicable series: MB89160/160A
•
Main clock ............ 4.194 MHz
•
Subclock............... 32.768 KHz
■ Circuit diagram for the remote-control signal transmitting sample program
Figure 6.1a is a circuit diagram for the remote-control signal transmitting sample program.
VCC
MB89160/160A
VCC
P30/RC0/BUZ
VSS
RST
X0A X1A X0
32.768 kHz
X1
4.194 MHz
Figure 6.1a Circuit diagram for the remote-control signal transmitting sample program
98
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
•
Header
•
Header pulse
‚
ƒ
‚
7-bit data
5-bit custom code
‚
*1
*1
*2
ƒ
'0' pulse
'1' pulse
*1
*1
2.4 ms
0.6 ms
0.6 ms
0.6 ms
1.2 ms
4T*2
T*2
T*2
T*2
2T*2
Carrier frequency (40 kHz) is output during this time.
Basic time unit (T) = The common time among the each pulse (0.6 ms)
Figure 6.1b Data format of the remote-control signal transmitting sample program
99
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
6.2
Skeletonized Flowchart for Remote-Control Signal
Transmitting
Figure 6.2 shows a skeletonized flowchart for remote-control signal transmitting.
■ Skeletonized flowchart for remote-control signal transmitting
Timer interrupt
Main routine
Remote-control signal
transmitting
Transmit?
Output for T period
No
Yes
Set the data for next T period
Set the transmitting data and
start the interrupt
The transmission
completed?
Yes
Stop the interrupt
End of processing
Figure 6.2 Skeletonized flowchart for remote-control signal transmitting
100
No
Memo
101
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
6.3
Resource Registers and RAM for Remote-Control Signal
Transmitting
Remote-control signal transmitting uses the following resources to initialize the
registers and RAM:
• 16-bit timer (8-bit timer × 2)
• Remote-control frequency generation circuit
■ Resource registers used for remote-control signal transmitting
Table 6.3a lists the resource registers used for remote-control signal transmitting.
Table 6.3a Resource registers for remote-control signal transmitting
Address
Register
Register contents
07H
SYCC
System clock control register
0CH
PDR3
Port 3 data register
14H
RCR1
Remote control register 1
15H
RCR2
Remote control register 2
18H
T2CR
Timer 2 control register
19H
T1CR
Timer 1 control register
1AH
T2DR
Timer 2 data register
1BH
T1DR
Timer 1 data register
7CH
ILR1
Interrupt level set register 1
7DH
ILR2
Interrupt level set register 2
7EH
ILR3
Interrupt level set register 3
■ RAM allocations for remote-control signal transmitting
Table 6.3b lists RAM allocations for the remote-control signal transmitting; Table 6.3c lists the
contents of the flags at address 80H.
102
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
Table 6.3b RAM allocations for remote-control signal transmitting
Address
Symbol
80H
–
Function
Each type of flag area
81H
DATA7
Data
82H
CUSTOM5
Custom code
83H
T_OUT_B
The number of output data every T period
84H
85H
86H
87H
88H
T_OUT
The output data buffer every T period
89H
T_OUT_BP
T_OUT bit pointer
8AH
8BH
T_OUT_AP
+1
T_OUT address pointer
8CH
T_OUT_BC
The output data counter every T period
8DH
T_OUT_C
The minimum number of transmitting counter
8EH
INTVL_C
Interval time counter
8FH
T_OUT_BPI
T_OUT bit pointer initial value
90H
91H
T_OUT_API
+1
T_OUT address pointer initial value
+1
+2
+3
+4
The minimum number of transmissions: Once transmission starts, at least three consecutive
frame must be transmitted. (The 4th frame and later are
to be output when repeating.)
Interval time:
Interval from start of frame transmitting to next frame
transmitting
Interval time (45 ms)
Header
Data
Custom
Header
Data
1
Custom
Header
Data
2
Custom
Header
Data
Custom
3
Minimum number of transmissions (3 times)
Table 6.3c Contents of flags at remote-control signal transmitting address 80H
Bit
Symbol
Function
0
F_SD_RQ
Transmitting request flag
1: Transmitting request
1
F_STP_RQ
Transmitting stop request flag
1: Transmitting stop request
2
F_RP_RQ
Repeat request flag
1: Repeat request
3
F_OUT
Transmitting output flag (output status to remote control port)
103
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
6.4
Register Initialization for Remote-Control Signal
Transmitting
This section provides the following types of initializing the registers used for the
remote-control signal transmitting sample program:
• Initialization for the system clock control register (SYCC)
• Initialization for the input/output port (PDR3)
• Initialization for the remote-control control registers (RCR1 and RCR2)
• Initialization for the 8/16-bit timers (timer 1 and timer 2) (T1CR, T2CR, T2DR, and
T1DR)
• Initialization for the interrupt level set registers (ILR1, ILR2, and ILR3)
■ Register initialization for remote-control signal transmitting (SYCC)
❍ Initializing the system clock control register (SYCC)
7 6 5 4 3 2 1 0
0 0 0 0 0 1 1 1
SYCC
*
* *
CS1, CS0: System operation clock 4/fch = 0.95 µs
SCS: Sets the system clock to the main clock
WT1, WT0: Oscillation stabilization time 24/fch = 0 ms
* Unused bits are set to 0.
❍ Initializing the input/output port (PDR3)
PDR3
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0
*
* *
*
*
*
*
P30/RCO/BUZ: Outputs 'L'
* Unused bits are set to 1.
❍ Initializing the remote-control control register (RCR1, RCR2)
7 6 5 4 3 2 1 0
PDR1 0 0 0 1 1 0 1 0
HSC5-HSC0: Remote control frequency
'H' width = 12.5 µs
H'1A X 1/2 instruction (0.47µs)
RCK1, RCK0: Basic clock = 1/2 instruction
7 6 5 4 3 2 1 0
PDR2 0 0 1 1 0 1 0 0
*
* Unused bits are set to 0.
104
SCL5-SCL0: Setting frequency = 25µs (40 kHz)
H'34 x 1/2 instruction (0.47µs)
RCEN: Inhibits the remote control transmitting frequency
from output
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
❍ Initializing the 8/16-bit timer (timer 1, timer 2) (T1CR, T2CR, T3DR, 1DR)
T1CR
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 0
T1STR: Stops the timer operation
T1STP: Stops the count operation
T1CS1, T1CS0: Clock source = 2
instructions (0.95µs × 2)
T1OS1,T1OS0: Sets P22/T0 to general output
T1IE: Disables the interrupts
T1IF: Clears the interrupt request flag
T2CR
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 0
T2STR: Stops the timer operation
T2STP: Continues the timer operation
T2CS1, T2CS0: Clock resource = 16-bit mode
T2OS1, T2OS0: Fixed "0"
T2IE: Disables the interrupt
T2IF: Clears the interrupt request flag
T2DR
7 6 5 4 3 2 1 0
Higher data
T1DR
Lower data
Data register = H'13b
0.6 ms ÷ 2 instructions (0.95 µs) = H'13B
❍ Initializing the interrupt level set register (ILR1, ILR2, ILR3)
ILR1
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
ILR1
* * * * * * * *
7 6 5 4 3 2 1 0
1 1 1 1 0 1 1 1
*
ILR3
*
*
*
*
*
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
*
*
*
*
*
*
*
* Sets the other interrupt levels to ‘3’
L51, L50: Sets the 16-bit timer interrupt level to ‘1’
* Sets the other interrupt levels to ‘3’
*
105
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
6.5
RAM Initialization for Remote-Control Signal Transmitting
This section provides the following 12 types of initializing the RAM areas used for the
remote-control signal transmitting sample program:
• Initialization for each flag (80H)
• Initialization for data (DATA7)
• Initialization for custom code (CUSTOM5)
• Initialization for the number of output data every T period (T_OUT_B)
• Initialization for the output data buffer every T period (T_OUT)
• Initialization for the T_OUT bit pointer (T_OUT_BP)
• Initialization for the T_OUT address pointer (T_OUT_AP)
• Initialization for the counter of the number of output data every T period
• Initialization for the counter of the minimum number of transmissions
• Initialization for the interval time counter (INTVL_C)
• Initialization for the T_OUT bit pointer initial value (T_OUT_BPI)
• Initialization for the T_OUT address pointer initial value (T_OUT_API)
■ RAM initialization for remote-control signal transmitting
❍ Initializing each type of flag (80H)
80H
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 0
*
*
*
*
F_SD_RQ: No transmitting request
F_STP_RQ: No transmitting stop request
F_RP_RQ: No repeat request
F_OUT: Outputs 'L' to remote control port
❍ Initializing data (DATA7)
7 6 5 4 3 2 1 0
DATA7
Determined by key code
Initial value = H'00
❍ Initializing the custom code (CUSTOM5)
7 6 5 4 3 2 1 0
CUSTOM5
Fixed to H'01
❍ Initializing the number of output data every T period (T OUT B)
7 6 5 4 3 2 1 0
T OUT B
106
The number of bits expanded in TOUT
Initial value = H'00
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
❍ Initializing the output data buffer every T period (T_OUT)
7 6 5 4 3 2 1 0
Performs bit-expansion of header, data and custom codes as outputs every T period.
T_OUT
+1
+2
+3
+4
❍ Initializing the T_OUT bit pointer
7 6 5 4 3 2 1 0
T_OUT_BP
Points the bit address of the bits extracted from
T_OUT
Initial value = H'00
❍ Initializing the address pointer of T_OUT (T_OUT_AP)
T_OUT_AP
+1
7 6 5 4 3 2 1 0
Higher address
Lower address
Points the byte address of the bits extracted
from T_OUT
Initial value = 'H'00
❍ Initializing the counter of the number of the output data every T period (T_OUT_BC)
7 6 5 4 3 2 1 0
T_OUT_BC
Counts the number of output data every
T period
Initial value = H'00
❍ Initializing the counter of the minimum number of transmissions (T_OUT_C)
7 6 5 4 3 2 1 0
T_OUT_C
Counts the minimum number of transmissions
Initial value = H'00
❍ Initializing the interval time counter (INTVL_C)
7 6 5 4 3 2 1 0
INTVL_C
Measures the interval time (45 ms)
Initial value = H'00
❍ Initializing the T_OUT bit pointer initial value (T_OUT_BPI)
7 6 5 4 3 2 1 0
T_OUT_BPI
Initial value of the bit address of the bits extracted
from T_OUT
Initial value = H'00
❍ Initializing the T_OUT address pointer initial value (T_OUT_API)
7 6 5 4 3 2 1 0
Higher address
T_OUT_API
Lower address
+1
Initial value of the byte address of the bits extracted
from T_OUT
Initial value = 'H'00
107
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
6.6
Detailed Flowchart for Remote-Control Signal Transmitting
Figure 6.6 shows a detailed flowchart for remote-control signal transmitting.
See also Sections 6.6.1 and 6.6.2 for the detailed flowcharts for the following
processes:
• Transmitting data setting and interrupt start (See Section 6.6.1.)
• 16-bit timer interrupt (See Section 6.6.2.)
■ Detailed flowchart for remote-control signal transmitting
RESET
Initialization
Clear RAM
KEY_INIT
Key read initialization
*
TR_INIT
Transmitting initialization
MAIN
KEY_PRC
Key code creation/
transmitting request
No
*
Is a transmitting
request made?
Yes
TR_DATA_PRC
Set the transmitting data/
start interrupt
*: External program
Figure 6.6 Detailed flowchart for remote-control signal transmitting
108
6.6 Detailed Flowchart for Remote-Control Signal Transmitting
6.6.1 Detailed Flowchart for Remote-Control Signal Transmitting
(Transmitting data setting and interrupt start)
Figure 6.6.1 shows a detailed flowchart for the transmitting data setting and interrupt
start for the remote-control signal transmitting.
■ Detailed flowchart for remote-control signal transmitting (transmitting data setting and interrupt start)
Setting the transmitting data/starting the interrupt
TR_DAT_PRC
Yes
Invalid key code?
No
Generate the data from the key code
Yes
Repeat code?
No
Yes
Off code?
No
Expand the header, data
and custom codes to T_OUT
Request to stop the transmission
Request to repeat
Set and start the 16-bit timer
interrupt
RET
Figure 6.6.1 Detailed flowchart for remote-control signal transmitting
(transmitting data setting and interrupt start)
109
6.6 Detailed Flowchart for Remote-Control Signal Transmitting
6.6.2 Detailed Flowchart for Remote-Control Signal Transmitting
(16-bit timer interrupt)
Figure 6.6.2 shows a detailed flowchart for 16-bit timer interrupt for remote-control
signal transmitting.
■ Detailed flowchart for remote-control signal transmitting (16-bit timer interrupt)
16-bit timer interrupt (remote-control transmitting)
T1_INT
Save the A/T register
Port output according to
transmitting output flag
1 frame completed?
Yes
No
Set the data for next T period
in transmitting output flag
Count the number of the
output data remaining in the output
data buffer
Count the interval time
Yes
Interval time?
No
Count the minimum number
of transmissions
Yes
Is there residual
transmitting times?
No
Is there a request to Yes
stop the transmission?
No
Yes
Repeat request?
No
Respecify the 1-frame data
Inhibit the 16-bit timer interrupt
Return the A/T register
RET1
Figure 6.6.2 Detailed flowchart for remote-control signal transmitting (16-bit timer interrupt)
110
Memo
111
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
6.7
Sample Program for Remote-Control Signal Transmitting
This section provides a sample program for remote-control signal transmitting.
■ Sample program for remote-control signal transmitting
NAME
RCNSND
;******************************************************************
;*
Sample program for remote-control signal transmitting
*
;******************************************************************
&INCLUDE
R160.INC
;********************************
;*
RAM definition
*
;********************************
RAM
DIRSEG ABS
ORG
0080H
F_SD_RQ
RBIT
1
; Transmitting request flag
F_STP_RQ
RBIT
1
; Transmitting stop request flag
F_RP_RQ
RBIT
1
; Repeat request flag
F_OUT
RBIT
1
; Transmitting output flag
RBIT
1
RBIT
1
RBIT
1
RBIT
1
;
DATA7
RB
1
; Data
CUSTOM5
RB
1
; Custom code
T_OUT_B
RB
1
; Number of output data every T period
T_OUT
RB
5
; Output data buffer every T period
T_OUT_BP
RB
1
; T_OUT bit pointer
T_OUT_AP
RW
1
; T_OUT address pointer
T_OUT_BC
RB
1
; Counter of the number of output data every T
period
T_OUT_C
RB
1
; Counter of the minimum number of transmissions
INTVL_C
RB
1
; Interval time counter
T_OUT_BPI
RB
1
; Initial value of T_OUT bit pointer
T_OUT_API
RW
1
; Initial value of T_OUT address pointer
RB
0
;
KEY_INT_ADD
RW
1
SW_DATA_N
RW
1
SW_DATA_VO
RW
1
SW_DATA_VN
RW
1
KEY_CODE
RB
1
KEY_CODE_O
RB
1
F_READ
RBIT
1
RBIT
1
RBIT
1
RBIT
1
RBIT
1
RBIT
1
RBIT
1
RBIT
1
;
RAM
ENDS
SSEG
STACK_END
RB
H'30
STACK_TOP:
ENDS
;
KEY_POW
EQU
H'00
; POWER
KEY_1CH
EQU
H'0l
; 1CH
KEY_2CH
EQU
H'02
; 2CH
KEY_3CH
EQU
H'03
; 3CH
KEY_4CH
EQU
H'04
; 4CH
KEY_5CH
EQU
H'05
; 5CH
KEY_6CH
EQU
H'06
; 6CH
KEY_7CH
EQU
H'07
; 7CH
KEY_8CH
EQU
H'08
; 8CH
KEY_9CH
EQU
H'09
; 9CH
112
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
KEY_10CH
EQU
H'0A
; 10CH
KEY_11CH
EQU
H'0B
; 11CH
KEY_12CH
EQU
H'0C
; 12CH
KEY_MUTE
EQU
H'0D
; MUTE
KEY_CHP
EQU
H'0E
; CH+
KEY_CHM
EQU
H'0F
; CHKEY_VOLP
EQU
H'10
; VOL+
KEY_VOLM
EQU
H'll
; VOLKEY_REP
EQU
H'12
; REPEAT
KEY_OFF
EQU
H'13
; OFF
;
PROG
CSEG
PUBLIC
;
;********************************
;*
Initialization
*
;********************************
RESET:
MOVW
A,#STACK_TOP
MOVW
SP,A
; Set the stack pointer
;
MOV
PDR3,#B'11111110
; Output "L" from the remote-control port (P30)
;
MOVW
A,#H'0030
; Set PS
MOVW
PS,A
;
MOV
SYCC,#B'10000111
MOV
ILR1,#B'llllllll
; Set the interrupt levels
MOV
ILR2,#B'01110111
MOV
ILR3,#B'llllllll
;
MOVW
EP,#H'80
; Clear RAM
MOVW
A,#STACK_END
XCHW
A,T
RESET_010:
MOV
@EP,#H'00
INCW
EP
MOVW
A,EP
CMPW
A
BNZ
RESET_010
;
CALL
KEY_INIT
; Initializations related to keys
;
CALL
TR_INIT
; Initializations related to transmission
SETI
;
;-----------------------------------------------;********************************
;*
Main routine
*
;********************************
MAIN:
CALL
KEY_PRC
; Key read
; Transmitting requested?
BBC
F_SD_RQ,MAIN ; NO
; No
;
CLRB
F_SD_RQ
; Clear the transmitting request flag
;
CALL
TR_DAT_PRC
; Remote-control transmitting processing
JMP
MAIN
;-----------------------------------------------PROG
ENDS
;--TRANS
CSEG
PUBLIC
;
113
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
;e.g.) Power key [Data = H'15,Custom = H'01]
;+-------+ +---+ +-+ +---+ +-+ +---+ +-+ +-+ +---+ +-+ +-+ +-+ +-+
;|
| |
| | | |
| | | |
| | | | | |
| | | | | | | | |
;|
| |
| | | |
| | | |
| | | | | |
| | | | | | | | |
;|
+-+
+-+ +-+
+-+ +-+
+-+ +-+ +-+
+-+ +-+ +-+ +-+ |
;|
| 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
;+<----->+<--->+<->+<--->+<->+<--->+<->+<->+<--->+<->+<->+<->+<->|
;|
|bit |bit|bit |bit|bit |bit|bit|bit |bit|bit|bit|bit|
;|
| 0
| 1 | 2
| 3 | 4
| 5 | 6 | 0
| 1 | 2 | 3 | 4 |
;
|
|
|
;+<----->+<------------------------------->+<------------------->+
;| Guide |
Data code
|
Custom code
|
;
;**************************************************
;* Setting transmitting data/activating interrupt *
;**************************************************
TR DAT PRC:
MOVW
A,#H'0000
MOV
A,KEY_CODE
CMP
A,#H'14
; Invalid key code [A>=#H'14]?
BNC
TR_DAT_PRC_EXIT
; Yes: Exit
;
MOVW
A,#DATA_TABLE
; Generate the data from key code
CLRC
;
ADDCW
A
;
MOV
A,@A
;
MOV
DATA7,A
;
;
CMP
A,#H'FE
; Repeat code?
BNZ
TR_DAT_PRC_100
; No
;
SETB
F_RP_RQ
; Repeat request
JMP
TR_DAT_PRC_EXIT
; Exit
;
tr_dat_Prc_100:
CMP
A,#H'FF
; Off code?
BNZ
TR_DAT_PRC_200
; No
;
CLRB
F_RP_RQ
; Clear the repeat request
;
; Transmitting?
BBC
TLIE,TR_DAT_PRC_EXIT
; No: Exit
;
SETB
F_STE_RQ
; Transmission stop request
JMP
TR_DAT_PRC_EXIT
; Exit
TR_DAT_PRC_200:
;
;
;
;
Transmitting?
Yes: Exit
Expand the guide, data and custom to T_OUT
Guide
BBS
TIIE,TR_DAT_PRC_EXIT
MOV
MOVW
MOVW
MOV
MOV
T_OUT+4,#B'00001111
A,#T_OUT+4
T_OUT_API, A
T_OUT_BPl,#B'00001000
T_OUT_B,#H'04
CALL
D_DATA_SET
; Data 7-bit
CALL
C_DATA_SET
; Custom 5-bit
; Set the transmitting pointer and counter
MOVW
MOVW
A,T_OUT_API
T_OUT_AP,A
MOV
MOV
A,T_OUT_BPI
T_OUT_BP,A
MOV
MOV
A,T_OUT,B
T_OUT_BC,A
MOV
INTVL_C,#D'75
MOV
T_OUT_C,#D'03
;
;
;
;
;
;
114
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
MOV
MOV
MOVW
MOVW
MOV
T2CR,#B'00001100
TlCR,#B'00000000
A,#H'013B
T2DR,A
TlCR,#B'01000001
;
TR_DAT_PRC_EXIT:
RET
;******************************
;* 16-bit timer interrupt
*
;******************************
Tl_INT:
PUSHW
A
XCHW
A,t
PUSHW
A
PUSHW
IX
;
CLRB
T1IF
;
BBC
SETB
JMP
TRANS_010:
CLRB
;
TRANS_100:
CLRB
;
MOV
BNZ
JMP
;
TRANS_200:
CLRB
;
MOVW
MOVW
;
MOV
MOV
;
MOV
;
MOV
;;;
MOV
;
TRANS_300:
;
CLRC
SUBC
MOV
; Activate 16-bit timer interrupt
; Save the A/T registers
; Clear the interrupt factors
: Port output according to the transmitting
output flag
F_OUT,TRANS_010
RCEN
TRANS_1OO
RCEN
F_OUT
A,T_OUT_BC
TRANS_300
TRANS_400
; 1 frame completed?
; No
; Yes
F_RP_RQ
A,T_OUT_API
T_OUT_AP,A
; Respecify the 1-frame data
A,T_OUT_BPI
T_OUT_BP,A
INTVL_C,#D'75
A,T_OUT_B
T_OUT_BC,A
; Set the next T-period data in the output flag
A,#Ol
T_OUT_BC,A
; Count the number of the output data remaining
in the output data buffer
;
MOVW
MOVW
MOV
A,T_OUT_AP
IX,A
A,T_OUT_BP
; Set the next T-period data in the output flag
;
MOV
AND
BZ
SETB
TRANS_310:
XCH
CLRC
RORC
BNC
RORC
INCW
TRANS_320:
MOV
MOVW
MOVW
;
TRANS_400:
A,@IX
A
TRANS_310
F_OUT
A,T
A
TRANS_320
A
IX
T_OUT_BP,A
A,IX
T_OUT_AP,A
115
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
MOV
CLRC
SUBC
MOV
BNZ
A,INTVL_C
; Count the interval time
A,#01
INTVL_C,A
TRANS_EXIT
; Interval time?
; No
MOV
BZ
CLRC
SUBC
MOV
BNZ
A,T_OUT_C
TRANS_410
;
; Count the minimum number of transmissions
A,#0l
T_OUT_C,A
TRANS_200
; No residual number of transmissions?
; No
BBS
F_STP_RQ,TRANS_420
; Transmission stop request?
; Yes
BBS
F_RP_RQ,TRANS_200
; Repeat request?
; Yes
F_STP_RQ
T1IE
; Inhibit the 16-bit timer interrupt
;
TRANS_410:
;
;
TRANS_420:
CLRB
CLRB
;
TRANS,EXIT:
POPW
IX
; Return the A/T registers
POPW
A
XCHW
A,t
POPW
A
RETI
;******************************************
;* Initialization related to transmission *
;******************************************
TR_INIT:
MOVW
A,#H'013B
;
MOVW
T2DR,A
;
MOV
T2CR,#B'00001100
MOV
TlCR,#B'00000010
;
MOV
RCR1,#B'00011010
MOV
RCR2,#B'00110100
;
MOVW
A,#H'00
;
MOV
DATA7,A
MOV
CUSTOM5,#H'0l
MOV
%F_SD_RQ,A
MOV
T_OUT_B,A
;
MOVW
T_OUT,A
MOVW
T_OUT+2,A
MOV
T_OUT+4,A
;
MOV
T_OUT_BP,A
MOVW
T_OUT_AP,A
MOV
T_OUT_BC,A
MOV
T_OUT_C,A
MOV
INTV_C,A
MOV
T_OUT_BPI,A
MOVW
T_OUT_API,A
RET
;********************************
;*
Data set
*
;********************************
D_DATA_SET:
MOV
R0,#7
MOV
A,DATA7
; 7-bit data
JMP
DATA_SET
;
116
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
;********************************
;*
Custom set
*
;********************************
C_DATA_SET:
MOV
R0,#5
MOV
A,CUSTOM5
; Custom 5-bit
;
DATA_SET:
MOV
Rl,A
DATA_SET_100:
CLRC
CALL
T_OUT_ROL
;
MOV
A,Rl
RORC
A
; "1" ?
MOV
R1,A
BNC
DATA_SET_110
; No
SETC
CALL
T_OUT_ROL
DATA_SET_110:
SETC
CALL
T_OUT_ROL
DEC
R0
BNZ
DATA_SET_100
RET
;---------------------------T_OUT <--- CF
;---------------------------T_OUT_ROL:
MOV
A,T_OUT+4
ROLC
A
MOV
T+OUT+4,A
MOV
A,T_OUT+3
ROLC
A
MOV
T_OUT+3,A
MOV
A,T_OUT+2
ROLC
A
MOV
T_OUT+2,A
MOV
A,T_OUT+l
ROLC
A
MOV
T_OUT+l,A
MOV
A,T_OUT
ROLC
A
MOV
T_OUT,A
;
MOV
A,T_OUT_B
INCW
A
MOV
T_OUT_B,A
;
MOV
A,T_OUT_BPI
CLRC
ROLC
A
MOV
T_OUT_BPI,A
BNC
T_OUT_ROL_EXIT
ROLC
A
MOV
T_OUT_BPI,A
;
MOVW
A,T_OUT_API
DECW
A
MOVW
T_OUT_API,A
;
T_OUT_ROL_EXIT:
RET
;*********************************
;*
Transmitting data table *
;*********************************
DATA_TABLE:
;------- transmit data --------- ;key_code: Key's name
;
DB
H'15
;
H'00:
POWER
DB
H'00
;
H'0l:
1 ch
DB
H'0l
;
H'02:
2 ch
DB
H'02
;
H'03:
3 ch
117
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
DB
H'03
;
H'04
4 ch
DB
H'04
;
H'05
5 ch
DB
H'05
;
H'06
6 ch
DB
H'06
;
H'07
7 ch
DB
H'07
;
H'08
8 ch
DB
H'08
;
H'09
9 ch
DB
H'09
;
H'OA
10 ch
DB
H'OA
;
H'OB
11 ch
DB
H'OB
;
H'OC
12 ch
DB
H'14
;
H'OD
MUTE
DB
H'10
;
H'OE
CH+
DB
H'Il
;
H'OF
CHDB
H'12
;
H'10
VOL+
DB
H'13
;
H'll
VOLDB
H'FE
;
H'12
rEPeat
DB
H'FF
;
H'13
off
;--- for extend data
;
DB
H'00
;
H'14
comment
;
DB
H'00
;
H'15
comment
;
DB
H'00
;
H'16
comment
;
DB
H'00
;
H'17
comment
;
DB
H'00
;
H'18
comment
;
DB
H'00
;
H'19
comment
;
DB
H'00
;
H'lA
comment
;
DB
H'00
;
H'lB
comment
;
DB
H'00
;
H'IC
comment
;
DB
H'00
;
H'ID
comment
;
DB
H'00
;
H'lE
comment
;
DB
H'00
;
H'lF
comment
;
TRANS
ENDS
;
;
KEY
CSEG
PUBLIC
;********************************
;*
Creating the key code
*
;********************************
;-----------------------------------------------; Transmission by one key-on (SW1 to SW11),
; while OFF request by pushing multi-key (including SW12)
; or key-off.
; Request for repeat when the same key is
; consecutively pressed.
;-----------------------------------------------KEY_PRC:
BBC
F_READ,KEY_PRC_300
CLRB
F_READ
;
MOV
R0,#0
MOVW
EP, #TBL_SW_ON
MOVW
A,SW_DATA_VO
MOVW
A,SW_DATA_VN
CMPW
A
BNZ
KEY_PRC_100
; SW status is changed.
MOV
A, KEY_CODE
MOV
KEY_CODE_O,A
CMP
A,#KEY_OFF
; Key remains off (or multi-key remains pushed)?
BZ
KEY_PRC_EXIT
; Yes
;
MOV
KEY_CODE,#KEY_REP
; Repeat since the key is the same as that used
previously
JMF
KEY_PRC_400
;
KEY_PRC_100:
MOVW
A,@EP
; Create a temporary key code
XCHW
A,T
CMPW
A
BZ
KEY_PRC_200
INCW
EP
INCW
EP
INC
RO
CMP
RO,#H'0B
; Applicable?
BNZ
KEY_PRC_100
; No
; R0=H'OB [Pushing multi-key, or pushing SW12 or
OFF]
KEY_PRC_200:
118
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
MOV
MOV
A,KEY_CDDE
KEY_CODE_O,A
; Update the previous key code
MOVW
MOV
MOVW
CLRC
ADDCW
MOV
MOV
JMP
A,#H'0000
A,R0
A,#TBL_KEY
; Create a key code from a temporary key code
;
;
;
KEY_PRC_300:
MOV
CMP
BZ
;
KEY_PRC_400:
SETB
;
KEY_PRC_EXIT:
RET
;
TBL_SW_ON:
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
A
A,@A
KEY_CODE,A
KEY_PRC_400
A,KEY_CODE
A,#KEY_REP
KEY_PRC_EXIT
; Repeat?
; Yes
F_SD_RQ
B'1111111111111110
B'1111111111111101
B'1111111111111011
B'1111111111110111
B'1111111111101111
B'1111111111011111
B'1111111110111111
B'1111111101111111
B'1111111011111111
B'1111110111111111
B'Illll0llllllllll
;
;
;
;
;
;
;
;
;
;
;
0
1
2
3
4
5
6
7
8
9
A
;Temporary code :
:Swl
:SW2
:SW3
:SW4
:SW5
:SW6
:SW7
:SW8
:SW9
:Swl0
:Swll
;
;
;
;
;
;
;
;
;
;
;
;
0
1
2
3
4
5
6
7
8
9
A
A
;Temporary code
:SW1
:SW2
:SW3
:SW4
:SW5
:SW6
:SW7
:SW8
:SW9
:SWl0
:SWll
:Pushing multi-key or key-off
;
TBL_KEY:
DB
KEY_POW
DB
KEY_MUTE
DB
KEY_CHP
DB
KEY_CHM
DB
KEY_VOLP
DB
KEY_VOLM
DB
KEY_4CH
DB
KEY_6CH
DB
KEY_8CH
DB
KEY_10CH
DB
KEY_2CH
DB
KEY_OFF
;******************************
;* Time-base timer interrupt *
;******************************
KEY_INT:
PUSHW
A
XCHW
A,T
PUSHW
A
PUSHW
IX
;
CLRB
TBOF
;
MOV
A,PDRO
OR
A,#B'11111000
XOR
A,#H'FF
MOV
R7,A
;
MOVW
A,KEY_INT_ADD
JMP
@A
;
INT_KEY_100:
MOV
PDR2,#B'11111101
;
119
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
MOVW
MOVW
A,#INT_KEY_200
KEY_lNT_ADD,A
MOVW
JMP
A,#TBL_KEY_159
INT_KEY_410
;
;
INT_KEY_200:
MOV
;
MOVW
MOVW
;
MOVW
JMP
;
INT_KEY_300:
MOV
;
MOVW
MOVW
;
MOVW
JMP
;
INT_KEY_400:
MOV
;
MOVW
MOVW
;
MOVW
;
INT_KEY_410:
MOVW
XCH
MOV
CLRC
ROLC
ADDCW
MOVW
MOVW
ANDW
MOVW
;
MOVW
MOVW
CMPW
BNZ
;
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
;
SETB
;
INT_KEY_EXIT:
POPW
POPW
XCHW
POPW
RETI
;
TBL_KEY_159:
DW
DW
DW
DW
DW
DW
DW
120
PDR2,#B'11111011
A, #INT_KEY_300
KEY_INT_ADD,A
A,#TBL_KEY_2610
INT_KEY_410
PDR2,#B'11110111
A,#INT_KEY_400
KEY_INT_ADD,A
A,#TBL_KEY_3711
INT_KEY_410
PDR2,#B'11111110
A,#INT_KEY_100
KEY_INT_ADD,A
A,#TBL_KEY_4812
A,#H'0000
A,T
A,R7
A
A
A,@A
A,SW_DATA_N
A
SW_DATA_N,A
A,KEY_INT_ADD
A,#INT_KEY_100
A
INT_KEY_EXIT
A,SW_DATA_VN
SW_DATA_VO,A
A,SW_DATA_N
SW_DATA_VN_A
A,#H'FFF
SW_DATA_N,A
; SW DATA "ALL OFF"
F_READ
IX
A
A,T
A
B'llllllllllllllll
B'llllll1011111111
B'1111111111101111
B'1111111011101111
B'1111111111111110
B'1111111011111110
B'1111111111101110
;
;
;
;
;
;
;
000
00l:SW9
010:SW5
011:SW9,SW5
100:SW1
101:SW1,SW9
110:SW1,SW5
CHAPTER 6 REMOTE-CONTROL SIGNAL TRANSMITTING
DW
B'1111111011101110
TBL_KEY_2610:
DW
B'llllllllllllllll
DW
B'1111110111111111
DW
B'1111111111011111
DW
B'1111110111011111
DW
B'1111111111111101
DW
B'1111110111111101
DW
B'1111111111011101
DW
B'1111110111011101
TBL_KEY_3711:
DW
B'llllllllllllllll
DW
B'lllll0llllllllll
DW
B'1111111110111111
DW
B'lllll0lll0llllll
DW
B'1111111111111011
DW
B'1111101111111011
DW
B'1111111110111011
DW
B'1111101110111011
TBL_KEY_4812:
DW
B'llllllllllllllll
DW
B'1111011111111111
DW
B'1111111101111111
DW
B'1111011101111111
DW
B'1111111111110111
DW
B'1111011111110111
DW
B'1111111101110111
DW
B'1111011101110111
;********************************
;*Initialization related to keys*
;********************************
KEY_INIT:
MOV
DDR0,#B'00000000
MOV
DDR2,#B'llllllll
MOV
PDR2,#B'11111110
;
MOVW
A, #INT_KEY_100
MOVW
KEY_INT_ADD,A
;
MOV
KEY_CODE,#KEY_OFF
MOV
KEY_CODE_O,#KEY_OFF
;
MOVW
A,#H'FFFF
MOVW
SW_DATA_N,A
MOVW
SW_DATA_VO,A
MOVW
SW_DATA_VN,A
;
CLRB
E_READ
MOV
TBTC,#B'01000000
;
RET
;
KEY
ENDS
;
;********************************
;*
Vector address
*
;********************************
VECTOR CSEG
ABS
ORG
0FFECH
DW
KEY_INT
VECTOR
; lll:SW1,SW5,SW9
;
;
;
;
;
;
;
;
000
001
010
011
100
101
110
111
;
;
;
;
;
;
;
;
000
001
010
011
100
101
110
111
;
;
;
;
;
;
;
;
000
001
010
011
100
101
110
111
; KEY_INT processing address
; KEY_CODE
; KEY_CODE(OLD)
; SW DATA 'ALL OFF'
; 1.95 ms [4.195 MHz]
; Time-base timer interrupt
ORG
DW
0FFF0H
T1_INT
; 16-bit timer interrupt
ORG
DB
DW
OFFFDH
00H
RESET
; Mode data
; Reset vector
ENDS
END
121
Memo
122
CHAPTER 7
REMOTE-CONTROL SIGNAL RECEIVING
This chapter describes a sample program for receiving remote-control signals.
The F2MC-8L series includes a timer interrupt, and external interrupt with edge
detection function. When these interrupts are used for measuring the pulse width and
the number of pulses, the remote-control signals can be received.
7.1 Specifications of the Remote-Control Signal Receiving Sample Program
7.2 Skeletonized Flowchart for Remote-Control Signal Receiving
7.3 Resource Registers and RAM for Remote-Control Signal Receiving
7.4 Register Initialization for Remote-Control Signal Receiving
7.5 RAM Initialization for Remote-Control Signal Receiving
7.6 Detailed Flowchart for Remote-Control Signal Receiving
7.7 Sample Program for Remote-Control Signal Receiving
123
CHAPTER 7 REMOTE-CONTROL SIGNAL RECEIVING
7.1
Specifications of the Remote-Control Signal Receiving
Sample Program
The remote-control signal receiving sample program is used to receive the remotecontrol signals on the data format illustrated in Figure 7.1b.
■ Specifications of the remote-control signal receiving sample program
The specifications of the remote-control signal receiving sample program for the F2MC-8L family
assume the following conditions:
❍ Applicable series: MB89160/160A
•
Main clock ............ 4.194 MHz
•
Subclock............... 32.768 KHz
■ Circuit diagram for the remote-control signal receiving sample program
Figure 7.1a shows a circuit diagram for the remote-control signal receiving sample program.
VCC
MB89160/160A
VCC
P10/INT10
Infrared remote-control sensor
VSS
RST
X0A X1A X0
32.768 kHz
X1
4.194 MHz
Figure 7.1a Circuit diagram for the remote-control signal receiving sample program
124
CHAPTER 7 REMOTE-CONTROL SIGNAL RECEIVING
❍ Data format of the remote-control signal receiving sample program
The sample program starts the timer by the both edges of an external interrupt signal, to
measure the pulse width according to the data format illustrated in Figure 7.1b .
bit 0
•
bit 0
‚ ƒ ‚
bit 10 bit 11
„
…
12-bit data length
* Distinguishing between '0' and '1'
Guide pulse
2.4 ms
'0'
'1'
‚ Data off
0.6 ms
ƒ Data on '0'
0.6 ms
0.6 ms 0.6 ms
0.6 ms
1.2 ms
„ Data on '1'
1.2 ms
… Frame frequency
45.0 ms
‚
ƒ
‚
„
* Each time sector has an allowable error.
•
Figure 7.1b Data format of the remote-control signal receiving sample program
125
CHAPTER 7 REMOTE-CONTROL SIGNAL RECEIVING
7.2
Skeletonized Flowchart for Remote-Control Signal Receiving
Figure 7.2 shows a skeletonized flowchart for remote-control signal receiving.
■ Skeletonized flowchart for remote-control signal receiving
Time-base timer interrupt
Determine the remote-control input
Main routine
Frame cycle timer
Processing after receiving
the remote-control signal
External interrupt
Remote-control signal input
No
Rising edge?
Yes
Save the 'L' pulse width
Restart the timer
'L' pulse width
= Guide pulse?
No
Operating?
Yes
Count the frame cycle timer
Frame cycle timer
No
Time-out?
Yes
No
Input bit = 12?
Save the 'H' pulse width
Yes
End of processing
Set the remote-control
input determination flag
End of processing
No
Yes
Clear the input bit counter
The input status ← Normal
End of processing
No
'H' pulse width OK?
Yes
No
Start the frame frequency timer
End of processing
The input status = Normal?
Yes
No
'L' pulse width OK?
Yes
Enter the 1-bit data
Increment the input bit counter
The input bit counter ≤ 12?
Yes
End of processing
No
Stop the frame frequency timer
The input status ← Abnormal
End of processing
Figure 7.2 Skeletonized flowchart for remote-control signal receiving
126
Memo
127
CHAPTER 7 REMOTE-CONTROL SIGNAL RECEIVING
7.3
Resource Registers and RAM for Remote-Control Signal
Receiving
Remote-control signal receiving uses the following three resources to set registers and
allocate RAM:
• External interrupt 1
• 8-bit timer 1
• Time-base timer
■ Resource registers used for remote-control signal receiving
Table 7.3a lists the resource registers used for remote-control signal receiving.
Table 7.3a Resource registers for remote-control signal receiving
Address
Register
Register contents
02H
PDR1
Port 1 data register
07H
SYCC
System clock control register
0AH
TBTC
Time-base timer control register
19H
T1CR
Timer 1 control register
1BH
T1DR
Timer 1 data register
30H
EIE2
External interrupt 1 control register
31H
EIF2
External interrupt 1 flag register
7CH
ILR1
Interrupt level set register 1
7DH
ILR2
Interrupt level set register 2
7EH
ILR3
Interrupt level set register 3
■ RAM allocations for remote-control signal receiving
Table 7.3b lists RAM allocations for remote-control signal receiving; Table 6.3c lists the flag
contents in the register at address 80H.
Table 7.3b RAM allocations for remote-control signal receiving
128
Address
Symbol
80H
–
Function
Each type of flag area
81H
HPLUSE
Remote-control 'H' width measurement value
82H
LPLUSE
Remote-control 'L' width measurement value
83H
84H
RMCDATA
+1
Remote-control input data
85H
BITCT
Remote-control input bit counter
86H
FRTMR
Remote-control frame frequency measurement timer
CHAPTER 7 REMOTE-CONTROL SIGNAL RECEIVING
Table 7.3c Flag contents in the register for remote-control signal receiving (80H)
Bit
Symbol
Function
0
F_OVFH
Remote-control 'H' width timer value overflow flag
1: Over
1
F_OVFL
Remote-control 'L' width timer value overflow flag
1: Over
2
F_RMCERR
Remote-control input status flag
1: Abnormal
3
F_RMCIN
Remote-control input determination flag
0: Normal
1: Determined
129
CHAPTER 7 REMOTE-CONTROL SIGNAL RECEIVING
7.4
Register Initialization for Remote-Control Signal Receiving
This section summarizes the following five types of initializing the resource registers
for remote-control signal receiving:
• Initialization for the system clock control register (SYCC)
• Initialization for the interrupt level set registers (ILR1, ILR2, and ILR3)
• Initialization for the time-base timer (TBTC)
• Initialization for the 8-bit timer 1 (T1CR and T1DR)
• Initialization for the external interrupt 1 control (EIE1) register
■ Register initialization for remote-control signal receiving
❍ Initialization for system clock control register (SYCC)
SYCC
7 6 5 4 3 2 1 0
0 0 0 0 1 1 1 1
*
* *
CS1, CS0: System operating clock 4/fch = 0.95 µs
SCS: Sets the system clock to the main clock
WT1, WT0: Oscillation stabilization time 24/fch = 0 ms
* Unused bits are set to 0.
❍ Initialization for interrupt level set register (ILR1, ILR2, ILR3)
ILR1
ILR2
7 6 5 4 3 2 1 0
1 1 1 1 1 1 0 0
* Sets the other interrupt levels to ‘3’
*
L01, L00: Sets the level of external interrupt 1 to ‘1’
*
*
*
*
7 6 5 4 3 2 1 0
1 0 1 1 1 1 1 1
*
ILR2
*
*
*
*
*
*
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
*
*
*
*
*
*
*
L71, L70: Sets the level of time-base timer interrupt to ‘2’
* Sets the other interrupt levels to ‘3’
*
❍ Initialization for time-base timer (TBTC)
TBTC
7 6 5 4 3 2 1 0
0 1 0 0 0 0 0 0
*
*
*
TBR: Clears the time-base timer
TBC1, TBC0: Interval time 213/fch = 1.95 ms
TBIE: Enables the interval interrupt
TBOF: Clears the interval timer overflow flag
* Unused bits are set to 0.
130
CHAPTER 7 REMOTE-CONTROL SIGNAL RECEIVING
❍ Initialization for the 8-bit timer 1 (T1CR, T1DR)
T1CR
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 0
T1STR: Stops the timer 1 operation
T1STP: Timer 1 continuous operation
T1CS1, T1CS0: Clock source = 32 instruction
(1/(fch/2)) × 2 × 32 = 30.5µs
T1OS1,T1OS0: Sets P20/T0 to general outputs
T1IE: Disables the interrupt
T1IF: Clears the interrupt request flag
T1DR
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
Data register = H'FF (D'255)
30.5µs × (255+1) = 7808µs (interval time)
❍ Initialization for the external interrupt 1 control register (EIE1)
EIE1
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1
*
*
*
*
*
*
IE10: Permits the INT10 operation
SIV0: No INT10 signal reversion
* Unused bits are set to 0.
131
CHAPTER 7 REMOTE-CONTROL SIGNAL RECEIVING
7.5
RAM Initialization for Remote-Control Signal Receiving
This section summarizes the following five types of initializing the areas of RAM which
are used for remote-control signal receiving.
• Initialization for each of flags (80H)
• Initialization for the remote-control pulse width measurement values (HPULSE
and LPULSE)
• Initialization for the remote-control input data (LPULSE)
• Initialization for the remote-control input bit counter (BITCT)
• Initialization for the remote-control frame frequency measurement timer
(FRTMR)
■ RAM initialization for remote-control signal receiving
❍ Initialization for each type of flag (80H)
7 6 5 4 3 2 1 0
– – – – 0 0 1 0
80H
*
*
*
*
F_OVFH: Clears the remote-control 'H' width timer
value overflow flag
F_OVFL: Clears the remote-control 'L' width timer
value overflow flag clear
* Unused bits
F_RMCERR: Clears the remote-control input status flag
F_RMCIN: Clears the remote-control input determination
flag
❍ Initialization for the remote-control pulse width measurement value (HPULSE, LPULSE)
7 6 5 4 3 2 1 0
HPULSE
7 6 5 4 3 2 1 0
LPULSE
Remote-control 'H' width measurement value
Initial value = H'00
Remote-control 'L' width measurement value
Initial value = H'00
❍ Initialization for the remote-control input data (LPULSE)
7 6 5 4 3 2 1 0
LPULSE
+1
Remote-control input data
Initial value = H'00
❍ Initialization for the remote-control input bit counter (BITCT)
7 6 5 4 3 2 1 0
Remote-control input bit
BTCT
Initial value = H'00
❍ Initialization for the remote-control frame frequency measurement timer (FRTMR)
7 6 5 4 3 2 1 0
Remote-control frame cycle measurement timer
FRTMR
Initial value = H'00
132
CHAPTER 7 REMOTE-CONTROL SIGNAL RECEIVING
7.6
Detailed Flowchart for Remote-Control Signal Receiving
Figure 7.6 shows a detailed flowchart for remote-control signal receiving.
See also Sections 7.6.1 and 7.6.2 for the detailed flowcharts for the following two
processes:
• External interrupt (See Section 7.6.1.)
• Time-base timer interrupt (See Section 7.6.2.)
■ Detailed flowchart for remote-control signal receiving
RESET
Initialization
Enable the interrupt
MAIN
RMC_PR
Processing after receiving
the remote-control signal
*
* : External program
Figure 7.6 Detailed flowchart for remote-control signal receiving
133
7.6 Detailed Flowchart for Remote-Control Signal Receiving
7.6.1 Detailed Flowchart for Remote-Control Signal Receiving
(External Interrupt)
Figure 7.6.1 shows a detailed flowchart for external interrupt of remote-control signal
receiving.
■ Detailed flowchart for remote-control signal receiving (external interrupt)
External interrupt
IRQ01INT
1
Save the registers
Rising edge?
Yes
INT10 Port level = 'H'?
Enter the 1-bit data
No
Increment the input bit counter
No
No
Yes
Yes
Save the 'L' pulse width
No
Yes
2
Save the 'H' pulse width
Restart the timer 1
Timer 1 overflow?
The input bit counter ≤ 12?
INT10 Port level = 'L'?
Restart the timer
Stop the frame cycle timer
No
No
Timer 1 overflow?
Clear the 'L' width overflow flag
Yes
Set the 'H' width overflow flag
Clear the 'H' width overflow flag
Yes
Set the 'L' width overflow flag
Set the falling detection
The input status ← Abnormal
Set the rising detection
No
'L' width Overflow flag = 0?
Yes
No
'L' pulse width = guide pulse?
Yes
No
'H' width Overflow flag = 0?
Clear the 'H' width overflow flag
Clear the input bit counter
Yes
The input status ← Normal
Start the frame cycle timer
No
'H' pulse width OK?
Yes
No
The input status = Normal?
Yes
'L' pulse width OK?
1
Yes
No
2
Return the registers
RET1
Figure 7.6.1 Detailed flowchart for remote-control signal receiving (external interrupt)
134
7.6 Detailed Flowchart for Remote-Control Signal Receiving
7.6.2 Detailed Flowchart for Remote-Control Signal Receiving
(Time-Base Timer Interrupt)
Figure 7.6.2 shows a detailed flowchart for time-base timer interrupt of remote-control
signal receiving.
■ Detailed flowchart for remote-control signal receiving (time-base timer interrupt)
Time-base timer interrupt
TBINT
Save the registers
Frame cycle timer
No
Operating?
Yes
Count the frame cycle timer
Frame cycle timer
No
Time-out?
Yes
No
The input bit = 12?
Yes
Set the remote-control
input determination flag
Return the registers
RESET
Figure 7.6.3 Detailed flowchart for remote-control signal receiving (time-base timer interrupt)
135
CHAPTER 7 REMOTE-CONTROL SIGNAL RECEIVING
7.7
Sample Program for Remote-Control Signal Receiving
This section provides a sample program for remote-control signal receiving.
■ Sample program for remote-control signal receiving
NAME
RCNRCV
;********************************************************
;*
Remote-control receiving sample program
*
;********************************************************
&INCLUDE
R160.INC
;********************************
;*
RAM definition
*
;********************************
RAM
DIRSEG ABS
ORG
0080H
F_OVFH
RBIT
1
; Remote-control "H" pulse width timer value
overflow flag
F_OVFL
RBIT
1
; Remote-control "L" pulse width timer value
overflow flag
F_RMCERR
RBIT
1
; Remote-control input status flag
F_RMCIN
RBIT
1
; Remote-control input determination flag
RBIT
1
RBIT
1
RBIT
1
RBIT
1
HPULSE
RB
1
; Remote-control "H" pulse width measurement
value
LPULSE
RB
1
; Remote-control "L" pulse width measurement
value
RMCDATA
RB
2
; Remote-control input data
BITCT
RB
1
; Remote-control input bit counter
FRTMR
RB
1
; Remote-control frame cycle measurement timer
RAM
ENDS
PROG
CSEG
EXTRN
RMC_PR
;********************************
;*
Initialization
*
;********************************
RESET:
MOV
SYCC,#10000111B
; Set the highest-speed mode
MOVW
SP,#0180H
; Set the stack pointer
MOVW
A,#0030H
; Set the PS
MOVW
PS,A
;
MOV
ILR1,#11111100B
; Set the interrupt levels
MOV
ILR2,#10111111B
MOV
ILR3,#11111111B
;
MOV
TBTC,#01000000B
; Set the time-base timer
MOV
T1CR,#00000100B
; Set the timer 1
MOV
TLDR,#0FFH
MOV
ElEl,#00000001B
; Set the external interrupt 1
;
CLRB
F_OVFH
; Clear the remote-control "H" pulse width timer
value overflow flag
CLRB
F_OVFL
; Clear the remote-control "L" pulse width timer
value overflow flag
CLRB
F_RMCERR
; Clear the remote-control input status flag
CLRB
F_RMCIN
; Clear the remote-control input determination
flag
MOV
HPULSE,#0
; Clear the remote-control "H" pulse width
measurement value
MOV
LPULSE,#0
; Clear the remote-control "L" pulse width
measurement value
MOVW
A,#0
; Clear the remote-control input data
MOVW
RMCDATA,A
MOV
BITCT,#0
; Clear the remote-control input bit counter
MOV
FRTMR,#0
; Clear the remote-control frame cycle
measurement timer
;
SETI
; Enable the interrupt
;********************************
;*
Main routine
*
;********************************
MAIN:
CALL
RMC_PR
; Processing after receiving the remote-control
signal
136
CHAPTER 7 REMOTE-CONTROL SIGNAL RECEIVING
;
JMP
MAIN
;*******************************
;*External interrupt processing*
;*******************************
IRQ01INT:
PUSHW
A
XCHW
A,T
PUSHW
A
PUSHW
IX
;
CLRB
IF10
;
BBC
SIV0,IRQ01_200
;
BBC
PDR1:0,IRQ01_RET
;
CLRB
T1STR
MOV
A,T1DR
MOV
LPULSE,A
SETB
T1STR
;
BBC
T1IF,IRQ01_0l0
;
CLRB
T1IF
SETB
F_OVFL
;
IRQ01_010:
CLRB
;
BBS
;
MOV
MOV
CMP
BC
;
MOV
MOV
CMP
BC
;
CLRB
MOV
CLRB
MOV
;
IRQ01 RET:
POPW
POPW
XCHW
POPW
;
RETI
;
IRQ01_200:
BBS
;
CLRB
MOV
MOV
SETB
;
BBC
;
CLRB
SETB
;
IRQ01_210:
SETB
;
JMP
;
IRQ01_300:
MOV
; Save the register
; Clear the interrupt flag
; The reverse bit = 1?
; Yes → rising edge detected
; Level = H?
; Stop the timer 1
; Save the "L" pulse width timer value
; Start the timer 1
; Timer 1 overflow?
; Clear the interrupt flag
; Set the remote-control "L" pulse width timer
value overflow flag
SIV0
; Clear the reverse bit
F_OVFL,IRQ01_300
; No "L" pulse width overflow?
A,LPULSE
A,#41H
A
IRQ01_400
; "L" pulse width >= #41h (2.00 ms)?
A,#5BH
A,LPULSE
A
IRQ01_300
; "L" pulse width =< #5bh (2.78 ms)?
F_OVFH
BITCT,#0H
F_RMCERR
FRTMR,#14H
IX
A
A,T
A
; Yes → the guide pulse
; Clear the remote-control "H" pulse width timer
value overflow flag
; Clear the remote-control input bit counter
; Clear the remote-control input status flag
; Start the remote-control frame cycle
measurement timer (40 ms)
; Return the registers
; Falling edge detection
PDRI:0, IRQ01_RET
T1STR
A,T1DR
HPULSE,A
T1STR
; Stop the timer 1
; Save the "H" pulse width timer value
T1IF,IRQ01_210
; Timer 1 overflow?
T1IF
F_OVFH
; Clear the interrupt flag
; Set the remote-control "H" pulse width timer
value overflow flag
SIV0
; Set the reverse bit
; Stop the timer 1
IRQ01_RET
FRTMR,#0
; Stop the remote-control frame cycle
measurement timer
137
CHAPTER 7 REMOTE-CONTROL SIGNAL RECEIVING
CLRB
F_OVFH
CLRB
F_OVFL
SETB
F_RMCERR
; Clear the remote-control "H" pulse width timer
value overflow flag
; Clear the remote-control "L" pulse width timer
value overflow flag
; Set the remote-control input status flag
;
JMP
IRQ01_RET
;
IRQ01_400:
BBS
F_OVFH,IRQ01_300
;
MOV
A,HPULSE
MOV
A,#0AH
CMP
A
BC
IRQ01_300
;
MOV
A,#19H
MOV
A,HPULSE
CMP
A
BC
IRQ01_300
;
BBS
F_RMCERR,IRQ01_300
;
MOV
A,LPULSE
MOV
A,#0FH
CMP
A
BC
IRQ01_300
;
MOV
A,#1DH
MOV
A,LPULSE
CMP
A
BC
IRQ01_600
;
CLRC
;
IRQ01_410:
MOV
A,RMCDATA+1
RORC
A
MOV
RMCDATA+1,A
MOV
A,RMCDATA
RORC
A
MOV
RMCDATA,A
;
MOV
A,BITCT
INCW
A
MOV
BITCT,A
;
MOV
A,#0CH
MOV
A,BITCT
CMP
A
BC
IRQ01_300
;
JMP
IRQ01_RET
;
IRQ01_600:
MOV
A,LPULSE
MOV
A,#22H
CMP
A
BC
IRQ01_300
;
MOV
A,#31H
MOV
A,LPULSE
CMP
A
BC
IRQ01_300
;
SETC
;
JMP
IRQ01_410
;**************************************
;*Time-base timer interrupt processing*
;**************************************
TBINT:
PUSHW
A
XCHW
A,T
PUSHW
A
PUSHW
IX
;
138
; Is "H" pulse width overflow not present?
; "H" pulse width >= #0ah (0.32 ms)?
; "H" pulse width =< #19h (0.75 ms)?
; Yes → "H" pulse width OK
; Remote-control input status OK?
; "L" pulse width >= #1fh (0.45 ms)?
; "L" pulse width =< #1dh (0.88 ms)?
; Yes → "L" pulse width = "0" data
; Clear the carry flag
; Enter the 1-bit data
; Increment the remote-control input bit counter
; Input bit =< 12?
; "L" pulse width >= #22h (1.05 ms)?
; "L" pulse width =< #31 (1.48 ms)?
; Yes → "L" pulse width = "1" data
; Set the carry flag
; Save the registers
CHAPTER 7 REMOTE-CONTROL SIGNAL RECEIVING
CLRB
TBOF
; Clear the interrupt flag
CLRB
IE10
; Disable the external interrupt
MOV
A,FRTMR
; The remote-control frame cycle measurement
timer is operating?
BZ
TB_RET
;
;
;
CLRC
; Decrement the remote-control frame measurement
timer
SUBC
MOV
BNZ
A,#l
FRTMR,A
TB_RET
CMP
BNZ
BITCT,#12
TB_RET
; Input bit = 12?
SETB
F_MCIN
; Determine the remote-control input
SETB
IE10
; Enable the external interrupt
POPW
POPW
XCHW
POPW
IX
A
A,T
A
; Return the registers
; Time out?
;
;
;
TB RET:
;
;
RETI
;
PROG
ENDS
;********************************
;*
Vector address
*
;********************************
VECTOR CSEG
ABS
ORG
0FFECH
DW
TBINT
ORG
0FFFAH
DW
IRQ01INT
ORG
0FFFCH
DB
00H
DB
00H
DW
RESET
VECTOR ENDS
END
; Time-base timer interrupt
; External interrupt
; Reset mode
; Reset vector
139
Memo
140
APPENDIX
RESOURCE DEFINITION LIST
This appendix lists the resource definitions for the MB89160 series.
;*****************************************
;*
*
;*
MB89160 resource definition
*
;*
*
;*****************************************
RES160 dirseg abs
;
;//
Port Register
org
000h
PDR0
rb
1
; Port 0 data register
DDR0
rb
1
; Port 0 input/output direction register
PDR1
rb
1
; Port 1 data register
DDR1
rb
1
; Port 1 input/output direction register
PDR2
rb
1
; Port 2 data register
DDR2
rb
1
; Port 2 input/output direction register
rb
1
; Dummy bit
;
;//
SYCC: System clock control register 0007h
SYCC
rb
0
; System clock control register
CSO
rbit
1
; System clock selection bit
CS1
rbit
1
; System clock selection bit
SCS
rbit
1
; System clock select bit
WT0
rbit
1
; Oscillation stabilization time selection bit
WT1
rbit
1
; Oscillation stabilization time selection bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
SCM
rbit
1
; System clock monitor bit
;
;//
STBC: Standby control register 0008h
STBC
rb
0
; Standby control register
rbit
1
; Dummy bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
TMD
rbit
1
; Watch bit
RST
rbit
1
; Software reset bit
SPL
rbit
1
; Pin status specification bit
SLP
rbit
1
; Sleep bit
STP
rbit
1
; Stop bit
;
;//
WDTE: Watch dog control register 0009h
WDTE
rb
0
; Watch dog control register
WTE0
rbit
1
; Watch dog control bit
WTEl
rbit
1
; Watch dog control bit
WTE2
rbit
1
; Watch dog control bit
WTE3
rbit
1
; Watch dog control bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
CS
rbit
1
; Clock resource switching bit
;
;//
TBTC: Time-base timer control register 000Ah
TBTC
rb
0
; Time-base timer control register
TBR
rbit
1
; Time-base timer clear bit
TBC0
rbit
1
; Interval time specification bit
TBC1
rbit
1
; Interval time specification bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
TBIE
rbit
1
; Interval interrupt enable bit
TBOF
rbit
1
; Interval timer overflow bit
;
;//
WPCR: Watch prescaler control register 000Bh
WPCR
WCLR
WSO
rb
rbit
rbit
0
1
1
WSI
rbit
1
WIE
WIF
rbit
rbit
rbit
rbit
rbit
1
1
1
1
1
; Watch pre-scaler control register
; Watch pre-scaler clear bit
; Interrupt interval time specification bit by
watch
; Interrupt interval time specification bit by
watch
; Dummy bit
; Dummy bit
; Dummy bit
; Watch interrupt enable bit
; Watch interrupt flag bit
141
;
PDR3
PDR4
PDR5
;
;//
BZCR
BUZ0
BUZ1
BUZ2
rb
rb
rb
rb
1
1
1
1
; Port 3 data register
; Port 4 data register
; Port 5 data register
BZCR: Buzzer register 0010h
rb
0
rbit
1
rbit
1
rbit
1
rbit
1
rbit
1
rbit
1
rbit
1
rbit
1
;
;
;
;
;
;
;
;
;
Buzzer register
Buzzer selection bit
Buzzer selection bit
Buzzer selection bit
Dummy bit
Dummy bit
Dummy bit
Dummy bit
Dummy bit
;
;
PDR6
PDR7
;
;//
RCR1
HSC0
HSC1
HSC2
HSC3
BSC4
HSC5
RCK0
RCK1
;
;//
RCR2
SCL0
SCL1
SCL2
SCL3
SCL4
SCL5
RCEN
rb
org
1
rb
rb
1
1
0011h
; Dummy
; Port 6 data register
; Port 7 data register
RCR1: Remote-control control register 1 0014h
rb
0
; Remote-control control register 1
rbit
1
; Bit for setting the "H" pulse width of remotecontrol transmitting frequency
rbit
1
; Bit for setting the "H" pulse width of remotecontrol transmitting frequency
rbit
1
; Bit for setting the "H" pulse width of remotecontrol transmitting frequency
rbit
1
; Bit for setting the "H" pulse width of remotecontrol transmitting frequency
rbit
1
; Bit for setting the "H" pulse width of remotecontrol transmitting frequency
rbit
1
; Bit for setting the "H" pulse width of remotecontrol transmitting frequency
rbit
1
; Bit for selecting the basic clock of remotecontrol transmitting frequency
rbit
1
; Bit for selecting the basic clock of remotecontrol transmitting frequency
RCR2: Remote-control control register 2 0015h
rb
0
; Remote-control control register 2
rbit
1
; Bit for setting the cycle of remote-control
transmitting frequency
rbit
1
; Bit for setting the cycle of remote-control
transmitting frequency
rbit
1
; Bit for setting the cycle of remote-control
transmitting frequency
rbit
1
; Bit for setting the cycle of remote-control
transmitting frequency
rbit
1
; Bit for setting the cycle of remote-control
transmitting frequency
rbit
1
; Bit for setting the cycle of remote-control
transmitting frequency
rbit
1
; Dummy bit
rbit
1
; Bit for selecting the output permission of
remote-control transmitting frequency
;
rb
rb
;
;//
T2CR
T2STR
T2STP
T2CS0
T2CS1
T20S0
T2DSl
T21E
T21F
;
;//
TlCR
TlSTR
TlSTP
TlCS0
TlCS1
T10S0
Tl0Sl
T11E
T11F
142
1
1
; Dummy
; Dummy
T2CR: Timer 2 control register 0018h
rb
0
; Timer 2 control register
rbit
1
; Timer start bit
rbit
1
; Timer stop bit
rbit
1
; Clock source selection bit
rbit
1
; Clock source selection bit
rbit
1
rbit
1
rbit
1
; Interrupt enable bit
rbit
1
; Interrupt request flag bit
TlCR: Timer 1 control register 0019h
rb
0
; Timer 1 control register
rbit
1
; Timer start bit
rbit
1
; Timer stop bit
rbit
1
; Clock source selection bit
rbit
1
; Clock source selection bit
rbit
1
; Square wave output control bit
rbit
1
; Square wave output control bit
rbit
1
; Interrupt enable bit
rbit
1
; Interrupt request flag bit
;
T2DR
T1DR
;
;//
SMR:
SMR1
SST
BDS
CKS0
CKS1
SOE
SCKE
SIOE
SIDF
;
SDR:
SDR1
;
;//
CNTR1
TIE
OE
TIR
TPE
P0
P1
P_TX
;
;//
COMR1:
COMP1
;
;//
CNTR2
;
;//
COMR2:
COMP2
;
;
;//
ADC1
AD
SIFM
ADMV
ADI
ANS0
ANSI
ANS2
ANS3
;
;//
ADC2
TEST
EXT
ADMD
ADIE
ADCK
;
;//
ADCD
;
;//
EIEl
IE10
IEll
IE12
rb
rb
1
1
; Timer 2 data register
; Timer 1 data register
SMR,SMR1: Serial mode register 001Ch
rb
rbit
rbit
rbit
rbit
rbit
rbit
rbit
rbit
0
1
1
1
1
1
1
1
1
;
;
;
;
;
;
;
;
;
Serial mode register
Serial I/O transfer start bit
Transfer direction selection bit
Shift clock selection bit
Shift clock selection bit
Serial data output permission bit
Shift clock output permission bit
Serial I/O interrupt enable bit
Serial I/O interrupt request flag bit
rb
1
; Serial data register
CNTR1:
rb
rbit
rbit
rbit
rbit
rbit
rbit
rbit
rbit
PWM1 control register 001Eh
0
; PWM1 data register
1
; Interrupt enable bit
1
; Output signal control bit
1
; Interrupt request flag bit
1
; Counter operation permission bit
1
; Clock selection bit
1
; Clock selection bit
1
; Dummy bit
1
; Timer, PWM and switching bit
COMR1,COMP1: PWM1 data register 001Fh
rb
1
; PWM1 data register
CNTR2: PWM2 control register 0020h
rb
1
; PW2 control register
COMR2,COMP2: PWM2 data register 0021h
rb
1
; PWM2 data register
rb
rb
rb
rb
rb
rb
rb
rb
rb
rb
rb
1
1
1
1
1
1
1
1
1
1
1
; Dummy
ADC1: A/D control register 1 002Dh
rb
0
; A/D control register 1
rbit
1
; A/D conversion start bit
rbit
1
; Interrupt factor set bit
rbit
1
; Converting flag
rbit
1
; Interrupt flag set
rbit
1
; Analog input selection bit
rbit
1
; Analog input selection bit
rbit
1
; Analog input selection bit
rbit
1
; Analog input selection bit
ADC2: A/D control register 2 002Eh
rb
0
; A/D control register 2
rbit
1
; Test bit
rbit
1
; Continuous conversion permission bit
rbit
1
; Function switching bit
rbit
1
; Interrupt enable specification bit
rbit
1
; Input clock selection bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
ADCD: A/D data register 002Fh
rb
1
; A/D data register
EIE1: External interrupt 1 control register 0030h
rb
0
; External interrupt 1 control register
rbit
1
; External interrupt operation enable bit
rbit
1
; External interrupt operation enable bit
rbit
1
; External interrupt operation enable bit
143
IE13
SIV0
SIV1
SIV2
SIV3
;
;//
EIF1
IF10
IF11
IF12
IF13
;
;//
EIE2
IE20
IE21
IE22
IE23
IE24
IE25
IE26
IE27
;
;//
EIF2
IF20
rbit
rbit
rbit
rbit
rbit
1
1
1
1
1
;
;
;
;
;
External
External
External
External
External
interrupt
interrupt
interrupt
interrupt
interrupt
operation enable bit
input reverse bit
input reverse bit
input reverse bit
input reverse bit
EIF1: External interrupt 1 flag register 0031h
rb
0
; External interrupt 1 flag register
rbit
1
; Falling edge detection flag bit
rbit
1
; Falling edge detection flag bit
rbit
1
; Falling edge detection flag bit
rbit
1
; Falling edge detection flag bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
EIE2: External interrupt 2 control register 0032h
rb
0
; External interrupt 2 control register
rbit
1
; External interrupt operation enable bit
rbit
1
; External interrupt operation enable bit
rbit
1
; External interrupt operation enable bit
rbit
1
; External interrupt operation enable bit
rbit
1
; External interrupt operation enable bit
rbit
1
; External interrupt operation enable bit
rbit
1
; External interrupt operation enable bit
rbit
1
; External interrupt operation enable bit
EIF2: External interrupt 2 flag register 0033h
rb
0
; External interrupt 2 flag register
rbit
1
; INT27 to INT20 low level detection flag bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
rbit
1
; Dummy bit
;
org
rb
rb
rb
rb
rb
rb
rb
rb
rb
rb
rb
rb
0034h
1
1
1
1
1
1
1
1
1
1
1
1
org
rb
0040h
16
org
rb
0050h
16
org
rb
0060h
12
rb
rb
rb
rb
rb
rb
1
1
1
1
1
1
; Dummy
;
;
;
VRAM
;
;
;//
LCDR
FP0
FPl
MS0
MSI
BK
VSEL
LCEN
CSS
;
; Dummy
LCDR: LCDC control register 0072h
rb
0
; LCDC control register
rbit
1
; LCD clock cycle selection bit
rbit
1
; LCD clock cycle selection bit
rbit
1
; Display mode selection bit
rbit
1
; Display mode selection bit
rbit
1
; Display/display blanking selection bit
rbit
1
; LCD drive power//rated voltage generation
circuit control bit
rbit
1
; Operation permission bit in the watch mode
rbit
1
; Clock selection bit for frame cycle generation
rb
rb
rb
144
; LCD display data RAM
1
1
1
; Dummy bit
; Dummy bit
; Dummy bit
rb
rb
rb
rb
rb
rb
1
1
1
1
1
1
;
;
;
;
;
;
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
bit
bit
bit
bit
bit
bit
;
;//
ILRl
ILR2
ILR3
org
007Ch
ILR1: Interrupt level set register 1007Ch
rb
1
; Interrupt level set register 1
rb
1
; Interrupt level set register 2
rb
1
; Interrupt level set register 3
rb
1
;
RES160
;
ends
end
145
Memo
146
CHAPTER 7 REMOTE-CONTROL SIGNAL RECEIVING
INDEX
The indexes consist of the keyword index, the subtitle index and the figure and table
index.
They are listed in numeric and alphabetic order.
Keyword Index ............................................................................................ 148
<Numerical Order> ................................................................................. 148
<Alphabetical Order>.............................................................................. 148
Subtitle Index .............................................................................................. 150
<Alphabetical Order>.............................................................................. 150
Figure and Table Index ............................................................................... 152
<Alphabetical Order>.............................................................................. 152
147
Keyword Index
<Numerical order>
E2PROM access indication command
storage area .......................................................... 82
EEPROM access supervisory processing ............. 91
external interrupt 1 control register ............... 59, 131
external interrupt 2 control register ....................... 10
external interrupt processing ............................... 137
1
F
16-bit timer interrupt ............................................ 115
flag .............................................................. 106, 132
flag area ................................................................ 83
flag area for A/D entry ........................................... 27
8
8/16-bit timer ....................................................... 105
8-bit PWM1 timer compare register .................. 9, 59
8-bit PWM1 timer control register ......................... 59
8-bit timer 1 ......................................................... 131
H
hardware ................................................................. 3
I
<Alphabetical order>
A
A/D converter control register 1 ............................ 26
A/D converter control register 2 ............................ 27
A/D entry data area ............................................... 27
A/D interrupt .......................................................... 31
activating interrupt ............................................... 114
activation of A/D conversion .................................. 30
address pointer initial value ................................. 107
address storage area ............................................ 83
B
bit pointer ............................................................ 107
bit pointer initial value .......................................... 107
initialization .... 16, 30, 44, 66, 90, 113, 116, 121, 136
input/output port ...................... 8, 26, 39, 58, 80, 104
interrupt level set register .... 10, 27, 39, 60, 105, 130
interval time ......................................................... 103
interval time counter ............................................ 107
J
JAMP TABLE ........................................................ 94
K
key ....................................................................... 121
key scan ................................................................ 16
key-entry chattering counter .................................. 13
key-entry data storage area .................................. 12
key-entry storage area .......................................... 13
L
C
counter of the minimum number of transmission 107
counter of the number of the output data ............ 107
creating the key code .......................................... 118
custom code ........................................................ 106
custom set ........................................................... 117
LCD clock display ..................................................37
LCD control register .............................................. 39
LCD display edit processing .................................. 46
LCD display output processing ............................. 47
LCD display segment data table 1 ........................47
LCD display segment data table 2 ........................48
D
M
data ..................................................................... 106
data read process ................................................. 92
data set ............................................................... 116
data write process ................................................. 91
main routine .................. 17, 30, 45, 67, 90, 113, 136
minimum number of transmission ....................... 103
N
E
number of output data ......................................... 106
E2PROM access buffer ......................................... 83
E2PROM access indication address storage area 82
E2PROM access indication byte counter .............. 82
O
148
Keyword Index
output data buffer ................................................107
P
processing for initialization .................................... 67
processing for key scan interrupt .......................... 17
R
RAM definition ............... 16, 30, 44, 66, 90, 112, 136
read data ............................................................... 83
register .................................................................. 37
remote-control control register ............................ 104
remote-control frame frequency
measurement timer ............................................. 132
remote-control input bit counter .......................... 132
remote-control input data .................................... 132
remote-control pulse width measurement
value ................................................................... 132
resource ................................................................ 37
S
sample program .................................................... 16
segment data set .................................................. 46
serial data register ................................................ 81
serial mode register .............................................. 81
setting the block write protection ........................... 91
setting transmitting data ...................................... 114
standby control register ..................................... 9, 38
status register read process .................................. 93
system clock control register ...................... 8, 38, 58,
80, 104, 130
T
T period ............................................................... 106
T_OUT ................................................................ 107
time update processing ......................................... 45
time-base timer ................................................... 130
time-base timer interrupt ..................................... 119
time-base timer interrupt processing ................... 138
timing chart ............................................................. 3
transmission ........................................................ 116
transmitting data table ......................................... 117
V
vector .................................................................... 49
vector address .................... 19, 31, 73, 95, 121, 139
W
wake-up processing .............................................. 18
watch interrupt processing .................................... 47
watch prescaler control register ............................ 38
write data output process ...................................... 92
write data source address storage area ................ 82
write inhibition set process .................................... 93
write permission process ...................................... 94
Keyword Index
149
Subtitle Index
<Alphabetical order>
C
Circuit diagram for the E2PROM interface ............ 77
Circuit diagram for the key scan sample
program ................................................................... 3
Circuit diagram for the key scan sample
program using the A/D conversion ........................ 23
Circuit diagram for the remote-control
signal receiving sample program ........................ 124
Circuit diagram for the remote-control signal
transmitting sample program ................................. 98
Circuit diagram for the software UART
sample program .................................................... 52
Conditions for the key scan sample program .......... 2
Conditions for the remote-control signal
transmitting sample program ................................. 98
Conditions for the Software UART
Sample Program ................................................... 52
Contents of flags for software UART ..................... 57
D
Data received by the software UART
sample program .................................................... 53
Data transmitted by the software UART
sample program .................................................... 53
Detailed flowchart for E2PROM interface .............. 84
Detailed flowchart for E2PROM interface
(data read) ............................................................. 87
Detailed flowchart for E2PROM interface
(data write) ............................................................ 88
Detailed flowchart for E2PROM interface
(status register read and block write protection) ... 86
Detailed flowchart for E2PROM interface
(write permission/inhibition OP code outputs) ....... 85
Detailed flowchart for Key Scan ............................ 14
Detailed flowchart for key scan using the A/D
conversion ............................................................. 28
Detailed flowchart for LCD clock display ............... 40
Detailed flowchart for LCD clock display
(Editing the display, LCD output, and
LCD segment output) ........................................... 42
Detailed flowchart for LCD clock display
(the watch update) ................................................ 41
Detailed flowchart for remote-control
signal receiving ................................................... 133
Detailed flowchart for remote-control
signal receiving (external interrupt) ..................... 134
Detailed flowchart for remote-control
signal receiving (time-base timer interrupt) ......... 135
150
Subtitle Index
Detailed flowchart for remote-control
signal transmitting ............................................... 108
Detailed flowchart for remote-control signal
transmitting (16-bit timer interrupt) ......................110
Detailed flowchart for remote-control signal
transmitting (transmitting data setting and
interrupt start) ...................................................... 109
Detailed flowchart for software UART ................... 61
Detailed flowchart for software UART
(receiving check, external interrupt, and
received data obtainment) .....................................63
Detailed flowchart for software UART
(timer interrupt) ...................................................... 64
Detailed flowchart for software UART
(UART initialization and transmitting
start processing) .................................................... 62
L
List of resource registers used for key scan ............ 6
O
Operation outline of the LCD clock
display sample program ........................................ 34
Operation outlines of the key scan
sample program ...................................................... 2
Operation outlines of the key scan
sample program using the A/D conversion ...........22
R
RAM allocations for E2PROM interface ................. 79
RAM allocations for key scan .................................. 7
RAM allocations for key scan using
the A/D conversion ................................................ 25
RAM allocations for LCD clock display ..................37
RAM allocations for remote-control
signal receiving ................................................... 128
RAM allocations for remote-control
signal transmitting ............................................... 102
RAM allocations for software UART ...................... 57
RAM initialization for E2PROM interface ............... 82
RAM initialization for key scan .............................. 12
RAM initialization for key scan using the A/D
conversion ............................................................. 27
RAM initialization for remote-control
signal receiving ................................................... 132
RAM initialization for remote-control
signal transmitting ............................................... 106
Register and RAM initialization for
software UART ...................................................... 58
Register and RAM initialization for the
LCD clock display sample program ....................... 38
Register initialization for E2PROM interface .......... 80
Register initialization for key scan using the A/D
conversion ............................................................. 26
Register initialization for remote-control signal
receiving .............................................................. 130
Register initialization for remote-control signal
transmitting (SYCC) ............................................ 104
Resource register initialization for key scan ............ 8
Resource registers for key scan using
the A/D conversion ................................................ 25
Resource registers used for LCD clock display .... 37
Resource registers used for
remote-control signal receiving ........................... 128
Resource registers used for
remote-control signal transmitting ....................... 102
Resource registers used for software UART ........ 56
Resource registers used for the E2PROM
interface ................................................................ 79
S
Sample program for E2PROM interface ................ 90
Sample program for key scan ............................... 16
Sample program for key scan using
the A/D conversion ................................................ 30
Sample program for LCD clock display ................. 44
Sample program for remote-control
signal receiving ................................................... 136
Sample program for remote-control
signal transmitting ............................................... 112
Sample program for software UART ..................... 66
Segment layout drawing for LCD clock display ..... 35
Skeletonized flowchart for E2PROM interface ...... 78
Skeletonized flowchart for key scan ........................ 4
Skeletonized flowchart for key scan using
the A/D conversion ................................................ 24
Skeletonized flowchart for LCD clock display ....... 36
Skeletonized flowchart for remote-control
signal receiving ................................................... 126
Skeletonized flowchart for remote-control
signal transmitting ............................................... 100
Skeletonized flowchart for software UART ........... 54
Specifications of the E2PROM Interface
Sample Program ................................................... 76
Specifications of the Key Scan Sample Program
using the A/D conversion ...................................... 22
Specifications of the LCD Clock Display
Sample Program ................................................... 34
Specifications of the remote-control
signal receiving sample program ........................ 124
Subtitle Index
151
Figure and table Index
<Alphabetical order>
A
A/D values corresponding to respective keys
(Table 2.1) ............................................................. 23
C
Circuit diagram for E2PROM interface
(Figure 5.1) ............................................................ 77
Circuit diagram for key scan using the A/D
conversion (Figure 2.1) ......................................... 23
Circuit diagram for the remote-control
signal receiving sample program (Figure 7.1a) ... 124
Circuit diagram for the remote-control signal
transmitting sample program (Figure 6.1a) ........... 98
Circuit diagram for the software UART sample
program (Figure 4.1a) ........................................... 52
Contents of flags at remote-control signal
transmitting address 80H (Table 6.3c) ................ 103
Contents of flags for software UART
(Table 4.3c) ........................................................... 57
D
Data format of the remote-control signal
receiving sample program (Figure 7.1b) ............. 125
Data format of the remote-control signal
transmitting sample program (Figure 6.1b) ........... 99
Detailed flowchart for E2PROM interface
(data read) (Figure 5.6.3) ...................................... 87
Detailed flowchart for E2PROM interface
(data write) (Figure 5.6.4) ...................................... 88
Detailed flowchart for E2PROM interface
(Figure 5.6) ............................................................ 84
Detailed flowchart for E2PROM interface
(Write permission/inhibition OP code output)
(Figure 5.6.1) ......................................................... 85
Detailed flowchart for key scan (Figure 1.6a) ........ 14
Detailed flowchart for key scan (interrupt
and wake-up) (Figure 1.6b) ................................... 15
Detailed flowchart for key scan using the A/D
conversion (Figure 2.5a) ....................................... 28
Detailed flowchart for key scan using the A/D
conversion (start and interrupt) (Figure 2.5b) ........ 29
Detailed flowchart for LCD clock display
(Editing the display, LCD output, and LCD
segment output) (Figure 3.6.2) .............................. 42
Detailed flowchart for LCD clock display
(Figure 3.6) ............................................................ 40
Detailed flowchart for LCD clock display
152
Figure and table Index
(the watch update) (Figure 3.6.1) .......................... 41
Detailed flowchart for remote-control signal
receiving (external interrupt) (Figure 7.6.1) .........134
Detailed flowchart for remote-control signal
receiving (Figure 7.6) ..........................................133
Detailed flowchart for remote-control signal
receiving (time-base timer interrupt)
(Figure 7.6.3) ....................................................... 135
Detailed flowchart for remote-control signal
transmitting (16-bit timer interrupt)
(Figure 6.6.2) ....................................................... 110
Detailed flowchart for remote-control signal
transmitting (Figure 6.6) ...................................... 108
Detailed flowchart for remote-control signal
transmitting (transmitting data setting and
interrupt start) (Figure 6.6.1) ............................... 109
Detailed flowchart for software UART
(Figure 4.5) ............................................................ 61
Detailed flowchart for software UART
(Receiving check, external interrupt, and
received data obtainment) (Figure 4.5.2) .............. 63
Detailed flowchart for software UART
(timer interrupt) (Figure 4.5.3) ...............................64
Detailed flowchart for software UART (UART
initialization and transmitting start processing)
(Figure 4.5.1) ......................................................... 62
Detailed flowchart for the E2PROM interface
(status register read and block write protection)
(Figure 5.6.2) ......................................................... 86
E
Example of hardware configuration for key scan
(Figure 1.1a) ............................................................ 3
F
Flag contents in the register for remote-control
signal receiving (80H) (Table 7.3c) ..................... 129
Format of data received by the software UART
sample program (Figure 4.1b) ...............................53
R
RAM allocations (Table 2.3b) ................................ 25
RAM allocations for E2PROM interface
(Table 5.3b) ........................................................... 79
RAM allocations for key scan (Table 1.3b) .............. 7
RAM allocations for LCD clock display
(Table 3.4b) ........................................................... 37
RAM allocations for remote-control signal
receiving (Table7.3b) ..........................................128
RAM allocations for remote-control signal
transmitting (Table 6.3b) ..................................... 103
RAM allocations for software UART
(Table 4.3b) ........................................................... 57
Resource registers (Table 2.3a) ............................ 25
Resource registers for remote-control signal
receiving (Table 7.3a) ......................................... 128
Resource registers for remote-control signal
transmitting (Table 6.3a) ..................................... 102
Resource registers for software UART
(Figure 4.3a) ......................................................... 56
Resource registers used for E2PROM interface
(Table 5.3a) ........................................................... 79
Resource registers used for key scan
(Table 1.3a) ............................................................. 6
Resource registers used for LCD clock display
(Table 3.4a) ........................................................... 37
S
Segment layout drawing for LCD clock display
(Figure 3.2) ........................................................... 35
Skeletonized flowchart for E2PROM interface
(Figure 5.2) ........................................................... 78
Skeletonized flowchart for key scan
(Figure 1.2) ............................................................. 4
Skeletonized flowchart for key scan using
the A/D conversion (Figure 2.2) ............................ 24
Skeletonized flowchart for LCD clock display
(Figure 3.3) ........................................................... 36
Skeletonized flowchart for remote-control
signal receiving (Figure 7.2) ................................ 126
Skeletonized flowchart for remote-control
signal transmitting (Figure 6.2) ........................... 100
Skeletonized flowchart for software UART
(External and timer interrupts) (Figure 4.2b) ......... 55
Skeletonized flowchart for software UART
(Figure 4.2a) ......................................................... 54
T
The transmitting data format of the software
UART sample program (Figure 4.1c) .................... 53
Timing chart when the "SW6" key is pushed
(Figure 1.1b) ........................................................... 3
Figure and table Index
153
CM25-00103-3E
FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL
F2MC-8L
8-Bit Microcontrollers
Application Note
Volume I
February 1997 the first edition
Published
FUJITSU LIMITED
Edited
Technical Communication Dept.
Electronic Devices