FUJITSU SEMICONDUCTOR DATA SHEET DS07-05602-5E Microprocessor SPARClite CMOS Peripheral LSI for SPARClite MB86941/942 ■ DESCRIPTION MB86941 and MB86942 are dedicated peripheral LSIs for SPARClite*. The MB86941 and MB86942 are designed to enable compact configuration of high-performance systems with SPARClite architecture, and provide the following features. * : SPARC is a registered trademark of SPARC International base on technology developed by Sun Microsystems, Inc. SPARClite is a trademark of SPARC International, Inc. licensed exclusively to Fujitsu Microelectronics, Inc. ■ FEATURES Direct connection to SPARClite Register read/write in 2 clock cycles up to 30MHz. Register read/write in 3 clock cycles at 40MHz (MB86941) or 50MHz (MB86942). Built-In On-Chip Modules: • Interrupt controller Interrupt input: 15 channels Each interrupt input has independent masking and trigger mode settings • 16-bit timer: 4 channels Two of the four channels have prescalers Each channel has five independent mode operations MODE0 : Periodical-interrupt MODE1 : Timeout-interrupt MODE2 : Square wave generator (Continued) ■ PACKAGE 144-pin Plastic QFP (FPT-144P-M03) MB86941/942 (Continued) MODE3: Programmable one shot (software trigger) MODE4: Programmable one shot (external trigger) • SDTR (Serial data transmitter receiver): 2 channels MB89251A type • Timing control, CS expansion Generates read, write and data strobe signals according to the requirements of external devices. • SIO (Synchronous serial input/output) Simple synchronous type serial input/output • I/O port, 16-bit Individual direction control by bit 5V single power supply (MB86941), 3.3V single power supply (MB86942) Upward pin compatibility with MB86940C 2 MB86941/942 ■ PIN ASSIGNMENT 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 INDEX 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 IPD0 CLK1 IN1 ACK1 PRSCK1 OUT1 VSS OUT0 PRSCK0 ACK0 IN0 CLK0 DSR1# CTS1# RTS1# TRNDT1 DTR1# VSS VDD SYBRK1 TRDY1 RCLK1 RCVDT1 RDYOUT# TCLK1# DS# TEMP1 VSS RRDY1 RRDY0 TEMP0 TCLK0# RCVDT0 A1 A0 RCS# VDD IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRL3 IRL2 VSS IRL1 IRL0 IRQ6 IRQ5 IRQ4 IRQ3 CS0# READY2#* VDD VSS READY1# CS1# IRQ2 IRQ1 CS2# CS3# DSR0# CTS0# RTS0# TRNDT0 VSS DTR0# SYBRK0 TRDY0 RCLK0 RE# WE# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SIRXD SITXD SIIRQ N.C. WSEL SICLK N.C. N.C. VSS RESET# CLOCK AS# RD/WR# CS# N.C. D8 D9 VDD VSS D10 D11 RS4 RS3 RS2 RS5 RS1 RS0 D12 D13 VSS D14 D15 IRQ15 IRQ14 IRQ13 IRQ12 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 N.C. IPD15 IPD14 IPD13 IPD12 IPD11 VSS D7 D6 IPD10 IPD9 N.C. IPD8 IPD7 IPD6 D5 D4 VSS VDD D3 D2 IPD5 IPD4 IPD3 IPD2 D1 D0 VSS OUT3 OUT2 IPD1 IN2 CLK2 IN3 CLK3 VDD (TOP VIEW) (FPT-144P-M03) * : Only for MB86941. Open for MB86942. 3 MB86941/942 ■ BLOCK DIAGRAM IRL < 3 : 0 > 1 / 2 Clock ÷2 1 / 1 Clock CLOCK RESET# AS# RD/WR# BIU Reset IRC Interrupt Request Controller Bus Interface Unit IRQ1 to IRQ15 CS# PRS0 RS < 5 : 0 > D < 15 : 0 > Prescaler ACK0 PRSCK0 READY1# READY2#* TM0 WSEL CLK0 Timer RCS# A<1:0> RDYOUT# IN0 RCSTG OUT0 Read/Write Chip Select Timing Generator PRS1 CS0# to CS3# Prescaler RE# ACK1 WE# PRSCK1 DS# TM1 CLK1 Timer IN1 IP OUT1 I/O Port IPD < 15 : 0 > TM2 CLK2 Timer SICLK SIRXD SITXD SIIRQ SIO IN2 Serial Data Input Output OUT2 TM3 Timer DSR0#, CTS0# RTS0#, DTR0# TEMP0, TRDY0 SDTR0 IN3 Serial Data Transmitter Receiver OUT3 TRNDT0 TCLK0# RCLK0, RCVDT0 SYBRK0 RRDY0 DSR1#, CTS1# RTS1#, DTR1# TEMP1, TRDY1 TRNDT1 SDTR1 Serial Data Transmitter Receiver TCLK1# RCLK1, RCVDT1 SYBRK1 RRDY1 * : Only for MB86941. Open for MB86942. 4 CLK3 Internal Data Bus Internal Control Bus MB86941/942 ■ DESCRIPTION OF BLOCK FUNCTIONS 1. BIU (Bus Interface Unit) This block receives MPU (SPARClite) bus signals and bus controls signals (CLOCK, AS#, RD/WR#, CS#, ADR6 to ADR2, D<15:0>) and generates control signals for accessing MB86941/MB86942 internal resources. It also returns that Ready signal to the MPU which corresponds to the access time of each of such resources. 2. IRC (Interrupt Request Controller) This block provides 15-channel interrupt input signals to transmit the interrupt level IRL <3:0> for each interrupt to the SPARClite. 3. TM (Timer) and PRS (Prescaler) TM0 to TM3 are 16-bit timers serving as periodic interrupt generation timers, a watchdog timer, and an external event counter. The operating clock can be selected from among the internal clock, the clock frequency-divided by the prescaler, and the external clock. Prescalers 0 and 1 are linked with timer channels 0 and 1, respectively. Each of the prescalers is initialized upon loading (or reloading) of the timer initial value of the corresponding timer. 4. SDTR (Serial Data Transmitter Receiver) SDTR0 and SDTR1 are serial data transmitter/receiver modules programmable for control of transmission and reception. The programming model is the same as that for the MB89251A. 5. RCSTG (Read/Write Timing Generator) This module generates read, write, and data strobe signals conforming to the required timings for external connection of other devices. The assert timing and pulse width of each signal to be generated is programmable. 6. IP (I/O Port) There are 16 I/O ports. The input/output direction of each port can be set by the control register. 7. SIO (Serial Data Input Output) This block is a clock-synchronous serial interface. The transfer clock signal can be set to the internally generated or externally input one. The SIO outputs data to be transmitted and inputs received data in synchronization with the transfer clock signal. 5 MB86941/942 ■ PIN DESCRIPTION IRQ15 to IRQ1 IRL < 3 : 0 > MB86941/2 MPU INTERFACE (34/33) CLOCK RESET# ACK0 PRSCK0 AS# CLK0 RD/WR# CS# IN0 OUT0 IRC (15) RS < 5 : 0 > D < 15 : 0 > READY1# ACK1 PRSCK1 READY2#* CLK1 IN1 WSEL OUT1 RCS# RCSTG (11) IP (16) A<1:0> CLK2 RDYOUT# IN2 TIMER & PRESCALER (16) OUT2 CS0# to CS3# RE# WE# CLK3 IN3 DS# OUT3 IPD < 15 : 0 > SICLK SIRXD SI0 (4) SITXD SIIRQ DSR1# RTS1# DTR1# SDTR1 (12) CTS1# TRNDT1 TEMP1 CTS0# TRNDT0 TRDY1 TRDY0 TCLK1# RCVDT1 RCLK1 TCLK0# RCVDT0 RCLK0 SYBRK1 RRDY1 SYBRK0 RRDY0 VDD: (6) VSS: (12) N.C.: (6/7) Note: Numerical value of a parenthesis shows numbers of PIN. * : Only for MB86941. Open for MB86942. 6 DSR0# RTS0# DTR0# TEMP0 SDTR0 (12) MB86941/942 1. MPU INTERFACE SIGNALS (34/33) Pin symbol RESET# CLOCK I/O Pin no. I 118 I 119 Pin name Description Reset Reset input pin Input an “L” signal to this pin to reset the chip. Clock System clock input pin The chip contains some modules that use the clock signal from this pin (not divided), and other modules that use the clock signal divided in half. Clock not divided: BIU, RCSTG, IP Clock divided: IRC, PRS0, PRS1, TM0 to TM3, SDTR0, SDTR1, SIO AS# I 120 Address Strobe Address strobe input pin Input an “L” signal to this pin to determine register access according to the signals input to the RS<5:0>, CS#, and RD/WR# pins. RD/WR# I 121 Read/Write Read/write input pin Input an “H” signal to designate a read cycle, or an “L” signal to designate a write cycle. CS# I 122 Chip Select Chip select input pin RS0 I 135 Register Select 0 RS1 I 134 Register Select 1 RS2 I 132 Register Select 2 RS3 I 131 Register Select 3 RS4 I 130 Register Select 4 RS5 I 133 Register Select 5 READY1# O 20 Ready 1 READY2# O 17 Ready 2 WSEL I 113 Wait Select Register select input pin The combination of input signals to the RS<5:0> and CS# pins determines which register is accessed. The RS5 pin has internal pull-down resistance (MB86941 only). Data ready output pin MB86941: Open drain output with 12mA “L” drive capability. Drives an “H” level signal for 3ns before going to High-Z state. MB86942: Normal output. READY2# signal deleted. If the READY generator circuit in the MPU is used, it is not necessary to connect this pin to the MPU. Wait select input pin Input to this pin determines the interface timing with the MPU. Fix “L” to set register read/write access to 3 cycles, or fix “H” to set register read/write access to 2 cycles. This pin has internal pull-up resistance (MB86941 only). (Continued) 7 MB86941/942 (Continued) Pin symbol 8 I/O Pin no. Pin name D0 I/O 82 Data Bus 0 D1 I/O 83 Data Bus 1 D2 I/O 88 Data Bus 2 D3 I/O 89 Data Bus 3 D4 I/O 92 Data Bus 4 D5 I/O 93 Data Bus 5 D6 I/O 100 Data Bus 6 D7 I/O 101 Data Bus 7 D8 I/O 124 Data Bus 8 D9 I/O 125 Data Bus 9 D10 I/O 128 Data Bus 10 D11 I/O 129 Data Bus 11 D12 I/O 136 Data Bus 12 D13 I/O 137 Data Bus 13 D14 I/O 139 Data Bus 14 D15 I/O 140 Data Bus 15 IRL0 O 11 Interrupt Request Level 0 IRL1 O 10 Interrupt Request Level 1 IRL2 O 8 Interrupt Request Level 2 IRL3 O 7 Interrupt Request Level 3 Description Data I/O port These pins are used to transfer register read/write data. Interrupt request output pin These pins are used to generate interrupts to the MPU and notify the interrupt level. MB86941/942 2. INTERRUPT REQUESTS (15) Pin symbol I/O Pin no. Pin name IRQ1 I 23 Interrupt Request 1 IRQ2 I 22 Interrupt Request 2 IRQ3 I 15 Interrupt Request 3 IRQ4 I 14 Interrupt Request 4 IRQ5 I 13 Interrupt Request 5 IRQ6 I 12 Interrupt Request 6 IRQ7 I 6 Interrupt Request 7 IRQ8 I 5 Interrupt Request 8 IRQ9 I 4 Interrupt Request 9 IRQ10 I 3 Interrupt Request 10 IRQ11 I 2 Interrupt Request 11 IRQ12 I 144 Interrupt Request 12 IRQ13 I 143 Interrupt Request 13 IRQ14 I 142 Interrupt Request 14 IRQ15 I 141 Interrupt Request 15 Description Interrupt request pin Interrupt receiving priority: IRQ15 is highest priority and IRQ1 is lowest. A choice of four interrupt waveforms is available by mode setting for each of the 15 pins independently, including “H” level, “L” level, rising edge, and falling edge. Each input has a filtering function for short pulse signals, by which an interrupt request is recognized once a signal is detected at active level at three successive rising edges of the internal clock signal. Once an interrupt request is detected, it passes through priority control and masking control and is output at the IRL<3:0> pins as an interrupt request to the MPU. If these pins are not used, they should be fixed at inactive level. 9 MB86941/942 3. TIMER SIGNALS (16) Pin symbol 10 I/O Pin no. CLK0 I 61 IN0 I 62 OUT0 O 65 CLK1 I 71 IN1 I 70 OUT1 O 67 CLK2 I 76 IN2 I 77 OUT2 O 79 CLK3 I 74 IN3 I 75 OUT3 O 80 Pin name Description CLK0 : Timer Clock 0 to CLK3 : Timer Clock 3 Timer control signal pin These pins are used to input an external clock signal to the timer. In external clock mode these signals are synchronized with the internal clock. IN0 : Timer Input 0 to IN3 : Timer Input 3 Input pin for count operation control signals to the timer In MODE0 through MODE3, the input signal is a gate signal. In MODE4, the pins input an external trigger signal. OUT0 : Timer Output 0 to OUT3 : Timer Output 3 Timer output pin The output waveform is determined by the mode setting: • Periodic signal waveform output • Square wave output • One-shot pulse waveform output At reset, an “L” level signal is output. Prescaler asynchronous clock pin Input can be asynchronous with respect to the system clock signal input at the CLOCK pin. If an external clock signal is selected by the PRS0 and PRS1 registers, this signal can be used as a source clock for the prescaler. The clock signal divided by the prescaler is output at the PRSCK0, PRSCK1 pins. If these pins are not used, they should be fixed at “L” level. ACK0 I 63 Asynchronous Clock 0 ACK1 I 69 Asynchronous Clock 1 PRSCK0 O 64 PRSCK1 O 68 Prescaler Clock Output 0 Prescaler clock output pin Prescaler Clock Output 1 An “L” level signal is output at reset. MB86941/942 4. SDTR SIGNALS (24) Pin symbol I/O Pin no. Pin name DSR0# I 26 Data Set Ready 0 DSR1# I 60 Data Set Ready 1 RTS0# O 28 Request To Send 0 RTS1# O 58 Request To Send 1 DTR0# O 31 Data Terminal Ready 0 DTR1# O 56 Data Terminal Ready 1 CTS0# I 27 Clear To Send 0 CTS1# I 59 Clear To Send 1 TRNDT0 O 29 Transmit Data 0 TRNDT1 O 57 Transmit Data 1 TEMP0 O 42 Transmit Empty 0 TEMP1 O 46 Transmit Empty 1 TRDY0 O 33 Transmit Ready 0 TRDY1 O 52 Transmit Ready 1 Description Modem control signal DSR input pin The status of these pins is indicated at the status register bit 7. Modem control signal RTS output pin Set the command register bit 5 to “1” to output an “L” signal, or to “0” to output an “H” signal. These pins can be used as a DATA TERMINAL READY signal or a RATE SELECT signal of modem.Set the command register bit 1 to “1” to output an “L” signal, or to “0” to output an “H” signal. Modem CLEAR TO SEND pin To enable sending, the command register bit 0 must be set to “1” and also an “L” level signal must be input at these pins. Transmit Data pin Parallel data written to the data register is converted to serial data and output from these pins. In asynchronous mode, a start bit and stop bit are attached, and a parity bit may be attached if necessary. If there is no data to be sent in the SDTR module, in synchronous mode a synchronizing character is output and in asynchronous mode the pins go to mark mode. If a send-prohibited setting (command register bit 0 set to “0”) is in effect, or if an “H” signal is input at the CTS# pin, these pins to mark mode. However if a send-prohibited setting is entered while a sending operation is in progress, all sending data already written will be sent before these pins go to mark mode. In addition, in bisynchronous mode if the first synchronization character is being sent (synchronization standby), then these pins will go to mark mode after sending the second synchronization character. These pins indicate whether sending data is present. If there is no data to be sent in the SDTR module, the signal level is “H.” As soon as one byte of sending data is written, these pins go to “L” level at the fall of the write signal. Transmit Ready output pin When the CTS# signal is “L” and the command register is set to enable sending, these pins send an “H” level signal whenever the sending data buffer is empty. (Continued) 11 MB86941/942 Pin symbol I/O Pin no. Pin name TCLK0# I 41 Transmit Clock 0 TCLK1# I 48 Transmit Clock 1 RCVDT0 I 40 Receive Data 0 RCVDT1 I 50 Receive Data 1 RCLK0 I 34 Receive Clock 0 RCLK1 I 51 Receive Clock 1 Description Transmit Clock input pin In synchronous mode, the sending bit rate is fixed at the sending clock ×1, so that the clock signal input at these pins becomes the sending bit rate. In asynchronous mode, the sending bit rate will be the sending clock signal ×1, or ×1/16, or ×1/64 depending on the bit rate setting in the mode register. For example, if a 19.2 kHz clock signal is input at the TCLK# pin, the sending bit rate will be 19200 pbs with an ×1 setting, or 1200 pbs with an ×1/16 setting, or 300 pbs with an ×1/64 setting. Sending data is output in synchronization with the falling edge of the sending clock signal. Receive Data input pin Serial data input to these pins is converted to parallel data in the SDTR module and then can be read by the data bus. Receive Clock input pin In synchronous mode, the receiving bit rate is fixed at the receiving clock ×1, so that the clock signal input at these pins becomes the receiving bit rate. In asynchronous mode, the receiving bit rate will be the sending clock signal ×1, or ×1/16, or ×1/64 depending on the bit rate setting in the mode register. For example, if a 19.2 kHz clock signal is input at the RCLK pin, the receiving bit rate will be 19200 pbs with an ×1 setting, or 1200 pbs with an ×1/16 setting, or 300pbs with an ×1/64 setting. Receiving data is sampled in synchronization with the rising edge of the receiving clock signal. Note that in asynchronous mode ×1 speed differs from ×1/16 and ×1/64 speeds in that external synchronization of the RCLK and RCVDT signals is required. (Continued) 12 MB86941/942 (Continued) Pin symbol I/O Pin no. Pin name SYBRK0 I/O 32 Synchronous/Break Detect 0 SYBRK1 I/O 53 Synchronous/Break Detect 1 RRDY0 O 43 Receive Ready 0 RRDY1 O 44 Receive Ready 1 Description These pins can function as synchronization detect input, synchronization detect output, or break detect output pins, depending on the mode setting. • External synchronization mode setting: Synchronization signals are input at these pins. When the RCLK is “H” level and these pins receive an “H” signal in hunting operation, the data sampled at the next rise of RCLK is the starting bit of the receiving data. • Internal synchronization mode: These pins are used as the synchronization character detect output pins. When incoming data matches the synchronization character register setting (both characters must match in bisynchronous mode), an “H” signal is output here. Next, the status register is read and this signal returns to “L” at the end of the read signal. • Asynchronous mode: These pins function as break detect output pins. Immediately after a framing error, an “H” signal is output if all receiving data values (one frame including start bit, parity bit, and stop bit) are “0.” This “H” signal is cancelled if a “1” data is received before a reset is applied. Receive Ready output pin These pins are “H” level, when serial data received at the RCVDT0, RCVDT1 pins is converted to parallel data in the SDTR module and is in readable form. Then after the received data is read, these pins becomes “L” level at the end of the read signal. 13 MB86941/942 5. RCSTG SIGNALS (11) Pin symbol I/O Pin no. Pin name CS0# O 16 Expansion Chip Select 0 CS1# O 21 CS2# O 24 CS3# O 25 RE# WE# DS# RCS# O O I Expansion Chip Select output pin Expansion Chip Select 1 When the input to the RCS# pin is “L,” one of these Expansion Chip Select 2 chip select signals will be active depending on the combination of input signals to the A0, A1 pins. Expansion Chip Select 3 35 Expansion Read Enable output pin When the input to the RCS# pin is “L” and a bus cycle Expansion Read Enable begins with an “H” input to the RD/WR# pin, this pin produces a pulse of the designated width and the designated timing. 36 Expansion Write Enable output pin When the input to the RCS# pin is “L” and a bus cycle Expansion Write Enable begins with an “L” input to the RD/WR# pin, this pin produces a pulse of the designated width and the designated timing. 47 37 Expansion Data Strobe Expansion Data Strobe output pin When a bus cycle begins with the RCS# pin input at “L” level, this pin produces a pulse of the designated width and the designated timing. Resource Chip Select Resource Chip Select pin. This pin is used to input the chip select signal supplied to the module RCSTG. When the module RCSTG is used to generate the external resource chip select signals CS0# to CS3#, read strobe RE#, write strobe WE#, and data strobe DS#, the corresponding areas must be decoded. This pin has internal pull-up resistance (MB86941 only). A0 I 38 Address 0 A1 I 39 Address 1 RDYOUT# 14 O O Description 49 Ready Out These are the input pins for the address signal to the module RCSTG. When the module RCSTG is used to generate the external resource chip select signals CS0# to CS3#, read strobe signal RE#, write strobe signal WE#, and data strobe signal DS#, this address input signal is used to designate the byte position in the corresponding area. When the input to the RCS# pins is “L”’ level, the input signal to these pins determines which of the external resource chip select signals CS0# to CS3# goes active. These pins have internal pull-up resistance (MB86941 only). This is the output pin for the ready signal generated by the module RCSTG. When the module RCSTG is used to generate the external resource chip select signals CS0#-CS3#, read strobe signal RE#, write strobe signal WE#, and data strobe signal DS#, the ready signal is output from these pins to the MPU. When any of the signals CS0# to CS1# is at “L” level, this signal is asserted with the designated timing interval. MB86941/942 6. I/O PORT SIGNALS (16) Pin symbol I/O Pin no. Pin name IPD0 I/O 72 I/O Port 0 IPD1 I/O 78 I/O Port 1 IPD2 I/O 84 I/O Port 2 IPD3 I/O 85 I/O Port 3 IPD4 I/O 86 I/O Port 4 IPD5 I/O 87 I/O Port 5 IPD6 I/O 94 I/O Port 6 IPD7 I/O 95 I/O Port 7 IPD8 I/O 96 I/O Port 8 IPD9 I/O 98 I/O Port 9 IPD10 I/O 99 I/O Port 10 IPD11 I/O 103 I/O Port 11 IPD12 I/O 104 I/O Port 12 IPD13 I/O 105 I/O Port 13 IPD14 I/O 106 I/O Port 14 IPD15 I/O 107 I/O Port 15 Description Signal I/O port These pins may be used for input or output, as determined by register setting. These pins have internal pull-up resistance (MB86941 only). 7. SIO SIGNALS (4) Pin symbol SICLK I/O I/O Pin no. 114 Pin name Description SIO Clock This is the input/output pin for the clock signal used for SIO serial data transfer. In external clock mode, the clock signal for serial data transfer is input at this pin. In internal clock mode, the clock signal from the internal clock generator is output at this pin. This pin has internal pull-up resistance (MB86941 only). SIRXD I 109 SIO Receive Data SIO Receive Data input pin This pin receives data input LSB first, synchronously with the SICLK pin clock signal. This pin has internal pull-up resistance (MB86941 only). SITXD O 110 SIO Transmit Data SIO Transmit Data output pin This pin outputs data LSB first, synchronously with the SICLK pin clock signal. SIIRQ O 111 SIO Interrupt Request SIO Interrupt Request output pin 15 MB86941/942 8. VDD, VSS, N.C. (24/25) Pin symbol I/O Pin no. Pin name VDD 1, 18, 54, 73, 90, 126 Power supply input pin VSS 9, 19, 30, 45, 55, 66, 81, 91, 102, 117, 127, 138 Grand pin N.C. 97, 108, 112, 115, 116, 123 (17*) These pins shall be used as an open pin. No. 17 is also an open pin for MB86942. * : No.17 is a READY2# pin for MB86941. 16 Description MB86941/942 ■ ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage VDD Input voltage VI Output voltage VO Storage temperature Rating Symbol MB86942 –0.5 to +0.6*1 –0.5 to +4.0*1 1 –0.3 to VDD + 0.5* –0.5 to VDD + 0.5* 1 At maximum VDD *4 VO = VDD +40 VO = 0 –40 VO = VDD +80 VO = 0 –40 VO = VDD +120 VO = 0 V °C –40 to 125 *5 *1: *2: *3: *4: *5: V –0.5 to VDD + 0.5* TSTG IO V 1 *3 Output current*2 Unit MB86941 VO = VDD +60 mA VO = 0 –60 –80 VSS = 0 V At 1 pin for 1 second Output pins other than D < 15 : 0 >, READY1# and REDY2# D < 15 : 0 > READY1#, READY2# WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power supply voltage VDD Operating temperature TA Value MB86941 MB86942 4.75 to 5.25 3.15 to 3.45 0 to +70 Unit V °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 17 MB86941/942 ■ ELECTRIC CHARACTERISTICS 1. DC Characteristics (1) Input Characteristics (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter “H” level input voltage “L” level input voltage Symbol VIH VIL MB86941 Condition MB86942 Min. Max. CLOCK 2.8 VDD IRQ15 to IRQ1 2.4 VDD Other 2.2 VDD IRQ15 to IRQ1 VSS 0.6 Other VSS 0.8 Unit Min. Max. VDD × 0.65 VDD + 0.15 V VSS VDD × 0.25 V (2) Output Characteristics (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter Symbol MB86941 Condition IOH = –8 mA*2 “H” level output voltage VOH IOH = –3.2 mA*3 IOH = –4 mA*4 MB86942 Min. Max. Min. Max. 4.0 VDD — — — — VDD – 0.5 VDD VSS 0.4 — — — — VSS 0.4 Unit V IOL = +12 mA*1 “L” level output voltage VOL IOL = +8 mA*2 IOL = +3.2 mA* IOL = +4 mA*4 *1: *2: *3: *4: 3 V MB86941 READY1#, READY2# MB86941 D < 15 : 0 > MB86941 Other than READY1#, READY2# and D < 15 : 0 > MB86942 (3) Power Supply Current (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter Power supply current 18 Symbol Condition ICC — MB86941 MB86942 Min. Max. Min. Max. — 230 — 190 Unit mA MB86941/942 2. Capacitances (VDD = VI = 0 V, f = 1 MHz, TA = +25°C) Parameter Symbol Value Unit Min. Max. CIN — 16 pF Output Capacitance COUT — 16 pF I/O Capacitance CI / O — 16 pF Input Capacitance 3. AC Test Conditions (1) Input/Output Signal Waveform tF tR VIH Input signal waveform Output delay 90% 10% MB86941: 1.5 V MB86942: 1 / 2 × (VIH + VIL) tPHL MB86941 : 1.5 V MB86942: VDD / 2 MB86941: 1.5 V MB86942: 1 / 2 × (VIH + VIL) tPLH VIL VOH MB86941: 1.5 V MB86942: VDD / 2 VOL tPZL Output enable/ disable MB86941: 1.5 V MB86942: VDD / 2 tPZH MB86941: 1.5 V MB86942: VDD / 2 tPLZ 0.5 V tPHZ VOL VOH 0.5 V tR, tF < 5 ns MB86941: VIH = CLOCK 2.8V, IRQ15 to IRQ1 2.4 V, Other 2.2 V, VIL = 0.4 V MB86942: VIH = VDD × 0.65, VIL = VDD × 0.25 19 MB86941/942 (2) Load Circuit VDD R1 = 2 KΩ SW1 MB86941/2 Output LSI tester R2 = 2 KΩ C SW2 VSS Load capacitance Condition MB86941 MB86942 Normal output 60 pF 30 pF Tri-state output (READY1#, READY2#) 65 pF — Bi-directional pin (D bus) 85 pF 30 pF SW1 SW2 L→H, H→L OFF OFF L→Z, Z→L ON OFF L→Z, Z→L OFF ON Signal transmit 4. AC Characteristics (1) Reset signal (Hardware reset) (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter Symbol Reset pulse width tRSTW tCLK: See “(2) Clock Signals.” tRSTW RESET# 20 Value Min. Max. 20 — Unit tCLK MB86941/942 (2) Clock signal (CLOCK) (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter MB86941 Symbol MB86942 Min. Max. Min. Max. Unit Clock cycle time tCLK 25 — 20 — ns Clock “H” pulse width tCLKH 9 — 8 — ns Clock “L” pulse width tCLKL 9 — 8 — ns Clock rise time tCLKR — 4 — 2 ns Clock fall time tCLKF — 4 — 2 ns tCLKF tCLKR tCLKL tCLKH CLOCK tCLK (3) MPU interface (Register read/write) (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) MB86941 Parameter Symbol WSEL = “H” WSEL = “L” MB86942 Min. Max. Min. Max. Min. Max. Unit AS# setup time tASS 11 — 7 — 7 — ns AS# hold time tASH 0 — 0 — 2 — ns CS# setup time tCSS 8 — 5 — 7 — ns CS# hold time tCSH 0 — 0 — 2 — ns RD/WR# setup time tRWS 13 — 9 — 7 — ns RD/WR# hold time tRWH 0 — 0 — 2 — ns RS < 5 : 0 > setup time tRSS 8 — 5 — 7 — ns RS < 5 : 0 > hold time tRSH 0 — 0 — 2 — ns READY1#, READY2# output delay time tRDYF 0 18 0 18 0 18 ns READY1#, READY2# hold time tRDYH 5 20 5 20 5 20 ns D < 15 : 0 > Output delay time at reading tODD 0 21 0 23 0 23 ns D < 15 : 0 > Output hold time at reading tODH 5 25 5 25 5 20 ns D < 15 : 0 > Input setup time at writing tIDS 11 — 7 — 7 — ns D < 15 : 0 > Input hold time at writing tIDH 0 — 0 — 0 — ns * : READY2# is available for MB86941. 21 MB86941/942 • WSEL = “H” CLOCK tASH tASH tASS AS# tCSH tCSS tCSH tRWH tRWS tRWH tRSH tRSS tRSH CS# RD/WR# RS < 5 : 0 > High-Z READY1# READY2#* tRDYF High-Z MB86942: “H” level output MB86942: “H” level output tODD D < 15 : 0 > at read * : Only for MB86941. tODH High-Z tIDS D < 15 : 0 > at write 22 tRDYH High-Z tIDH MB86941/942 • WSEL = “L” CLOCK tASH tASH tASS AS# tCSH tCSS tCSH tRWH tRWS tRWH tRSH tRSS tRSH CS# RD/WR# RS < 5 : 0 > High-Z READY1# READY2#* tRDYF tRDYH High-Z MB86942: “H” level output MB86942: “H” level output tODD D < 15 : 0 > at read tODH High-Z tIDS tIDH D < 15 : 0 > at write * : Only for MB86941. 23 MB86941/942 (4) Interrupt signal • Interrupt input pulse width (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter Symbol Value Min. Max. Unit IRQ input “H” level pulse width*1 tIHW 6 tCLK + 10 — ns 2 tILW 6 tCLK + 10 — ns IRQ input “L” level pulse width* tCLK: See “(2) Clock Signals.” *1: When the trigger mode is set for “H” level signal input or RISE-EDGE, a pulse of at least this width is received as a REQ-FF signal. Note that this rule does not guarantee that no interrupts less than this width will be received. *2: When the trigger mode is set for “L” level signal input or FALL-EDGE, a pulse of at least this width is received as a REQ-FF signal. Note that this rule does not guarantee that no interrupts less than this width will be received. tILW IRQx tIHW 24 MB86941/942 • Interrupt input clear (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter Value Symbol IRQx clear setup time* tIRQS Min. Max. 2 tCLK + 10 — Unit ns tCLK: See “(2) Clock Signals.” * : This parameter means the condition of REQUEST CLEAR execution and is applied at level trigger modes. IRQx (High Level Trigger) IRQx (Low Level Trigger) CLOCK AS# RD/WR# tIRQS REQ CLEAR 25 MB86941/942 • Interrupt level output (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter Symbol Value Min. Max. Unit IRL < 3 : 0 > clear delay time tIRLCD — 80 ns IRL < 3 : 0 > mask delay time tIRLMD — 80 ns CLOCK AS# CS# IRL clear IRL mask RD/WR# RS < 5 : 0 > High-Z READY1# READY2#* High-Z MB86942: “H” level output MB86942: “H” level output tIRLMD, tIRLCD IRS < 3 : 0 > * : Only for MB86941. 26 MB86941/942 (5) Prescaler timer • Prescaler input (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter Symbol MB86941 MB86942 Unit Min. Max. Min. Max. tACK 50 — 40 — ns Prescaler input clock “H” level width* tACHW 22 — 15 — ns Prescaler input clock “L” level width* tACLW 22 — 15 — ns Prescaler input clock rise time* tACR — 5 — 5 ns Prescaler input clock fall time* tACF — 5 — 5 ns Prescaler input clock cycle time* * : Applied in prescaler external clock mode. When the prescaler output is used as a timer signal, the timer input clock requirements must be met. tACF tACHW tACR tACLW ACLK0, ACLK1 tACK • Prescaler output (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter Symbol Standard Value Unit 1, 3 Prescaler output “L” level width* * tPSCLW 1 tPCK*4 Prescaler output “H” level width*1, *3 tPSCHW N–1 tPCK*4 Prescaler output “L” level width*2, *3 tPSCLW N ⋅ 2M – 1 tPCK*4 Prescaler output “H” level width*2, *3 tPSCHW N ⋅ 2M – 1 tPCK*4 *1: Applied when the prescaler register SELECT field is set to “0.” N: Value set in the prescaler register PRESCALE VALUE field *2: Applied when the prescaler register SELECT field is set to any value other than “0.” M: Value set in the prescaler register SELECT field. N: Value set in the prescaler register PRESCALE VALUE field. *3: When the prescaler register SELECT field is set to “0,” the PRSCKx output is fixed at “L” level. *4: tPCK has the following prescaler input clock period. Internal clock mode: tPCK = 2 ⋅ tCLK (For tCLK, see “(2) Clock Signals”) External clock mode: tPCK = tACK (For tACK, see “(5) Prescaler Timer Unit/Prescaler Input”) tPSCLW tPSCHW PRSCK0, PRSCK1 27 MB86941/942 • Timer (at external clock mode) (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter Value Symbol Min. Max. Unit Timer input clock “H” level width tTCKH 3 — tCLK Timer input clock “L” level width tTCKL 3 — tCLK GATE signal (IN pin) setup time (for CLKx) tGS 10 — ns GATE signal (IN pin) hold time (for CLKx) tGH 0 — ns tCLK: See “(2) Clock Signals”. tTCKH tGS tTCKL tGH CLKx INx (as IN pin of EVENT set “L”) INx (as IN pin of EVENT set “H”) • Timer output 1 (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter Symbol OUT output delay time (for CLOCK) tOUTD1 CLOCK tOUTD1 OUTx 28 Value Min. Max. — 30 Unit ns MB86941/942 • Timer output 2 (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter OUT output delay time* Value Symbol Min. Max. — 3 tCLK + 30 tOUTD2 Unit ns tCLK: See “(2) Clock Signals”. * : Applied to the following cases. • Setting mode (write to TCR). • After setting to MODE0, write to RELOAD register/read COUNT register. • After setting to MODE1, write to RELOAD register/read COUNT register. • After setting to MODE3, write to RELOAD register. CLOCK AS# CS# RD/WR# Set to MODE, read count RS < 5 : 0 > High-Z READY1# READY2#* High-Z MB86942: “H” level output MB86942: “H” level output OUTx tOUTD2 * : Only for MB86941. 29 MB86941/942 (6) SDTR • DSR#, RRDY (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter Symbol Value Min. Max. Unit DSR# setup time for resistor read tDSRS 28 — tCLK Interval from register read to RRDY off tRRDYL 0 100 ns tCLK: See “(2) Clock Signals”. CLOCK AS# CS# RS < 5 : 0 > Register read RD/WR# D < 15 : 0 > High-Z READY1# READY2#* High-Z MB86942: “H” level output MB86942: “H” level output tDSRS DSR# RRDY tRRDYL * : Only for MB86941. 30 MB86941/942 • DTR#, RTS#, TRDY Parameter (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Symbol Value Min. Max. Unit Delay time from register write to DTR# output tDTROD 0 40 tCLK Delay time from register write to RTS# output tRTSOD 0 40 tCLK Delay time from register write to TRDY output tTRDYOD 0 100 ns tCLK: See “(2) Clock Signals”. CLOCK AS# CS# RS < 5 : 0 > RD/WR# Register write D < 15 : 0 > READY1# READY2#* High-Z High-Z MB86942: “H” level output MB86942: “H” level output DSR#, RTS# TRDY tTRDYOD tRRDYL, tDTROD * : Only for MB86941. 31 MB86941/942 • Command write cycle (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter Symbol Min. Max. Unit Command write cycle time (for initial value setup) tCMDC 14 — tCLK Command write cycle time (for asynchronous mode) tCMDC 20 — tCLK Command write cycle time (for synchronous mode) tCMDC 40 — tCLK tCLK: See “(2) Clock Signals”. CLOCK ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ AS# ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ CS# ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ RD/WR# ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ READY1# READY2#* ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ tCMDC * : Only for MB86941. 32 Value MB86941/942 • Transmit Clock and Transmit Data Parameter (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Symbol Syncroh mode, × 1 mode ×1/16, ×1/64 mode Min. Max. Min. Max. Unit Transmit Clock “H” width tTCKHW 32 — 4 — tCLK Transmit Clock “L” width tTCKLW 14 — 4 — tCLK Interval from transmit clock falling to transmit data output tTCKDT 0 100 0 100 ns tCLK: See “(2) Clock Signals”. tTCKLW 64 1 2 3 16 1 2 3 TCLK# (× 1/64 mode) tTCKHW ⋅⋅⋅⋅⋅ 4 5 30 31 32 33 34 35 6 7 8 9 10 11 ⋅⋅⋅⋅⋅ 12 13 62 63 64 1 2 14 15 16 1 2 TCLK# (× 1/64 mode) tTCKLW tTCKHW TCLK# (× 1 mode, Sync mode) tTCKDT tTCKDT TRNDT 33 MB86941/942 • Receive Clock and Receive Data Parameter (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Syncroh mode, × 1 mode Symbol ×1/16, ×1/64 mode Unit Min. Max. Min. Max. tRCK 62 — 8 — tCLK Receive clock “H” width tRCKHW 12 — 4 — tCLK Receive clock “L” width tRCKLW 7 — 4 — tCLK Receive data setup time tRDS 6 — 6 — tCLK Receive data hold time tRDH 6 — 6 — tCLK Receive clock period tCLK: See “(2) Clock Signals”. RCLK (× 1 mode, Sync mode) tRCKLW tRCKHW tRCK tRDS tRDH RCVDT tTCKDT 16 1 2 3 64 1 2 3 4 5 6 7 8 9 10 11 30 31 32 33 34 35 12 13 14 15 16 1 2 62 63 64 1 2 RCLK (× 1/16 mode) RCLK (× 1/64 mode) ⋅⋅⋅⋅⋅ ⋅⋅⋅⋅⋅ tRCKLW tRCK 34 MB86941/942 • SYBRK Signal Timing for External Synchronous mode Parameter (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Symbol Value Min. Max. Unit SYBRK setup time (for RCLK) tBRKS 0 — tCLK SYBRK hold time (for RCLK) tBRKH 10 — tCLK tCLK: See “(2) Clock Signals”. RCLK SYBRK tBRKH tBRKS • Transmit and Receive Control Signal Timing (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter Symbol Value Min. Max. Unit Delay time from TCLK# rising (last bit) to TRDY rising tTCKRDY — 36 tCLK Delay time from TCLK# rising (last bit) to TEMP rising tTCKEMP — 24 tCLK Delay time from RCLK rising (last bit) to RRDY rising tRCKRDY — 35 tCLK Detection time from RCLK rising (last bit) to internal SYNC (SYBRK pin) tSYCD1 — 62 tCLK Detection time RCLK rising (last bit) to internal SYNC (status data buffer register) tSYCD2 — 70 tCLK tCLK: See “(2) Clock Signals”. 35 36 RCVEN set <1> SYBRK FERR bit OERR bit RRDY Read Strobe (Internal Signal) Write Strobe (Internal Signal) RCVDT RS < 5 : 0 > tRCKRDY Data 2 Data 1 Data 1 Loss Framing Error D0 D1 D2 D3 D4 P S1 S2 Error Reset <2> <1> < 2 >: Status data buffer selection Data 2 D0 D1 D2 D3 D4 P S1 S2 D0 D1 D2 D3 D4 P S1 S2 < 1 >: Control data buffer selection • Receive Timing Example 1 (Asynchronous mode, 5 data bits, Parity enable, 2 stop bits) <1> Error Reset Break Pattern Detection D0 D1 D2 D3 D4 P S1 S2 <2> MB86941/942 CTS# TEMP TRDY TRDY bit Write Strobe (Internal Signal) TRNDT RS < 5 : 0 > tTCKRDY tTCKEMP Data 2 Data 1 Data 2 D0 D1 D2 D3 D4 D5 S1 S2 <1> D0 D1 D2 D3 D4 D5 S1 S2 Data 1 <1> < 1 >: Transmit data buffer selection <2> Break Set D0 D1 D2 D3 Data 3 Data 3 <1> ...... ...... ...... ...... D0 D1 D2 D3 D4 D5 S1 S2 Data 4 Data 4 <1> Break Clear ...... ...... ...... < 2 > < 2 >: Control data buffer selection • Transmit Timing Example 1 (Asynchronous mode, 6 data bits, Parity enable, 2 stop bits) MB86941/942 37 38 CTS# TEMP TRDY TRDY bit Write Strobe (Internal Signal) TRNDT RS < 5 : 0 > <1> Data 1 Synchronous Character 2 Data 2 Synchronous Character 1 Data 2 ...... ...... ...... ...... Break Clear ...... ...... < 2 > ...... < 2 > <1> Data 3 Data 4 Data 4 D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 Data 3 <1> < 2 >: Control data buffer selection Break Set D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P Data 1 <1> < 1 >: Transmit data buffer selection • Transmit Timing Example 2 (Synchronous mode, Bisynchronous mode, 5 data bits, Parity enable) MB86941/942 OERR bit SYBRK bit SYBRK RRDY READ STROBE (Internal signal) WRITE STROBE (Internal signal) RCVDT RS < 5 : 0 > <2> <2> <1> <3> : STATUS DATA BUFFER SELECTION <3> < 2> : RECIEVE DATA BUFFER SELECTION <2> tSYCD2 tSYCD1 DATA 1 DATA 1 STATUS DATA 2 DATA 3 DATA 2 loss DATA 3 Synchronous Character 1 ERROR RESET Synchronous Character 1 Synchronous Character 2 D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P Synchronous Character 1 Synchronous Character 2 EMH, RCVEN set <1> <1> : CONTROL DATA BUFFER SELECTION • Transmit Timing Example 2 (Synchronous mode, Bisynchronous mode, 5 data bits, Parity enable) STATUS <3> MB86941/942 39 MB86941/942 (7) RCSTG • Control Signal Output Timing (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter 40 Symbol MB86941 MB86942 Min. Max. Min. Max. Unit RCS# setup time tRCSS 5 — 7 — ns RCS# hold time tRCSH 5 — 2 — ns A < 1 : 0 > setup time tADS 5 — 7 — ns A < 1 : 0 > hold time tADH 5 — 2 — ns Delay time from RCS#, A1, A0 fix to CS3# to CS0# fix tECSD — 15 — 18 ns Delay time from CLOCK to RE#, WE#, DS# fix tECNTD — 15 — 18 ns MB86941/942 • Register Read Control Signal Output Timing CLOCK AS# tRCSH tRCSS RCS# tADS tADH A<1:0> CS3# to CS0# tECSD tECSD RD/WR# DS# *1 *1 RE# *1 *1 WE# “H” tECNTD RDYOUT# tECNTD tECNTD tECNTD RD/WR# DS# *2 RE# *2 “H” WE# *2 *2 RDYOUT# tECNTD tECNTD tECNTD tECNTD *1: Set register RTR0, RTR1. *2: Set register WTR0, WTR1. 41 MB86941/942 (8) SIO • Control Signal Output Timing (MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C) (MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C) Parameter Value Symbol Min. Max. SICLK rise time tSCLKR — 3 ns SICLK fall time tSCLKF — 3 ns Setup time from SICLK rise/fall to valid SIRXD at receiving tSRD 80 — ns Delay time from SICLK rise/fall to SITXD output at transmitting Hold time from SICLK rise/fall to valid SITXD tDTD — 30 ns tHTD 80 — ns SICLK tSCLKR tSCLKF SICLK tSRD SIRXD SICLK tDTD SITXD 42 Unit tHTD MB86941/942 ■ NOTES ON USE When the prescaler is used in external clock mode, and the prescaler output signal is used as the timer operating clock, use the following settings. Set the timer operating clock to ’External clock’ (TCR bits 10, 9 = “01”), and connect the prescaler output pin PRSCK externally to the timer external clock input pin CLK. When the prescaler and timer are set to the following modes, the timer output signal OUT will not change at the anticipated time: Prescaler: External clock mode (PRESCALER REGISTER bit15 = “1”). Timer: Prescaler internal output signal used as operating clock, without using the external input pin (TCR bit 10, 9 = “10”). 43 MB86941/942 ■ REGISTER MAP Block name RS5 to RS0 (HEX) SDTR 1 Reserved PRESCALER0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM0 (TRIGGER MODE 0) CH15 CH14 CH13 CH12 CH11 CH10 CH9 01H TM1 (TRIGGER MODE 1) CH7 CH6 CH5 CH4 CH3 CH2 CH1 02H RS (REQ SENSE) 15 14 13 12 11 10 9 8 7 6 5 4 3 03H RC (REQ CLEAR) 15 14 13 12 11 10 9 8 7 6 5 4 04H MASK (MASK) 15 14 13 12 11 10 9 8 7 6 5 4 05H IRL (IRL Latch/Clear) — — — — — — — — — — — CL — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 06H 07H Reserved CH8 — — 2 1 — 3 2 1 — 3 2 1 IM IRL LATCH 08H SDR0 (SDTR Data 0) — — — — — — — — TRANSMIT DATA/ RECEIVE DATA 09H SCSR0 (SDTR CM/ST 0) — — — — — — — — CONTROL DATA/STATUS DATA — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SDR1 0CH (SDTR Dsta 1) — — — — — — — — TRANSMIT DATA/ RECEIVE DATA SCSR1 0DH (SDTR CM/ST 1) — — — — — — — — CONTROL DATA/ STATUS DATA 0EH — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — EX TEST — — — SDTR 0 Reserved bit 00H IRC Reserved Register name 0AH 0BH 0FH 10H Reserved Reserved PRS0 (PRESCALE 0) SELECT PRESCALE VALUE (Continued) 44 MB86941/942 Block name TIMER 0 PRESCALER1 TIMER 1 Reserved TIMER 2 Reserved TIMER 3 RS5 to RS0 (HEX) Register name bit 15 14 13 12 11 11H TCR0 (TIMER OT CONTROL 0) IN — TEST CE 12H RVR0 (RELOAD VALUE 0) RELOAD VALUE 13H CVR0 (COUNT VALUE 0) COUNT VALUE 14H PRS1 (PRESCALE 1) 15H TCR1 (TIMER OT CONTROL 1) 16H RVR1 (RELOAD VALUE 1) RELOAD VALUE 17H CVR1 (COUNT VALUE 1) COUNT VALUE 18H Reserved — — — — — 19H TCR2 (TIMER OT CONTROL 2) IN — TEST CE 1AH RVR2 (RELOAD VALUE 2) RELOAD VALUE 1BH CVR2 (COUNT VALUE 2) COUNT VALUE 1CH Reserved EX 10 9 CS 8 OCONT TEST — — — SELECT IN — TEST CE CS — — — — — TCR3 1DH (TIMER TO CONTROL 3) IN — TEST CE — — — CS — 6 IV 4 3 2 MODE IV — — OCONT IV — 5 1 0 EVENT PRESCALE VALUE OCONT CS — 7 — — OCONT IV 1EH RVR3 (RELOAD VALUE 3) RELOAD VALUE 1FH CVR3 (COUNT VALUE 3) COUNT VALUE MODE — — EVENT — — MODE — — MODE — — EVENT — — — — EVENT (Continued) 45 MB86941/942 (Continued) Block name RS5 to RS0 (HEX) 20H PDR (PORT DATA) 21H DCR (PORT DIRECTION) I/O PORT Reserved SIO Register name 22H 23H Reserved 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PORT DATA PORT DIRECTION — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 25H STR (SERIAL STATUS) — — — — — — — — 26H RDR (RECEIVE DATA) — — — — — — — — RECEIVE DATA 27H TDR (TRANSMIT DATA) — — — — — — — — TRANSMIT DATA 28H TRR (TRANSFER RATE) — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TREW TRDSW TREL TRDSL — — — — — — TWEW TWDSW TWEL TWDSL 2AH 2CH Reserved RTR0 (READ TIMING 0) WTR0 2DH (WRITE TIMING 0) CONTROL — — — — STATUS RATE SELECT 2EH RTR1 (READ TIMING 1) — — — — — — TREW TRDSW TREL TRDSL 2FH WTR1 (WRITE TIMING 1) — — — — — — TWEW TWDSW TWEL TWDSL TIMING1 46 14 SCR (SERIAL CONTROL) 2BH TIMING0 15 24H 29H Reserved bit MB86941/942 ■ ORDERING INFORMATION Part number Package MB86941PFV 144-pin Plastic QFP (FPT-144P-M03) MB86942PFV 144-pin Plastic QFP (FPT-144P-M03) Remarks 47 MB86941/942 ■ PACKAGE DIMENSION 144-pin Plastic QFP (FPT-144P-M03) 3.85(.152)MAX 22.60±0.20(.890±.008)SQ (Mounting height) 20.00±0.10(.787±.004)SQ 108 0.05(.002)MIN (STAND OFF) 73 109 72 17.50 (.689) REF 21.60 (.850) NOM Details of "A" part 0.15(.006) 0.15(.006) INDEX 0.15(.006)MAX 0.40(.016)MAX 37 144 "A" Details of "B" part LEAD No. 36 1 0.50(.0197)TYP 0.20±0.10 (.008±.004) 0.08(.003) M 0.125±0.05 (.005±.002) 0 10˚ 0.50±0.20(.020±.008) 0.10(.004) C 48 1995 FUJITSU LIMITED F144003S-2C-3 "B" Dimensions in mm (inches) MB86941/942 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F9812 FUJITSU LIMITED Printed in Japan 49