HIP5060 ® Power Control IC Single Chip PowerSupply T ent at UC OD lacem enter c R P ep rt C /ts R o om August 1998 ETE OL endedl Supp ersil.c S OB mm nica .int eco Tech r www R No t our IL o tac TERS n o N c I 88Features 1-8 • • • • • • • • • • The HIP5060 is a complete power control IC, incorporating both the high power DMOS transistor, CMOS logic and low level analog circuitry on the same Intelligent Power IC. Both the standard “Boost” and the “SEPIC” (Single-Ended Primary Inductance Converter) power supply topologies are easily implemented with this single control IC. Special power transistor current sensing circuitry is incorporated that minimizes losses due to the monitoring circuitry. Moreover, over-temperature and over-voltage detection circuitry is incorporated within the IC to monitor the chip temperature and the actual power supply output voltage. These circuits can disable the drive to the power transistor to protect both the transistor and, most importantly, the load from over-voltage. File Number 3207.2 Single Chip Current Mode Control IC 60V, 10A On-Chip DMOS Transistor Thermal Protection Over-Voltage Protection Over-Current Protection 1MHz Operation or External Clock Synchronization Output On-Chip Reference Voltage - 5.1V Output Rise and Fall Times ~ 3ns Designed for 27V to 45V Operation Applications • • • • As a result of the power DMOS transistor’s current and voltage capability (10A and 60V), power supplies with output power capability up to 100 watts are possible. Single Chip Power Supplies Current Mode PWM Applications Distributed Power Supplies Multiple Output Converters Ordering Information TEMPERATURE RANGE PACKAGE HIP5060DY 0oC to +85oC 37 Pad Chip HIP5060DW 0oC to +85oC Wafer PART NUMBER (7) VDDD (6) DGD2 (5) IRFI (4) IRFO (3) SPST (2) VINP (1) AGND Chip (8) VDDA FLTH (37) VREG (36) (9) V+ S (15) S (16) D (17) S (19) D (18) S (20) D (21) S (23) D (22) S (24) (14) VDDP D (25) (13) VDDP TMON (31) S (27) (12) DGD1 PSEN (32) D (26) SHRT (33) S (28) (11) CKIO D (29) (10) SLCT PSOK (34) D (30) VCMP (35) NOTE: Unused pads are for trim and test. 153 mils x 165 mils (3.88mm x 4.19mm) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HIP5060 Simplified Block Diagram 4µH 4µH 1.1µF VIN 0.1µF 100µF 0.1µF 4µH CLOCK AND CONTROL LOGIC VCMP 30.1K D V+ FLTN GATE DRIVERS S PSOK DG02 0.033µF SHRT VREG AMP PSEN 0.1µF VDDP TMON VDDP REFERENCE VINP DGD1 AGND CKIO SLCT VDDA VDDD 0.1µF IRF1 4.02K IRF0 SFST 0.1µF 0.1µF TYPICAL SEPIC CONFIGURATION 2 0.1µF 0.88µF 1 µF HIP5060 Absolute Maximum Ratings Thermal Information DC Supply Voltage, V+. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V DMOS Drain Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V DMOS Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20A DC Logic Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Output Voltage, Logic Outputs . . . . . . . . . . . . . . . . . . . -0.3V to 16V Input Voltage, Analog and Logic. . . . . . . . . . . . . . . . . . -0.3V to 16V Operating Junction Temperature Range . . . . . . . . . .0oC to +110oC Storage Temperature Range . . . . . . . . . . . . . . . . . -55oC to +150oC Thermal Resistance θJC (Solder Mounted to . . . . . . . . . . . . . . . . . . . . . . . . . 3oC/W Max 0.050” Thick Copper Heat Sink) Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +110oC (Controlled By Thermal Shutdown Circuit) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications V+ = 36V, TJ = 0oC to +110oC; Unless Otherwise Specified SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - 19.5 32 mA DEVICE PARAMETERS I+ Supply Current PSEN = 12V VDDA Internal Regulator Output Voltage V+ = 15V to 45V, IOUT = 10mA 11.0 - 13.2 V VINP Reference Voltage IVINP = 0mA 5.01 5.1 5.19 V RVINP VINP Resistance VINP = 0 - 900 - Ω Input Offset Voltage (VREG - VINP) IVCMP = 0mA - - 10 mV RIN VREG Input Resistance to GND VREG = 5.1V - 56 - kΩ gm (VREG) VREG Transconductance IVCMP/(VREG - VINP) VCMP = 1V to 8V, SFST = 11V 15 30 50 mS gm (SFST) SFST Transconductance IVCMP/(VREG - SFST) VSFST < 4.9V 0.8 - 6 mS IVCMP Maximum Source Current VREG = 4.95V, VCMP = 8V -2.5 - -0.75 mA IVCMP Maximum Sink Current VREG = 5.25V, VCMP = 0.4V 0.75 - 2.5 mA OVTH Over-Voltage Threshold Voltage at VREG for FLTN to be latched 6.2 - 6.7 V Internal Clock Frequency SLCT = 0V, V DDD = 12V 0.9 1.0 1.1 MHz External Clock Input Threshold Voltages SLCT = 12V 33 - 66 %VDDD ERROR AMPLIFIERS |VIO| CLOCK fq VTH CKIN DMOS TRANSISTORS rDS(on) IDSS Drain-Source On-State Resistance I Drain = 5A, TJ = +25oC - - 0.13 Ω Drain-Source Leakage Current Drain to Source Voltage = 60V - 1 100 µA IRFO = 0mA to -5mA, VCMP = 0.2V to 7.6V - - 125 mV 100 - 270 mV CURRENT CONTROLLED PWM |VIO| VCMP Buffer Offset Voltage (VCMP VIRFO) VTH IRFO Voltage at IRFO that disables PWM. This is due to low load current 3 HIP5060 Electrical Specifications V+ = 36V, TJ = 0oC to +110oC; Unless Otherwise Specified (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 7.4 - 8.0 V -37 - -17 µA 4 6 8 V CURRENT CONTROLLED PWM (Continued) ITH IRFO Voltage at IRFO to enable SHRT output current. This is due to Regulator Over Current Condition ISHRT SHRT Output Current, During Over-Current VTH SHRT Threshold voltage on SHRT to set FLTN latch VIRFO = 8.1V IGAIN IPEAK (DMOSDRAIN)/IIRFI ∆I (DMOSDRAIN)/∆t = 1A/ms 3.8 - 4.9 A/mA RIRFI IRFI Resistance to GND IIRFI = 2mA 150 - 360 Ω tRS (Note 1) Current Comparator Response Time ∆I (DMOSDRAIN)/∆t > 1A/µs - 30 - ns MCPW (Note 1) Minimum Controllable Pulse Width 25 50 100 ns MCPI (Note 1) Minimum Controllable DMOS Peak Current 200 400 800 mA V+ Rising V+ Power-On Reset Voltage 22 - 27 V V+ Falling V+ Power-Off Set Voltage - 15 - V V+ V+ Power-On Hysteresis 9 - 12 V 0.8 - 2.0 V - 20 - KΩ -1.0 -0.7 -0.4 µA START-UP VTH PSEN Voltage at PSEN to Enable Supply rPSEN Internal Pull-Up Resistance, to 5.1V ISFST Soft-Start Charging Current VSFST = 0V to 10V IPSOK PSOK High-State Leakage Current SFST = 0V, PSOK = 12V -1 - 1 µA VPSOK PSOK Low-State Voltage SFST = 11V, IPSOK = 1mA - - 0.4 V 9.4 - 11 V 105 - 135 oC VTH SFST PSOK Threshold, Rising V SFST THERMAL MONITOR TEMP (Note 1) Substrate Temperature for Thermal Monitor to Trip TMON pin open NOTE: 1. Determined by design, not a measured parameter. 4 HIP5060 Pin Descriptions PAD NUMBER DESIGNATION 1 AGND Analog ground. 2 VINP Internal 5.1V reference. 3 SFST Controls the rate of rise of the output voltage. Time is determined by an internal 0.7µA current source and an external capacitor. 4 IRFO A resistor placed between this pad and IRFI converts the VCMP signal to a current for the current sense comparator. The maximum current is set by the value of the resistor, according to the equation: IPEAK = 32/R. Where R is the value of the external resistor in KΩ and must be greater than 1.5KΩ but less than 10KΩ. For example, if the resistor chosen is 1.8K, the peak current will be 17.8A. This assumes VCMP is 7.3V. Maximum output current should be kept below 20A. 5 IRFI See IRFO 6 DGD2 Ground of the DMOS gate driver. This pad is used for bypassing. 7 V DDD Voltage input for the chip’s digital circuits. This pad also allows decoupling of this supply. 8 VDDA This is the analog supply and internal 12V regulator output. 9 V+ This is the main supply voltage input pad to the regulator IC. Because of the high peak currents this pad must be well bypassed with at least a 0.7µF capacitor and may be composed of seven, single 0.1µF chip capacitors. 10 SLCT This pad provides for the option of using either internal 1MHz operation of for an external clock. Floating or grounding this pad will place the internal clock at the CKIO pad. Returning this terminal to V DDD or 12V will allow application of an external clock to the IC via the CKIO pad. There is an internal 50K pull down 11 CKIO Clock output when SLCT is floated or grounded. External clock input when SLCT is returned to 12V. 12 DGD1 This pad is the return for the digital supply. 13 & 14 VDDP These pads are used to decouple the high current pulses to the output driver transistors. The capacitor should be at least a 0.1µF chip capacitor placed close to this pad and the DMOS source pads. 15, 16, 19, 20, 23, 24, 27, 28 S Source pads of the DMOS power transistor. 17, 18, 21, 22, 25, 26, 29, 30 D Drain pads of the DMOS power transistor. 31 TMON This is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By returning this pad to 12V the function is disabled. Returning this pad to ground will put the IC into the thermal shutdown state. Normally, this pad is left floating. Thermal shutdown occurs at a nominal junction temperature of +125oC. 32 PSEN This terminal is provided to activate the converter. This terminal may be left open or returned to 5V for normal operation. When the input is low, the DMOS driver is disabled. 33 SHRT 25µA is internally applied to this node when there is an over-current condition. 34 PSOK This pad provides a delayed positive indication when the supply is enabled. 35 VCMP Output of the transconductance amplifier. This node is used for both gain and frequency compensation of the loop. 36 VREG Input to the transconductance error amplifier is available on this pad. The other input is internally connected to the 5.1V reference, VINP, Pad 2. 37 FLTN This is an open drain output that remains low when V+ is too low for proper operation. This node and PSEN are useful in multiple converter configurations. This pad will be latched low when overtemperature, over-voltage or over-current is experienced. 5 DESCRIPTION HIP5060 Functional Block Diagram 12V REGULATOR V+ VREF = 5.1V 12V REGULATOR VREF PSEN PSOK SFST + - POWER SUPPLY OK VREF 1MHz CLOCK 50K MULTIPLEXER VDDP DRAIN 0.7µA S FLIP-FLOP R Q FAST RESET 900Ω gm AMP + - LOW LOAD 98KΩ 4KΩ FLTN GATE DRIVERS CONTROL AND BLANKING LOGIC + - 11.3KΩ + VDDP VDDA VREF 45KΩ VDDD BIAS CIRCUITS POWER SUPPLY ENABLE 360KΩ 140KΩ VINP VREG VDDA BAND GAP REFERENCE REGULATOR V+ MONITOR VDDP 20KΩ CKIO SLCT VDDA VREF CURRENT MONITORING AMP OVER VOLTAGE VREF TMON THERMAL MONITOR SHRT VREF 26KΩ + - SHORT - CIRCUIT + 13KΩ IRF0 6 VCMP DGD1 DGD2 AGND IRFI SOURCE