® N HIP5062 T ent UC OD lacem R E P Re p LET ded O n S O B m me o c e oR Power Control IC Single Chip Dual Switching Power Supply August 1998 File Number 3208.2 Features • • • • • • • • • • The HIP5062 is a complete power control IC, incorporating two high power DMOS transistors, CMOS logic and two low level analog control circuits on the same Intelligent Power IC. Both the standard “Boost” and the “SEPIC” (SingleEnded Primary Inductance Converter) power supply topologies are easily implemented with this single control IC. Special power transistor current sensing circuitry is incorporated that minimizes losses due to the monitoring circuitry. Moreover, over-temperature and over-voltage detection circuitry is incorporated within the IC to monitor the chip temperature and the actual power supply output voltage. These circuits can disable the drive to the power transistor to protect both the transistor and, most importantly, the load from over-voltage. Two Current Mode Control Regulators Two 60V, 5A On-chip DMOS Transistors Thermal Protection Over-Voltage Protection Over-Current Protection 1MHz Operation or External Clock Synchronization Output On-Chip Reference Voltage - 5.1V Output Rise and Fall Times ~ 3ns Designed for 26V to 42V Operation Applications • • • • As a result of the power DMOS transistor’s current and voltage capability (5A and 60V), multiple output power supplies with total output power capability up to 100W are possible. Single Chip Power Supplies Current Mode PWM Applications Distributed Power Supplies Multiple Output Converters Ordering Information TEMPERATURE RANGE PACKAGE HIP5062DY 0oC to +85oC 40 Pad Chip HIP5062DW 0oC to +85oC Wafer PART NUMBER (7) S2 (6) D2 (5) D2 (4) S2 (3) D2 (2) D2 (1) S2 Chip (8) VDDP2 (9) VCMP2 (10) PSOK (11) VREG2 (12) FLTN (13) PSEN (14) SHRT (15) SLRN (16) SFST (17) VDDD (18) VDDA (19) VREG1 (20) VDDP1 S1 (21) D1 (23) D1 (22) S1 (24) D1 (25) D1 (26) S1 (27) V+ (40) TMON (39) IRFI2 (38) IRFO2 (37) VINP (36) AGND (35) DGND (34) XCKS (33) CKIN (32) IRFI1 (31) IRFO1 (30) VCMP1 (29) VTCN (28) 175 mils x 175 mils (4.44mm x 4.44mm) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HIP5062 Simplified Block Diagram VIN 4µH 5µH 4µH 1.0µF 11µH 0.66µF 0.1µF 0.1µF VDDD 0.1 µF VDDP2 D2 S2 DGND VREG2 681Ω VDDP1 INTERNAL POWER SUPPLY AND REF VOLTAGE GATE DRIVERS 511Ω V+ CONTROL Q AND LOGIC CLOCK 0.1 µF D1 VDDP1 GATE DRIVERS S1 Q CONTROL AND LOGIC VREG1 IRFO1 IRFO2 IRFI1 IRFI2 VCMP1 VCMP2 VTCN TYPICAL SEPIC CONFIGURATION 2 SHRT SLRN SFST PSOK XCKS CKIN AGND VDDA VINP PSEN 4.7 µH FLTN 0.88 µF TMON 15 µF VDDD 12V 4.0 µH 1.0 µF 33 µF 5.1V HIP5062 Absolute Maximum Ratings Thermal Information DC Supply Voltage, V+. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 42V DMOS Drain Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V DMOS Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10A DC Logic Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Output Voltage, Logic Outputs . . . . . . . . . . . . . . . . . . . -0.3V to 16V Input Voltage, Analog and Logic. . . . . . . . . . . . . . . . . . -0.3V to 16V Operating Junction Temperature Range . . . . . . . . . .0oC to +110oC Storage Temperature Range . . . . . . . . . . . . . . . . . -55oC to +150oC Thermal Resistance θJC (Solder Mounted to . . . . . . . . . . . . . . . . . . . . . . . . . 3oC/W Max 0.050” Thick Copper Heat Sink) Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +110oC (Controlled By Thermal Shutdown Circuit) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications V+ = 36V, Channels 1 and 2, TJ = 0oC to +110oC; Unless Otherwise Specified SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - 24.7 30 mA DEVICE PARAMETERS I+ VDDA Supply Current V+ = 42V, PSEN = 12V Internal Regulator Output Voltage V+ = 30V to 42V, IOUT = 0mA 11.7 - 13.3 V V+ = 30V to 42V, IOUT = 30mA 11.5 - 13.3 V SLRN = 12V, IOUT = 0mA 11.5 - 13.3 V 5.01 5.1 5.19 V VINP Reference Voltage VDDA = SLRN = 12V, IVINP = 0mA RVINP VINP Resistance VINP = 0 - 900 - Ω Input Offset Voltage (REG - VINP) IVCMP = 0mA - - 10 mV RIN VREG Input Resistance to GND VREG = 5.1V 39 - 85 kΩ gm (VREG) VREG Transconductance (IVCMP/(VREG - VINP) VCMP = 1V to 8V, SFST = 11V 15 30 50 mS gm (SFST) SFST Transconductance IVCMP/(VREG - SFST) VSFST < 4.9V 0.8 - 6 mS IVCMP Maximum Source Current VREG = 4.95V, VCMP = 8V -2.5 - -0.75 mA Maximum Sink Current VREG = 5.25V, VCMP = 0.4V 0.75 - 2.5 mA Over-Voltage Threshold Voltage at VREG for FLTN to be latched 6.05 - 6.5 V Internal Clock Frequency XCKS = 12V, V DDD = 12V 0.9 1.0 1.1 MHz 33 - 66 %VDDD ERROR AMPLIFIERS | VIO | OVTH CLOCK fq V TH CKIN External Clock Input Threshold Voltages DMOS TRANSISTORS rDS(on) IDSS Drain-Source On-State Resistance I Drain = 2.5A, VDDD = 11V, TJ = +25oC - - 0.22 Ω Drain-Source Leakage Current Drain to Source Voltage = 60V - 1 100 µA IFRO = 0mA to -5mA, VTCN = 0.2V to 7.6V, VCMP2 = 0.2V to 7.6V - - 125 mV CURRENT CONTROLED PWM |VIO| VCMP Buffer Offset Voltage (VCOMP VIFRO) 3 HIP5062 Electrical Specifications V+ = 36V, Channels 1 and 2, TJ = 0oC to +110oC; Unless Otherwise Specified (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VTH IFRO Voltage at IRFO that disables PWM. This is due to low load current 116 - 250 mV ITH IFRO Voltage at IRFO to enable SHRT output current. This is due to Regulator Over Current Conditions 6.85 - 7.65 V ISHRT SHRT Output Current, During Over-Current VIRFO = 7.7V -75 - -33 µA VTH SHRT Threshold voltage on SHRT to set FLTN latch VDDD = 11V - 5 - V IGAIN IPEAK (DMOSDRAIN)/IIRFI ∆I (DMOSDRAIN)/∆t = 1A/ms 2.0 - 3.2 A/mA RIRFI IRFI Resistance to GND IIRFI = 2mA 150 - 360 Ω Current Comparator Response Time (Note 1) ∆I (DMOSDRAIN)/∆t > 1A/µs - 30 - ns tRS MCPW Minimum Controllable Pulse Width (Note 1) 25 50 100 ns MCPI Minimum Controllable DMOS Peak Current (Note 1) 125 250 500 mA Rising V+ Power-On Reset Voltage 23 - 26.3 V Falling V+ Power-Off Set Voltage - 15 - V V+ Power-On Hysteresis 9.5 - 11.8 V 3.6 - 6.5 V - 12 - KΩ -1.5 -1.0 -0.65 µA START-UP V+ VTH PSEN Voltage at PSEN to Enable Supply VDDD = 11V rPSEN Internal Pull-Up Resistance, to VDDD ISFST Soft-Start Charging Current VSFST = 0V to 11V IPSOK PSOK High-State Leakage Current SFST = 11V, PSOK = 12V -1 - 1 µA VPSOK PSOK Low-State Voltage SFST = 0V, IPSOK = 1mA - - 0.4 V PSOK Threshold, Rising V SFST VDDD = 11V 8.1 - 9.9 V TMON = 0V 105 - 135 oC VTH SFST THERMAL MONITOR TEMP Substrate Temperature for Thermal Monitor to Trip (Note 1) NOTE: 1. Determined by design, not a measured parameter. 4 HIP5062 Pin Descriptions PAD NUMBER DESIGNATION 1, 4, 7 S2 Source pads for the channel 2 regulator. 2, 3, 5, 6 D2 Drain pads for the channel 2 regulator. 8 VDDP2 This pad is the power input for the channel 2 DMOS gate driver and also is used to decouple the high current pulses to the output driver transistors. The decoupling capacitor should be at least a 0.1µF chip capacitor placed close to this pad and the DMOS source pads. 9 VCMP2 Output of the second channel transconductance amplifier. This node is used for both gain and frequency compensation of the loop. 10 PSOK 11 VREG2 12 FLTN This is an open drain output that remains low when V+ is too low for proper operation. This node and PSEN are useful in multiple converter configurations. This pad will be latched low when overtemperature, over-voltage or over-current is experienced. V+ must be powered down to reset. 13 PSEN This terminal is provided to activate the converter. When the input is low, the DMOS drivers are disabled. There is an internal 12K pull-up resistor on this terminal. 14 SHRT 50µA is internally applied to this node when there is an over-current condition. 15 SLRN Control input to internal regulator that is used during the “start-up” of the supply. In normal operation this terminal starts at 0V and shuts down the internal regulator at approximately 9V. This pad is usually connected to SFST, pad 16. 16 SFST Controls the rate of rise of both output voltages. Time is determined by an internal 1µA current source and an external capacitor. 17 V DDD Voltage input for the chip’s digital circuits. This pad also allows decoupling of this supply. 18 VDDA This is the analog supply and internal 12V regulator output usually used only during the start-up sequence. The internal regulator reduced to a nominal 9.2V when SLRN is returned to 12V. Output current capability is 30mA at both voltages. 19 VREG1 Input to channel one transconductance error amplifier. The other, common input for both amplifiers is VINP, pad 36. 20 VDDP1 This pad is the power input for the channel 1 DMOS gate driver and also is used to decouple the high current pulses to the output driver transistors. The decoupling capacitor should be at least a 0.1µF chip capacitor placed close to this pad and the DMOS source pads. 22, 23, 25, 26 D1 Drain pads for the channel 1 regulator. 21, 24, 27 S1 Source pads for the channel 1 regulator. 28 VTCN Input to transconductance amplifier buffer for channel 1 only. Normally connected to VCMP1, pad 29. 29 VCMP1 Output of the first channel transconductance amplifier. This node is used for both gain and frequency compensation of the loop. 30 IRFO1 A resistor placed between this pad and IRFI1 converts the VCMP1 signal to a current for the current sense comparator. The maximum current is set by the value of the resistor, according to the equation: IPEAK = 16/R. Where R is the value of the external resistor in KΩ and must be greater than 1.5KΩ but less than 10KΩ. For example, if the resistor chosen is 1.8K, the peak current will be 8.8A. This assumes VCMP1 is 7.3V. Maximum output current should be kept below 10A. 31 IRFI1 See IRFO1. 5 DESCRIPTION This pad provides delayed positive indication when both supplies are enabled. Input to the transconductance error amplifier. The other common input for both amplifiers is VINP, Pad 36. HIP5062 Pin Descriptions (Continued) PAD NUMBER DESIGNATION 32 CKIN Clock input when XCKS is grounded. 33 XCKS Grounding this terminal provides for the application of an external clock to CKIN input terminal. For normal internal clock operation, this terminal may be left floating or returned to 12V. There is an internal 30K pull-up resistor on this terminal. 34 DGND Ground of the DMOS gate drivers. This pad is used for bypassing. 35 AGND Analog ground. 36 VINP Internal 5.1V reference. This point is usually bypassed. 37 IRFO2 A resistor placed between this pad and IRFI2 converts the VCMP2 signal to a current for the current sense comparator. The maximum current set by the value of the resistor, according to the equation: IPEAK = 16/R. Where R is the value of the external resistor in KΩ and must be greater than 1.5KΩ but less than 10KΩ. For example, if the resistor chosen is 1.8K, the peak current will be 8.8A. This assumes VCMP2 is 7.3V. Maximum output current should be kept below 10A. 38 IRFI2 See IRFO2. 39 TMON This is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By returning this pad to VDDA or 12V the function is disabled. Returning this pad to ground will put the IC into the thermal shutdown state. Thermal shutdown occurs at a nominal junction temperature or +120oC. This terminal is normally returned to ground. 40 V+ This is the main supply voltage input pad to the regulator IC. Because of the high peak currents this pad must be well bypassed with at least a 0.1µF capacitor. 6 DESCRIPTION HIP5062 Functional Block Diagram VDDA SLRN BIAS CIRCUITS SFST PSOK FLTN XCKS VDDD VDDD 1 MHz CLOCK BAND GAP REF REG DRAIN 2 CKIN 30KΩ 12V REG VDDA VDDP2 V+ POWER SUPPLY OK V+ MONITOR VDDP1 MULTIPLEXER DRAIN 1 VREF = 5.1V S FLIP-FLOP R FAST RESET GATE DRIVERS S FLIP-FLOP Q R FAST RESET VDDA Q GATE DRIVERS 1µA SOURCE 2 CONTROL & BLANKING LOGIC CURRENT MONITORING AMP TO IRFI2 13.3KΩ 2KΩ VINP 900Ω TO IFRO1 VREF TO SFST OVER VOLTAGE - + - + SHORT CIRCUIT VREG2 31.3KΩ VDDD VREF SHRT 7 - IRFO1 + THERMAL MONITOR PSEN 11.3KΩ VTCN TO VINP TO SFST VCMP1 + VREF gm AMP 45KΩ + - VREG1 gm SD 12KΩ DGND 11.3KΩ VREG2 13.3KΩ gm AMP IRFI1 2KΩ 50µA TO SOURCE 1 + VREF 98KΩ 98KΩ VREF VCMP2 CURRENT MONITORING AMP - VDDA - + IRF02 LOW LOAD LOW LOAD + gm SD CONTROL & BLANKING LOGIC TMON AGND