74LVC1G3157-Q100 2-channel analog multiplexer/demultiplexer Rev. 3 — 31 May 2016 Product data sheet 1. General description The 74LVC1G3157-Q100 provides one analog multiplexer/demultiplexer with one digital select input (S), two independent inputs/outputs (Y0, Y1) and a common input/output (Z). Schmitt trigger action at the select input makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 1.65 V to 5.5 V. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V Very low ON resistance: 7.5 (typical) at VCC = 2.7 V 6.5 (typical) at VCC = 3.3 V 6 (typical) at VCC = 5 V Switch current capability of 32 mA Break-before-make switching High noise immunity CMOS low power consumption TTL interface compatibility at 3.3 V Latch-up performance meets requirements of JESD 78 Class I Control input accepts voltages up to 5.5 V Multiple package options ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version SOT363 74LVC1G3157GW-Q100 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads 40 C to +125 C SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 74LVC1G3157GV-Q100 4. Marking Table 2. Marking Type number Marking code[1] 74LVC1G3157GW-Q100 YJ 74LVC1G3157GV-Q100 YJ [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram < 6 = 6 < = < < DDF DDF Fig 1. Logic symbol 74LVC1G3157_Q100 Product data sheet Fig 2. Logic diagram All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 2 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning /9&*4 < 6 *1' 9&& < = DDD Fig 3. Pin configuration SOT363 and SOT457 6.2 Pin description Table 3. Pin description Symbol Pin Description Y1 1 independent input or output GND 2 ground (0 V) Y0 3 independent input or output Z 4 common output or input VCC 5 supply voltage S 6 select input 7. Functional description Table 4. Function table[1] Input S Channel on L Y0 H Y1 [1] H = HIGH voltage level; L = LOW voltage level. 74LVC1G3157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 3 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions [1] VI input voltage IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V ISK switch clamping current VI < 0.5 V or VI > VCC + 0.5 V [2] Min Max Unit 0.5 +6.5 V 0.5 +6.5 50 - mA - 50 mA 0.5 VCC + 0.5 V VSW switch voltage enable and disable mode ISW switch current VSW > 0.5 V or VSW < VCC + 0.5 V - 50 mA ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 250 mW total power dissipation Ptot Tamb = 40 C to +125 C [3] [1] The minimum input voltage rating may be exceeded if the input current rating is observed. [2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed. [3] For SC-88 and SC-74 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. V 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VSW Conditions switch voltage Tamb ambient temperature t/V input transition rise and fall rate Min Typ Max Unit 1.65 - 5.5 V 0 - 5.5 V 0 - VCC V C enable and disable mode [1] 40 - +125 VCC = 1.65 V to 2.7 V [2] - - 20 ns/V VCC = 2.7 V to 5.5 V [2] - - 10 ns/V [1] To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current flows from terminal Yn. In this case, there is no limit for the voltage drop across the switch. [2] Applies to control signal levels. 74LVC1G3157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 4 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter 40 C to +85 C Conditions Min HIGH-level input voltage VIH VCC = 1.65 V to 1.95 V LOW-level input voltage 40 C to +125 C Max Min Max Unit 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 3 V to 3.6 V 2.0 - - 2.0 - V 0.7VCC - - 0.7VCC - V VCC = 1.65 V to 1.95 V - - 0.35VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 3 V to 3.6 V - - 0.8 - 0.8 V 0.3VCC V VCC = 4.5 V to 5.5 V VIL Typ[1] VCC = 4.5 V to 5.5 V 0.35VCC V - - 0.3VCC [2] - 0.1 2 - 10 A [2] - 0.1 5 - 20 A [2] - 0.1 5 - 20 A II input leakage current pin S; VI = 5.5 V or GND; VCC = 0 V to 5.5 V IS(OFF) OFF-state leakage current VCC = 5.5 V; see Figure 4 IS(ON) ON-state leakage current VCC = 5.5 V; see Figure 5 ICC supply current VI = 5.5 V or GND; VSW = GND or VCC; VCC = 1.65 V to 5.5 V [2] - 0.1 10 - 40 A ICC additional pin S; VI = VCC 0.6 V; supply current VCC = 5.5 V; VSW = GND or VCC [2] - 5 500 - 5000 A CI input capacitance - 2.5 - - - pF CS(OFF) OFF-state capacitance - 6.0 - - - pF CS(ON) ON-state capacitance - 18 - - - pF [1] Typical values are measured at Tamb = 25 C. [2] These typical values are measured at VCC = 3.3 V 74LVC1G3157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 5 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 10.1 Test circuits 9&& 9,/RU9,+ 6 < = < VZLWFK VZLWFK 6 9,+ 9,/ ,6 92 9, *1' DDF VI = VCC or GND and VO = GND or VCC. Fig 4. Test circuit for measuring OFF-state leakage current 9&& 9,/RU9,+ ,6 6 < = < VZLWFK 6 9,+ 9,/ VZLWFK 9, 92 *1' DDF VI = VCC or GND and VO = open circuit. Fig 5. Test circuit for measuring ON-state leakage current 74LVC1G3157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 6 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 10.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 7 to Figure 12. Symbol RON(peak) RON(rail) Parameter ON resistance (peak) ON resistance (rail) 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max ISW = 4 mA; VCC = 1.65 V to 1.95 V - 34.0 130 - 195 ISW = 8 mA; VCC = 2.3 V to 2.7 V - 12.0 30 - 45 ISW = 12 mA; VCC = 2.7 V - 10.4 25 - 38 ISW = 24 mA; VCC = 3 V to 3.6 V - 7.8 20 - 30 ISW = 32 mA; VCC = 4.5 V to 5.5 V - 6.2 15 - 23 ISW = 4 mA; VCC = 1.65 V to 1.95 V - 8.2 18 - 27 ISW = 8 mA; VCC = 2.3 V to 2.7 V - 7.1 16 - 24 ISW = 12 mA; VCC = 2.7 V - 6.9 14 - 21 VI = GND to VCC; see Figure 6 VI = GND; see Figure 6 ISW = 24 mA; VCC = 3 V to 3.6 V - 6.5 12 - 18 ISW = 32 mA; VCC = 4.5 V to 5.5 V - 5.8 10 - 15 ISW = 4 mA; VCC = 1.65 V to 1.95 V - 10.4 30 - 45 ISW = 8 mA; VCC = 2.3 V to 2.7 V - 7.6 20 - 30 ISW = 12 mA; VCC = 2.7 V - 7.0 18 - 27 ISW = 24 mA; VCC = 3 V to 3.6 V - 6.1 15 - 23 - 4.9 10 - 15 ISW = 4 mA; VCC = 1.65 V to 1.95 V - 26.0 - - - VI = VCC; see Figure 6 ISW = 32 mA; VCC = 4.5 V to 5.5 V RON(flat) ON resistance (flatness) VI = GND to VCC [2] ISW = 8 mA; VCC = 2.3 V to 2.7 V - 5.0 - - - ISW = 12 mA; VCC = 2.7 V - 3.5 - - - ISW = 24 mA; VCC = 3 V to 3.6 V - 2.0 - - - ISW = 32 mA; VCC = 4.5 V to 5.5 V - 1.5 - - - [1] Typical values are measured at Tamb = 25 C and nominal VCC. [2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature. 74LVC1G3157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 7 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 10.3 ON resistance test circuit and graphs PQD 521 ȍ 96: 9 VZLWFK 9&& 9,/RU9,+ 6 < = < 9,/ 9,+ VZLWFK 6 ,6: 9, *1' RON = VSW / ISW. 9,9 DDF (1) VCC = 1.8 V. (2) VCC = 2.5 V. (3) VCC = 2.7 V. (4) VCC = 3.3 V. (5) VCC = 5.0 V. Fig 6. Test circuit for measuring ON resistance Fig 7. DDD Typical ON resistance as a function of input voltage; Tamb = 25 C DDD 521 ȍ 521 ȍ 9,9 (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (4) Tamb = 40 C. ON resistance as a function of input voltage; VCC = 1.8 V 74LVC1G3157_Q100 Product data sheet 9,9 (1) Tamb = 125 C. Fig 8. Fig 9. ON resistance as a function of input voltage; VCC = 2.5 V All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 8 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer DDD DDD 521 ȍ 521 ȍ 9,9 9,9 (1) Tamb = 125 C. (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (4) Tamb = 40 C. Fig 10. ON resistance as a function of input voltage; VCC = 2.7 V Fig 11. ON resistance as a function of input voltage; VCC = 3.3 V DDD 521 ȍ 9,9 (1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = 40 C. Fig 12. ON resistance as a function of input voltage; VCC = 5.0 V 74LVC1G3157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 9 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 11. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 16. Symbol Parameter tpd ten propagation delay enable time 40 C to +85 C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V - - 2 - 3.0 ns VCC = 2.3 V to 2.7 V - - 1.2 - 2.0 ns VCC = 2.7 V - - 1.0 - 1.5 ns VCC = 3 V to 3.6 V - - 0.8 - 1.5 ns VCC = 4.5 V to 5.5 V - - 0.6 - 1.0 ns 3.1 8.7 20.8 3.1 22.0 ns Z to Yn or Yn to Z; see Figure 13 S to Yn; see Figure 14 [2][3] [4] VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 2.2 5.3 11.5 2.2 12.5 ns VCC = 2.7 V 2.1 4.9 9.3 2.1 10.2 ns VCC = 3 V to 3.6 V 1.8 4.0 7.6 1.8 9.0 ns 1.5 3.0 5.7 1.5 6.1 ns VCC = 1.65 V to 1.95 V 3.0 6.0 11.4 3.0 11.7 ns VCC = 2.3 V to 2.7 V 2.1 4.4 7.3 2.1 7.6 ns VCC = 2.7 V 2.1 4.2 6.3 2.1 6.6 ns VCC = 3 V to 3.6 V 1.7 3.6 5.3 1.7 5.9 ns VCC = 4.5 V to 5.5 V 1.3 2.9 3.8 1.3 4.3 ns 0.5 - - 0.5 - ns VCC = 4.5 V to 5.5 V tdis tb-m disable time break-before-make time 40 C to +125 C Unit Typ[1] S to Yn; see Figure 14 [5] [6] see Figure 15 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 0.5 - - 0.5 - ns VCC = 2.7 V 0.5 - - 0.5 - ns VCC = 3 V to 3.6 V 0.5 - - 0.5 - ns VCC = 4.5 V to 5.5 V 0.5 - - 0.5 - ns [1] Typical values are measured at Tamb = 25 C and nominal VCC. [2] tpd is the same as tPLH and tPHL. [3] Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when driven by an ideal voltage source (zero output impedance). [4] ten is the same as tPZH and tPZL. [5] tdis is the same as tPLZ and tPHZ. [6] Break-before-make specified by design. 74LVC1G3157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 10 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 11.1 Waveforms and test circuits 9, <QRU= LQSXW 90 90 *1' W3/+ W3+/ 92+ =RU<Q RXWSXW 90 90 92/ DDF Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 13. Input (Yn or Z) to output (Z or Yn) propagation delays 9, 6LQSXW 90 *1' W3=/ W3/= 9&& <Q RXWSXW /2:WR2)) 2))WR/2: 90 9; 92/ W3=+ W3+= 92+ <Q RXWSXW +,*+WR2)) 2))WR+,*+ 9< 90 *1' VZLWFK HQDEOHG VZLWFK GLVDEOHG VZLWFK HQDEOHG DDF Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 14. Enable and disable times Table 10. Measurement points Supply voltage Input Output VCC VM VM VX VY 1.65 V to 5.5 V 0.5 VCC 0.5 VCC VOL + 0.3 V VOH 0.3 V 74LVC1G3157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 11 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 9&& 9, * 92 5/ 9&& 6 < = < &/ *1' DDF a. Test circuit 9, 9, 92 92 92 WEP DDJ b. Input and output measurement points Fig 15. Test circuit for measuring break-before-make timing 9(;7 9&& * 9, 5/ 92 '87 57 &/ 5/ PQD Test data is given in Table 11. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. VEXT = External voltage for measuring switching times. Fig 16. Test circuit for measuring switching times 74LVC1G3157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 12 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer Table 11. Test data Supply voltage Input Load VEXT VCC VI tr, tf CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC 2.0 ns 50 pF 500 open GND 2 VCC 2.3 V to 2.7 V VCC 2.0 ns 50 pF 500 open GND 2 VCC 2.7 V VCC 2.5 ns 50 pF 500 open GND 2 VCC 3 V to 3.6 V VCC 2.5 ns 50 pF 500 open GND 2 VCC 4.5 V to 5.5 V VCC 2.5 ns 50 pF 500 open GND 2 VCC 11.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol Parameter Conditions THD total harmonic distortion fi = 600 Hz to 20 kHz; RL = 600 ; CL = 50 pF; VI = 0.5 V (p-p); see Figure 17 f(3dB) iso Qinj 3 dB frequency response isolation (OFF-state) charge injection 74LVC1G3157_Q100 Product data sheet Min Typ Max Unit VCC = 1.65 V - 0.260 - % VCC = 2.3 V - 0.078 - % VCC = 3.0 V - 0.078 - % VCC = 4.5 V - 0.078 - % VCC = 1.65 V - 200 - MHz VCC = 2.3 V - 300 - MHz VCC = 3.0 V - 300 - MHz VCC = 4.5 V - 300 - MHz VCC = 1.65 V - 42 - dB VCC = 2.3 V - 42 - dB VCC = 3.0 V - 40 - dB VCC = 4.5 V - 40 - dB VCC = 1.8 V - 3.3 - pC VCC = 2.5 V - 4.1 - pC VCC = 3.3 V - 5.0 - pC VCC = 4.5 V - 6.4 - pC VCC = 5.5 V - 7.5 - pC RL = 50 ; see Figure 18 RL = 50 ; CL = 5 pF; fi = 10 MHz; see Figure 19 CL = 0.1 nF; Vgen = 0 V; Rgen = 0 ; fi = 1 MHz; RL = 1 M; see Figure 20 All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 13 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 11.3 Test circuits 9&& 9,/RU9,+ IL ) 9&& 6 < = < 5/ ) VZLWFK 6 9,/ 9,+ ' &/ ȍ VZLWFK *1' DDF Fig 17. Test circuit for measuring total harmonic distortion 9&& 9,/RU9,+ '&ELDV P9 IL ) 6 < = < VZLWFK 6 9,/ 9,+ VZLWFK 5/ ȍ G% *1' DDD To obtain 0 dBm level at input, adjust fi voltage. Increase fi frequency until dB meter reads 3 dB. Fig 18. Test circuit for measuring the frequency response when switch is in ON-state 9&& 9&& 9&& 5/ 9,/RU9,+ IL ) 5/ 6 < = < VZLWFK &/ ȍ VZLWFK 6 9,+ 9,/ G% *1' DDF To obtain 0 dBm level at input, adjust fi voltage Fig 19. Test circuit for measuring isolation (OFF-state) 74LVC1G3157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 14 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 9&& * 6 < = < VZLWFK 5JHQ 9, 5/ &/ 92 9JHQ *1' DDD a. Test circuit ORJLF 6 RII LQSXW RQ 92 RII ǻ92 DDF b. Input and output pulse definitions Qinj = VO CL. VO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage. Fig 20. Test circuit for measuring charge injection 74LVC1G3157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 15 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 12. Package outline 3ODVWLFVXUIDFHPRXQWHGSDFNDJHOHDGV 627 ' % $ ( \ ; +( Y 0 $ 4 SLQ LQGH[ $ $ H ES F /S Z 0 % H GHWDLO; PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ $ PD[ ES F ' ( H H +( /S 4 Y Z \ PP 287/,1( 9(56,21 5()(5(1&(6 ,(& -('(& -(,7$ 6& 627 (8523($1 352-(&7,21 ,668('$7( Fig 21. Package outline SOT363 (SC-88) 74LVC1G3157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 16 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 3ODVWLFVXUIDFHPRXQWHGSDFNDJH7623OHDGV ' 627 % $ ( \ +( ; Y 0 $ 4 SLQ LQGH[ $ $ F /S H ES Z 0 % GHWDLO; PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ $ ES F ' ( H +( /S 4 Y Z \ PP 287/,1( 9(56,21 5()(5(1&(6 ,(& -('(& -(,7$ 6& 627 (8523($1 352-(&7,21 ,668('$7( Fig 22. Package outline SOT457 (SC-74) 74LVC1G3157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 17 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 13. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor TTL Transistor-Transistor Logic HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model MIL Military DUT Device Under Test 14. Revision history Table 14. Revision history Document ID Release date 74LVC1G3157_Q100 v.3 20160531 Modifications: • • • • Product data sheet Supersedes - 74LVC1G3157_Q100 v.2 Table 12 and Figure 18: Condition and test circuit for f(-3dB) revised. Figure 20: Test circuit for charge injection revised. Product data sheet - 74LVC1G3157_Q100 v.1 Type number 74LVC1G3157GM-Q100 has been removed. 74LVC1G3157_Q100 v.1 20130219 74LVC1G3157_Q100 Change notice Product data sheet Table 9: Minimum and maximum values enable and disable times revised. 74LVC1G3157_Q100 v.2 20130410 Modifications: Data sheet status Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 - © NXP Semiconductors N.V. 2016. All rights reserved. 18 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC1G3157_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 19 of 21 74LVC1G3157-Q100 NXP Semiconductors 2-channel analog multiplexer/demultiplexer No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC1G3157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 20 of 21 NXP Semiconductors 74LVC1G3157-Q100 2-channel analog multiplexer/demultiplexer 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ON resistance test circuit and graphs. . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms and test circuits . . . . . . . . . . . . . . 11 Additional dynamic characteristics . . . . . . . . . 13 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2016. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 31 May 2016 Document identifier: 74LVC1G3157_Q100