HEF4518B
Dual BCD counter
Rev. 8 — 19 April 2016
Product data sheet
1. General description
The HEF4518B is a dual 4-bit internally synchronous BCD counter. The counter has an
active HIGH clock input (nCP0) and an active LOW clock input (nCP1), buffered outputs
from all four bit positions (nQ0 to nQ3) and an active HIGH overriding asynchronous
master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of
the nCP0 input if nCP1 is HIGH or the HIGH-to-LOW transition of the nCP1 input if nCP0
is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter and the other
clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0
to nQ3 = LOW) independent of nCP0, nCP1. Schmitt trigger action in the clock input
makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Multistage synchronous counting
Multistage asynchronous counting
Frequency dividers
4. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +85 C
Type number
HEF4518BT
Package
Name
Description
Version
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
HEF4518B
NXP Semiconductors
Dual BCD counter
5. Functional diagram
4 &3
4 &3
4 4 05
4 &3
4 &3
4 4 05
DDH
Fig 1.
Functional diagram
4
4
4
&3
&3
4
4
))
4
))
7
7
&' 4
4
))
7
&' 4
4
))
7
&' 4
&' 4
05
DDH
Fig 2.
Logic diagram for one counter
HEF4518B
Product data sheet
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Rev. 8 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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HEF4518B
NXP Semiconductors
Dual BCD counter
6. Pinning information
6.1 Pinning
+()%
&3 9''
&3 05
4 4
4 4
4 4
4 4
05 &3
966 &3
DDH
Fig 3.
Pin configuration
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1CP0, 2CP0
1, 9
clock input (LOW-to-HIGH triggered)
1CP1, 2CP1
2, 10
clock input (HIGH-to-LOW triggered)
1Q0, 2Q0
3, 11
output
1Q1, 2Q1
4, 12
output
1Q2, 2Q2
5, 13
output
1Q3, 2Q3
6, 14
output
1MR, 2MR
7, 15
master reset input
VDD
16
supply voltage
VSS
8
ground supply voltage
HEF4518B
Product data sheet
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Rev. 8 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 14
HEF4518B
NXP Semiconductors
Dual BCD counter
7. Functional description
Table 3.
Function table[1]
nCP0
nCP1
nMR
Mode
H
L
counter advances
L
L
counter advances
X
L
no change
X
L
no change
L
L
no change
H
L
no change
X
X
H
nQ0 to nQ3 = LOW
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; = positive-going transition; = negative-going transition.
Q&3
Q&3
Q05
Q4
Q4
Q4
Q4
DDH
Fig 4.
Timing diagram
HEF4518B
Product data sheet
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Rev. 8 — 19 April 2016
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HEF4518B
NXP Semiconductors
Dual BCD counter
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDD
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
II/O
input/output current
IDD
supply current
Tstg
storage temperature
Tamb
ambient temperature
Max
Unit
0.5
+18
V
mA
VI < 0.5 V or VI > VDD + 0.5 V
-
10
0.5
VDD + 0.5
-
10
mA
-
10
mA
VO < 0.5 V or VO > VDD + 0.5 V
Ptot
total power dissipation
SO16 package
P
power dissipation
per output
[1]
Min
V
-
50
mA
65
+150
C
40
+85
C
-
500
mW
-
100
mW
[1]
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Min
Typ
Max
VDD
supply voltage
Conditions
3
-
15
V
Unit
VI
input voltage
0
-
VDD
V
Tamb
ambient temperature
in free air
40
-
+85
C
t/V
input transition rise and fall rate
VDD = 5 V
-
-
3.75
s/V
VDD = 10 V
-
-
0.5
s/V
VDD = 15 V
-
-
0.08
s/V
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
VIH
VIL
VOH
HIGH-level input voltage
LOW-level input voltage
Product data sheet
Tamb = 25 C
Tamb = 85 C
Max
Min
Max
Min
Max
-
3.5
-
3.5
-
V
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
V
5V
4.95
-
4.95
-
4.95
-
V
VDD
Min
IO < 1 A
5V
3.5
10 V
IO < 1 A
HIGH-level output voltage IO < 1 A
HEF4518B
Tamb = 40 C
Conditions
Unit
10 V
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
V
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Rev. 8 — 19 April 2016
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HEF4518B
NXP Semiconductors
Dual BCD counter
Table 6.
Static characteristics …continued
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
VOL
IOH
IOL
Conditions
Tamb = 40 C
VDD
Tamb = 25 C
Tamb = 85 C
Unit
Min
Max
Min
Max
Min
Max
5V
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
V
HIGH-level output current VO = 2.5 V
5V
-
1.7
-
1.4
-
1.1
mA
VO = 4.6 V
5V
-
0.52
-
0.44
-
0.36 mA
VO = 9.5 V
10 V
-
1.3
-
1.1
-
0.9
mA
VO = 13.5 V
15 V
-
3.6
-
3.0
-
2.4
mA
VO = 0.4 V
5V
0.52
-
0.5
-
0.36
-
mA
VO = 0.5 V
10 V
1.3
-
1.1
-
0.9
-
mA
LOW-level output voltage
LOW-level output current
IO < 1 A
VO = 1.5 V
15 V
3.6
-
3.0
-
2.4
-
mA
II
input leakage current
VDD = 15 V
15 V
-
0.3
-
0.3
-
1.0
A
IDD
supply current
IO = 0 A
5V
-
20
-
20
-
150
A
10 V
-
40
-
40
-
300
A
15 V
-
80
-
80
-
600
A
-
-
-
-
7.5
-
-
pF
CI
input capacitance
11. Dynamic characteristics
Table 7.
Dynamic characteristics
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 6; unless otherwise specified.
Symbol
tPHL
Parameter
HIGH to LOW
propagation delay
Conditions
VDD
Extrapolation formula
Min
Typ
Max
Unit
93 ns + (0.55 ns/pF)CL
-
120
240
ns
10 V
44 ns + (0.23 ns/pF)CL
-
55
110
ns
15 V
32 ns + (0.16 ns/pF)CL
-
40
80
ns
nMR to nQn;
see Figure 5
5V
48 ns + (0.55 ns/pF)CL
-
75
150
ns
10 V
24 ns + (0.23 ns/pF)CL
-
35
70
ns
nCP0, nCP1 to nQn;
see Figure 5
5V
nCP0, nCP1 to nQn;
see Figure 5
5V
[1]
15 V
tPLH
LOW to HIGH
propagation delay
[1]
10 V
15 V
tt
transition time
HEF4518B
Product data sheet
nQn; see Figure 5
5V
[1]
17 ns + (0.16 ns/pF)CL
-
25
50
ns
93 ns + (0.55 ns/pF)CL
-
120
240
ns
44 ns + (0.23 ns/pF)CL
-
55
110
ns
32 ns + (0.16 ns/pF)CL
-
40
80
ns
10 ns + (1.00 ns/pF)CL
-
60
120
ns
10 V
9 ns + (0.42 ns/pF)CL
-
30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
-
20
40
ns
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Rev. 8 — 19 April 2016
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HEF4518B
NXP Semiconductors
Dual BCD counter
Table 7.
Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 6; unless otherwise specified.
Symbol
Parameter
Conditions
VDD
tW
pulse width
nCP0 input LOW;
minimum width;
see Figure 5
nCP1 input HIGH;
minimum width;
see Figure 5
nMR input HIGH;
minimum width;
see Figure 5
recovery time
trec
set-up time
tsu
maximum
frequency
[1]
Min
Typ
Max
5V
60
30
-
ns
10 V
30
15
-
ns
15 V
20
10
-
ns
5V
60
30
-
ns
10 V
30
15
-
ns
15 V
20
10
-
ns
5V
30
15
-
ns
10 V
20
10
-
ns
15 V
16
8
-
ns
50
25
-
ns
10 V
30
15
-
ns
15 V
20
10
-
ns
5V
50
25
-
ns
10 V
30
15
-
ns
15 V
20
10
-
ns
5V
50
25
-
ns
10 V
30
15
-
ns
15 V
20
10
-
ns
5V
8
16
-
MHz
10 V
15
30
-
MHz
15 V
20
40
-
MHz
nMR input; see Figure 5 5 V
nCP0 to nCP1;
see Figure 5
nCP1 to nCP0;
see Figure 5
fmax
Extrapolation formula
nCP0, nCP1;
see Figure 5
Unit
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
PD
Parameter
dynamic power
dissipation
VDD
Typical formula for PD (W)
Where:
5V
PD = 750 fi + (fo CL) VDD
10 V
PD = 3300 fi + (fo CL) VDD2
fo = output frequency in MHz;
15 V
PD = 8000 fi + (fo CL) VDD
CL = output load capacitance in pF;
2
fi = input frequency in MHz;
2
VDD = supply voltage in V;
(fo CL) = sum of the outputs.
HEF4518B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
7 of 14
HEF4518B
NXP Semiconductors
Dual BCD counter
12. Waveforms
9,
90
Q&3LQSXW
9
9,
Q&3LQSXW
90
9
9
WVX
WVX
9,
Q05LQSXW
90
9
W3+/
Q4QRXWSXW
W3+/
W3/+
92+
90
92/
WW
WW
DDH
a. nCP0 and nCP1 set-up times, propagation delays and output transition times
IPD[
9,
Q&3LQSXW
Q&3 /2:
90
9
W:
9,
Q&3LQSXW
Q&3 +,*+
90
9
W:
9,
90
Q05LQSXW
9
W:
WUHF
DDH
b. nMR recovery time, minimum nCP0, nCP1, and nMR pulse widths and maximum frequency
Measurement points are given in table Table 9.
The logic levels VOH and VOL are typical output voltage levels that occur with the output load.
Fig 5.
Waveforms showing measurements for switching times
HEF4518B
Product data sheet
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Rev. 8 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
8 of 14
HEF4518B
NXP Semiconductors
Dual BCD counter
W:
9,
QHJDWLYH
SXOVH
90
90
9
WI
WU
WU
WI
9,
SRVLWLYH
SXOVH
90
90
9
W:
DDM
a. Input waveforms
9''
*
9,
92
'87
57
&/
DDJ
b. Test circuit
Test data is given in Table 9.
Definitions for test circuit:
DUT = Device Under Test;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 6.
Test circuit for switching times
Table 9.
Measurement points and test data
Supply voltage
Input
VDD
VI
VM
tr, tf
CL
5 V to 15 V
VDD
0.5VI
20 ns
50 pF
HEF4518B
Product data sheet
Load
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Rev. 8 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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HEF4518B
NXP Semiconductors
Dual BCD counter
13. Package outline
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Package outline SOT109-1 (SO16)
HEF4518B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
10 of 14
HEF4518B
NXP Semiconductors
Dual BCD counter
14. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4518B v.8
20160419
Product data sheet
-
HEF4518B v.7
Modifications:
HEF4518B v.7
Modifications:
•
Type number HEF4518BP (SOT38-4) removed.
20111121
•
•
Product data sheet
-
HEF4518B v.6
Table 6: IOH minimum values changed to maximum
Figure 6: added “DUT = Device Under Test”
HEF4518B v.6
20091210
Product data sheet
-
HEF4518B v.5
HEF4518B v.5
20090727
Product data sheet
-
HEF4518B v.4
HEF4518B v.4
20090703
Product data sheet
-
HEF4518B_CNV v.3
HEF4518B_CNV v.3
19950101
Product specification
-
HEF4518B_CNV v.2
HEF4518B_CNV v.2
19950101
Product specification
-
-
HEF4518B
Product data sheet
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Rev. 8 — 19 April 2016
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NXP Semiconductors
Dual BCD counter
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
HEF4518B
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
12 of 14
HEF4518B
NXP Semiconductors
Dual BCD counter
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
HEF4518B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
13 of 14
HEF4518B
NXP Semiconductors
Dual BCD counter
17. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 19 April 2016
Document identifier: HEF4518B