Data Sheet

Freescale Semiconductor
Technical Data
Document Number: MC33879
Rev. 11.0, 11/2015
Configurable Octal Serial Switch with
Open Load Detect Current Disable
33879
33879A
The 33879 device is an 8-output hardware configurable, high-side/low-side
switch with 16-bit serial input control using the serial peripheral interface (SPI).
Two of the outputs may be controlled directly via a microcontroller for pulsewidth modulation (PWM) applications. The 33879 incorporates SMARTMOS
technology, with CMOS logic, bipolar/MOS analog circuitry, and DMOS power
MOSFETs. The 33879 controls various inductive, incandescent, or LED loads by
directly interfacing with a microcontroller. The circuit’s innovative monitoring and
protection features include very low standby currents, cascade fault reporting,
internal + 45 V clamp voltage for low-side configuration, - 20 V high-side
configuration, output specific diagnostics, and independent overtemperature
protection.
HIGH-SIDE/ LOW-SIDE SWITCH
Features
•
•
•
•
•
•
•
•
•
•
•
Designed to operate 5.5 V < VPWR < 27.5 V
16-bit SPI for control and fault reporting, 3.3 V / 5.0 V compatible
Outputs are current limited (0.6 to 1.2 A) to drive incandescent lamps
Output voltage clamp, + 45 V (low-side) and - 20 V (high-side) during
inductive switching
On/Off control of open load detect current (LED application)
Internal reverse battery protection on VPWR
Loss of ground or supply will not energize loads or damage IC
Maximum 5.0 μA IPWR standby current at 13 V VPWR
RDS(ON) of 0.75 Ω at 25 °C typical
Short-circuit detect and current limit with automatic retry
Independent overtemperature protection
VPWR
•
•
•
•
•
•
Solenoids
Relays
Actuators
Stepper motors
Brush DC motors
Incandescent lamps
33879
VPWR
VDD
MCU
A0
Applications
VBAT
5.0 V
MOSI
SCLK
CS
MISO
PWM1
PWM2
EK SUFFIX (PB-FREE)
98ARL10543D
32-PIN SOICW
EN
DI
SCLK
CS
D0
IN5
IN6
GND
D1
D2
D3
D4
S1
S2
S3
S4
High-side Drive
M
D5
D6
D7
D8
S5
S6
S7
S8
H-Bridge Configuration
VBAT VBAT
Low-side Drive
Figure 1. 33879 Simplified Application Diagram
© Freescale Semiconductor, Inc., 2009-2015. All rights reserved.
1
Orderable Parts
Table 1. Orderable Part Variations
Part Number (1)
MC33879APEK
MC33879TEK
Temperature (TA)
Package
-40 to 125 °C
32 SOICW-EP
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
Table 2. Device Variations
Symbol
VPWR
Characteristic
VPWR Supply Voltage
• 33879
• 33879A
Min
Typ
Max
Unit
-16
-16
–
–
40
45
V
35
35
55
55
90
150
65
60
100
100
160
190
40
40
75
75
135
150
20
20
45
45
100
110
2.5
2.5
4.0
4.0
4.5
5.0
20
20
30
30
60
115
Output Fault Detection Current @ Threshold, High-side Configuration
IOUT(FLT-TH)
Outputs Programmed OFF
• 33879
• 33879A
μA
Output OFF Open Load Detection Current, High-side Configuration
VDRAIN = 16 V, VSOURCE = 0 V, Outputs Programmed OFF,
IOCO
VPWR = 16 V
• 33879
• 33879A
μA
Output OFF Open Load Detection Current, Low-side Configuration
VDRAIN = 16 V, VSOURCE = 0 V, Outputs Programmed OFF,
IOCO
VPWR =16 V
• 333879
• 338979A
μA
EN Pull-down Current
I EN
EN = 5.0 V
• 333879
• 33879A
μA
Output Fault Detection Voltage Threshold
VOUT(FLT-TH)
Outputs Programmed OFF
• 33879
• 33879A
V
Output Fault Detection Current @ Threshold, Low-side Configuration
IOUT(FLT-TH)
Outputs Programmed OFF
• 33879
• 33879A
μA
33879
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
Internal Block Diagram
VDD
__
VPWR
~50 μA
CS
Internal
Bias
Power Supply
SCLK
Charge
Pump
Overvoltage
Shutdown/POR
Sleep State
DI
GND
DO
EN
~110 kΩ
OV, POR, SLEEP
SPI and
Interface
Logic
Typical of all 8 output drivers
SPI Bit 0
IN5
Enable
~50 μA
SPI Bit 4
IN5
IN6
D1
D2
TLIM
Open
Load
Detect
Current
~80 μA
Gate
Drive
Control
Current
Limit
+
‚
~50 μA
+
‚
Open/Short
Comparator
+
D3
D4
D7
D8
S1
S2
S3
S4
S7
S8
‚
~4.0 V Open/Short
Threshold
D5
Open
Load
Detect
Current
~80 μA
TLIM
EP
Exposed Pad
Gate
Drive
Control
Current
Limit
+
‚
+
‚
Open/Short
Comparator
D6
S5
S6
+
Drain
Outputs
Source
Outputs
Drain
Outputs
Source
Outputs
‚
~4.0 V Open/Short
Threshold
Figure 2. 33879 Simplified Internal Block Diagram
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
3
Pin Connections
3.1
Pinout Diagram
GND
VDD
S8
NC
D8
S2
D2
NC
NC
S1
D1
D6
S6
IN6
EN
SCLK
9
24
10
23
11
22
12
21
13
20
14
19
DO
VPWR
NC
S7
D7
S4
D4
NC
NC
S3
D3
D5
S5
IN5
15
18
CS
16
17
DI
1
32
2
31
3
30
4
29
5
28
6
27
7
8
26
GND
25
Figure 3. 33879 Pin Connections
3.2
Pin Definitions
A functional description of each pin can be found in 5.1, Functional Pin Description, page 14.
Table 3. 33879 Pin Definitions
Pin Number
Pin Name
Pin
Function
Formal Name
1
GND
Ground
Ground
2
Definition
Digital ground.
VDD
Input
3
S8
Output
Logic Supply Voltage Logic supply for SPI interface. With VDD low the device is in Sleep mode.
Source Output 8
4, 8, 9, 24,
25, 30
NC
No
Connection
Not Connected
No internal connection to this pin.
5
D8
Output
Drain Output 8
Output 8 MOSFET drain pin.
6
S2
Output
Source Output 2
Output 8 MOSFET source pin.
Output 2 MOSFET source pin.
7
D2
Output
Drain Output 2
10
S1
Output
Source Output 1
Output 2 MOSFET drain pin.
11
D1
Output
Drain Output 1
Output 1 MOSFET drain pin.
12
D6
Output
Drain Output 6
Output 6 MOSFET drain pin.
13
S6
Output
Source Output 6
14
IN6
Input
Command Input 6
PWM direct control input pin for output 6. IN6 is “OR” with SPI bit.
15
EN
Input
Enable Input
IC Enable. Active high. With EN low, the device is in Sleep mode.
16
SCLK
Clock
SPI Clock
17
DI
Input
Serial Data Input
SPI control data input pin from MCU to the 33879. Logic [1] activates output.
18
CS
Input
SPI Chip Select
SPI control chip select input pin from MCU to the 33879. Logic [0] allows data to be
transferred in.
19
IN5
Input
Command Input 5
20
S5
Output
Source Output 5
Output 1 MOSFET source pin.
Output 6 MOSFET source pin.
SPI control clock input pin.
PWM direct control input pin for output 5. IN5 is “OR” with SPI bit.
Output 5 MOSFET source pin.
33879
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 3. 33879 Pin Definitions (continued)
Pin Number
Pin Name
Pin
Function
Formal Name
21
D5
Output
Drain Output 5
Output 5 MOSFET drain pin.
22
D3
Output
Drain Output 3
Output 3 MOSFET drain pin.
23
S3
Output
Source Output 3
26
D4
Output
Drain Output 4
27
S4
Output
Source Output 4
28
D7
Output
Drain Output 7
29
S7
Output
Source Output 7
31
VPWR
Input
Battery Input
32
DO
Output
Serial Data Output
SPI control data output pin from the 33879 to the MCU. DO = 0 no fault, DO = 1 specific
output has fault.
33
EP
Ground
Exposed Pad
Device performs as specified with the Exposed Pad un-terminated (floating) however,
it is recommended the exposed pad be terminated to pin 1 (GND) and system ground.
Definition
Output 3 MOSFET source pin.
Output 4 MOSFET drain pin.
Output 4 MOSFET source pin.
Output 7 MOSFET drain pin.
Output 7 MOSFET source pin.
Power supply pin to the 33879. VPWR has internal reverse battery protection.
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
4
Electrical Characteristics
4.1
Maximum Ratings
Table 4. 33879 Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Ratings
Value
Unit
Notes
VDD Supply Voltage
- 0.3 to 7.0
VDC
(1)
CS, DI, DO, SCLK, IN5, IN6, and EN
- 0.3 to 7.0
VDC
(1)
ELECTRICAL RATINGS
VDD
–
VPWR
VPWR Supply Voltage
• 33879
• 33879A
-16 to 40
-16 to 45
VDC
(1)
ECLAMP
Output Clamp Energy
50
mJ
(2)
V
(3)
VESD1
VESD2
VESD1
VESD2
ESD Voltage
• Human Body Model 33879
• Machine Model 33879
• Human Body Model 33879A
• Machine Model 33879A
± 450
±100
±2000
±200
THERMAL RATINGS
Operating Temperature
• Ambient
• Junction
• Case
- 40 to 125
- 40 to 150
- 40 to 125
°C
Storage Temperature
- 55 to 150
°C
Power Dissipation
1.7
W
RθJA
RθJC
Thermal Resistance
• Junction to Ambient
• Between the Die and the Exposed Die Pad
71
1.2
°C/W
TPPRT
Peak Package Reflow Temperature During Reflow
Note 6
°C
TA
TJ
TC
TSTG
PD
(4)
(5), (6)
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. Maximum output clamp energy capability at 150°C junction temperature using single non-repetitive pulse method with I = 350 mA.
3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance
with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
4.
Maximum power dissipation at TA = 25 °C with no heatsink used.
5.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature
and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to
view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
6.
33879
6
Analog Integrated Circuit Device Data
Freescale Semiconductor
4.2
StatiC Electrical Characteristics
Table 5. Static Electrical Characteristics
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, - 40 °C ≤ TC ≤ 125 °C, unless otherwise noted. Where
applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 °C.
Symbol
Characteristic
Min
Typ
Max
Unit
5.5
5.5
–
–
26.5
27.5
V
Notes
POWER INPUT
VPWR (FO)
Supply Voltage Range
• Fully Operational 33879
• 33879A
IPWR (ON)
Supply Current
–
14
24
mA
IPWR (SS)
Sleep State Supply Current
• VDD or EN ≤ 0.8 V, VPWR = 13 V
–
2.0
5.0
μA
IVDD (SS)
Sleep State Supply Current
• EN ≤ 0.8 V, VDD = 5.5 V
–
2.0
5.0
μA
VPWR(OV)
VPWR Overvoltage Shutdown Threshold Voltage
• 33879
• 33879A
27
28
28.5
30
32
33
V
VPWR(OV-HYS)
VPWR Overvoltage Shutdown Hysteresis Voltage
0.2
1.5
2.5
V
VPWR(UV)
VPWR Undervoltage Shutdown Threshold Voltage
3.0
4.0
5.0
V
VPWR(UV-HYS)
VPWR Undervoltage Shutdown Hysteresis Voltage
300
500
700
mV
VDD
Logic Supply Voltage
3.1
–
5.5
V
IDD
Logic Supply Current
250
400
700
μA
Logic Supply Sleep State Threshold Voltage
0.8
2.5
3.0
V
–
–
–
–
0.75
–
1.4
–
–
VDD(SS)
POWER OUTPUT
Drain-to-Source ON Resistance (IOUT = 0.350 A, VPWR = 13 V)
RDS (on)
• TJ = 125°C
TJ = 25°C
TJ = -40°C
Ω
IOUT (LIM)
Output Self Limiting Current High-side and Low-side Configurations
0.6
–
1.2
A
VOUT(FLT-TH)
Output Fault Detection Voltage Threshold Outputs Programmed OFF
• 33879
• 33879A
2.5
2.5
4.0
4.0
4.5
5.0
V
IOUT(FLT-TH)
Output Fault Detection Current @ Threshold, High-side Configuration
Outputs Programmed OFF
• 33879
• 33879A
35
35
55
55
90
150
IOUT(FLT-TH)
Output Fault Detection Current @ Threshold, Low-side Configuration
Outputs Programmed OFF
• 33879
• 33879A
20
20
30
30
60
115
65
60
100
100
160
190
IOCO
Output OFF Open Load Detection Current, High-side Configuration
• VDRAIN = 16 V, VSOURCE = 0 V, Outputs Programmed OFF,
VPWR = 16 V
33879
33879A
(7)
μA
μA
μA
Notes
7. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts.
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, - 40 °C ≤ TC ≤ 125 °C, unless otherwise noted. Where
applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 °C.
Symbol
Characteristic
Min
Typ
Max
40
40
75
75
135
150
Unit
Notes
POWER OUTPUT (CONTINUED)
Output OFF Open Load Detection Current, Low-side Configuration
IOCO
VDRAIN = 16 V, VSOURCE = 0 V, Outputs Programmed OFF,
VPWR =16 V
• 33879
• 33879A
μA
VOC (LSD)
Output Clamp Voltage Low-side Drive
• ID = 10 mA
40
45
55
V
VOC (HSD)
Output Clamp Voltage High-side Drive
• IS = -10 mA
-15
- 20
- 25
V
IOUT (LKG)
Output Leakage Current High-side and Low-side Configurations
• VDD = 0 V, VDRAIN = 16 V, VSOURCE = 0 V
–
–
5.0
μA
IOUT (LKG)
Output Leakage Current Low-side Configuration
• VDD = 5.0 V, VDRAIN = 16 V, VSOURCE = 0 V, Open Load Detection
Current Disabled
–
–
5.0
Output Leakage Current High-side Configuration
• VDD = 5.0 V, VDRAIN = 16 V, VSOURCE = 0 V, Open Load Detection
Current Disabled
–
–
20
Overtemperature Shutdown
155
–
185
°C
(8)
Overtemperature Shutdown Hysteresis
5.0
10
15
°C
(8)
IOUT (LKG)
TLIM
TLIM (HYS)
μA
μA
DIGITAL INTERFACE
VIH
Input Logic High-voltage Thresholds
0.7 VDD
–
VDD + 0.3
V
(9)
VIL
Input Logic Low-voltage Thresholds
GND - 0.3
–
0.2 VDD
V
(9)
IN5, IN6, EN Input Logic Current
• IN5, IN6, EN = 0 V
-10
–
10
μA
IN5, IN6 Pull-down Current
• 0.8 to 5.0 V
30
45
100
μA
20
20
45
45
100
110
μA
SCLK, DI Input, Tri-state DO Output
• 0 to 5.0 V
-10
–
10
μA
ICS
CS Input Current
• CS = VDD
-10
–
10
μA
ICS
CS Pull-up Current
• CS = 0 V
-30
–
-100
μA
–
–
10
μA
VDD - 0.4
–
VDD
V
I IN5, I IN6, I EN
I IN5, I IN6,
I EN
I SCK, I DI, I TRI-DO
EN Pull-down Current, EN = 5.0 V
• 33879
• 33879A
ICS(LKG)
CS Leakage Current to VDD
• CS = 5.0 V, VDD = 0 V
VDOHIGH
DO High State Output Voltage
• IDO-HIGH = -1.6 mA
Notes
8. This parameter is guaranteed by design; however, it is not production tested.
9. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, and EN.
33879
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, - 40 °C ≤ TC ≤ 125 °C, unless otherwise noted. Where
applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 °C.
Symbol
Characteristic
Min
Typ
Max
Unit
DO Low State Output Voltage
• IDO-LOW = 1.6 mA
–
–
0.4
V
Input Capacitance on SCLK, DI, Tri-state DO, IN5, IN6, EN
–
–
20
pF
Notes
DIGITAL INTERFACE (CONTINUED)
VDOLOW
CIN
(10)
Notes
10. This parameter is guaranteed by design; however, it is not production tested.
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
4.3
Dynamic Electrical Characteristics
Table 6. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, - 40 °C ≤ TC ≤ 125 °C, unless otherwise noted. Where
applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 °C.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
POWER OUTPUT TIMING
t SR(RISE)
Output Slew Rate Low-side Configuration
• RLOAD = 620Ω, CL = 200pF
0.1
0.5
1.0
V/μs
(11)
t SR(FALL)
Output Slew Rate Low-side Configuration
• RLOAD = 620 Ω, CL = 200 pF
0.1
0.5
1.0
V/μs
(11)
t SR(RISE)
Output Rise Time High-side Configuration
• RLOAD = 620 Ω, CL = 200 pF
0.1
0.3
1.0
V/μs
(11)
t SR(FALL)
Output Fall Time High-side Configuration
• RLOAD = 620 Ω, CL = 200 pF
0.1
0.3
1.0
V/μs
(11)
t DLY(ON)
Output Turn ON Delay Time, High-side and Low-side Configuration
1.0
15
50
μs
(12)
t DLY(OFF)
Output Turn OFF Delay Time, High-side and Low-side Configuration
1.0
30
100
μs
(12)
Output Fault Delay Time
100
–
300
μs
(13)
Power-ON Reset Delay
• Delay Time Required from Rising Edge of EN and VDD to SPI Active
100
–
–
μs
Low-State Duration on VDD or EN for Reset
• VDD or EN ≤ 0.2 V
100
–
–
µs
–
4.0
–
MHz
t FAULT
tPOR
t RESET
DIGITAL INTERFACE TIMING(14)
f SPI
Recommended Frequency of SPI Operation
(14)
t LEAD
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
100
–
–
ns
t LAG
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
50
–
–
ns
t DI (SU)
DI to Falling Edge of SCLK (Required Setup Time)
16
–
–
ns
t DI (HOLD)
Falling Edge of SCLK to DI (Required Hold Time)
20
–
–
ns
t R (DI)
DI, CS, SCLK Signal Rise Time
–
5.0
–
ns
(15)
t F (DI)
DI, CS, SCLK Signal Fall Time
–
5.0
–
ns
(15)
t DO (EN)
Time from Falling Edge of CS to DO Low-impedance
–
–
55
ns
(16)
t DO (DIS)
Time from Rising Edge of CS to DO High-impedance
–
–
55
ns
(17)
Time from Rising Edge of SCLK to DO Data Valid
–
25
55
ns
(18)
t VALID
Notes
11. Output slew rate respectively measured across a 620 Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points.
CL capacitor is connected from Drain or Source output to Ground.
12.
13.
14.
15.
16.
17.
18.
Output turn ON and OFF delay time measured from 50 percent rising edge of CS to the beginning of the 10 and 90 percent transition points.
Duration of fault before fault bit is set. Duration between access times must be greater than 300 μs to read faults.
This parameter is guaranteed by design. Production test equipment uses 4.16 MHz, 5.5 V/3.1 V SPI interface.
Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at DO pin.
Time required for output status data to be terminated at DO pin.
Time required to obtain valid data out from DO following the rise of SCLK.
33879
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
4.4
Timing Diagrams
CS
0.2 VDD
tLEAD
SCLK
tLAG
0.7 VDD
0.2 VDD
tDI(SU) tDI(HOLD)
DI
0.7 VDD
0.2 VDD
MSB in
tDO(EN)
DO
tDO(DIS)
tVALID
0.7 VDD
0.2 VDD
MSB out
LSB out
Figure 4. SPI Timing Diagram
VDD = 5.0 V
33879
Under
Test
SCLK
DO
CL = 200 pF
NOTE: CL represents the total capacitance of the test
fixture and probe.
Figure 5. Valid Data Delay Time and Valid Time Test Circuit
tR(DI)
0.7 VDD
SCLK
< 50 ns
tF(DI
50%
0.2 VDD
0V
0.7 VDD
DO
0.2 VDD
(Low-to-High)
DO
< 50 ns
3.3/5.0 V
VOH
VOL
tR(DO
tVALID
(High-to-Low) 0.7 VDD
0.2
VOH
VOL
Figure 6. Valid Data Delay Time and Valid Time Waveforms
33879
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
tF(CS)
tR(CS)
< 50 ns
< 50 ns
3.3/5.0 V
90%
CS
0.2 VDD
0.7 VDD
10%
0V
tDO(EN)
tDO(DIS)
VTri-State
DO
(Tri-State to Low)
90%
10%
tDO(EN)
VOL
tDO(DIS)
VOH
90%
DO
VTri-State
10%
(Tri-State to High)
Figure 7. Enable and Disable Time Waveforms
4.5
Typical Electrical Characteristics
140
VPWR @ 18 V
19
33879
18
17
16
33879A
15
14
-40 -25
0
25
50
75
100
125
IPWR Current into VPWR Pin (µA
IPWR Current into VPWR Pin (mA)
20
TA = 25ℜ°
120
100
33879
80
60
40
20
33879A
0
5
TA, Ambient Temperature (ℜ°C
20
25
Figure 10. Sleep State IPWR vs. VPWR
Figure 8. IPWR vs. Temperature
1.4
7
VPWR @ 13 V
6
1.2
5
1.0
RDS(ON) (Ω)
IPWR Current into VPWR Pin (µA
10
15
VPWR
4
3
2
VPWR @ 13 V
High-side Drive
0.8
0.6
0.4
1
-40 -25
0
25
50
75
100
125
TA, Ambient Temperature (ℜ°C
Figure 9. Sleep State IPWR vs. Temperature
-40 -25
0
25
50
75
100
TA, Ambient Temperature (ℜ°C
125
Figure 11. RDS(ON) vs. Temperature at 350 mA
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1.4
TA = 25ℜ°
High-side Drive
IOCO, Open Load (µA
1.2
VPWR @ 13 V
RDS(ON) (Ω)
1.0
0.8
0.6
0.4
0.2
0
5
10
15
20
120
100
80
60
High-side
40
Low-side
20
-40 -25
25
25
50
75
100
125
TA, Ambient Temperature (ℜ°C
VPWR (V)
Figure 13. Open Load Detection Current at Threshold
VOUT(flt-th), Open Load Threshold (V)
Figure 12. RDS(ON) vs. VPWR at 350 mA
0
5.5
5.0
VPWR @ 13 V
High-side and Low-side
4.5
4.0
3.5
3.0
2.5
-40 -25
0
25
50
75
100
125
TA, Ambient Temperature (ℜ°C
Figure 14. Open Load Detection Threshold vs. Temperature
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5
Functional Description
5.1
Functional Pin Description
5.1.1
CS PIN
The system MCU selects the 33879 with which to communicate through the use of the chip select CS pin. Logic low on CS enables the
data output (DO) driver and allows data to be transferred from the MCU to the 33879 and vice versa. Data clocked into the 33879 is acted
upon on the rising edge of CS. To avoid any spurious data, it is essential the high-to-low transition of the CS signal occur only when the
SPI clock (SCLK) is in a logic low state.
5.1.2
SCLK Pin
The SCLK pin clocks the internal shift registers of the 33879. The serial data input (DI) pin is latched into the input shift register on the
falling edge of the SCLK. The serial data output (DO) pin shifts data out of the shift register on the rising edge of the SCLK signal. False
clocking of the shift register must be avoided to ensure validity of data. It is essential the SCLK pin be in a logic low state when the CS pin
makes any transition. For this reason, it is recommended the SCLK pin is commanded to a logic low state when the device is not accessed
(CS in logic high state). With CS in a logic high state, signals present on SCLK and DI are ignored and the DO output is in tri-state.
5.1.3
DI Pin
The DI pin is used for serial instruction data input. DI information is latched into the input register on the falling edge of SCLK. A logic high
state present on DI programs a specific output on. The specific output turns on with the rising edge of the CS signal. Conversely, a logic
low state present on the DI pin programs the output off. The specific output turns off with the rising edge of the CS signal. To program the
eight outputs and open load detection current on or off, send the DI data beginning with the open load detection current bits, followed by
output eight, output seven, and so on to output one. For each falling edge of the SCLK while CS is logic low, a data bit instruction (on or
off) is loaded into the shift register per the data bit DI state. Sixteen bits of entered information is required to fill the input shift register.
5.1.4
DO Pin
The DO pin is the output from the shift register. The DO pin remains tri-state until the CS pin is in a logic low state. All faults on the 33879
device are reported as logic [1] through the DO data pin. Regardless of the configuration of the driver, open loads and shorted loads are
reported as logic [1]. Conversely, normal operating outputs with non-faulted loads are reported as logic [0]. Outputs programmed with
open load detection current disabled report logic [0] in the off state. The first eight positive transitions of SCLK report logic [0] followed by
the status of the eight output drivers. The DI / DO shifting of data follows a first-in, first-out protocol with both input and output words
transferring the most significant bit (MSB) first.
5.1.5
EN Pin
The EN pin on the 33879 enables the device. With the EN pin high, output drivers may be activated and open / short fault detection
performed and reported. With the EN pin low, all outputs become inactive, open load detection current is disabled, and the device enters
Sleep mode. The 33879 performs Power-ON Reset on the rising edge of the enable signal.
5.1.6
IN5 and IN6 Pins
The IN5 and IN6 command inputs allow outputs five and six to be used in PWM applications. The IN5 and IN6 pins are OR-ed with the
serial peripheral interface (SPI) command input bits. For SPI control of outputs five and six, the IN5 and IN6 pins should be grounded or
held low by the microprocessor. When using IN5 or IN6 to PWM the output, the control SPI bit must be logic [0]. Maximum PWM frequency
for each output is 2.0 kHz.
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5.1.7
VDD Pin
The VDD input pin is used to determine logic levels on the microprocessor interface (SPI) pins. Current from VDD is used to drive the DO
output and the pull-up current for CS. VDD must be applied for normal mode operation. The 33879 device performs Power-ON Reset with
the application of VDD.
5.1.8
VPWR Pin
The VPWR pin is the battery input and Power-ON Reset to the 33879 IC. The VPWR pin has internal reverse battery protection. All internal
logic current is provided from the VPWR pin. The 33879 performs Power-ON Reset with the application of VPWR.
5.1.9
D1– D8 Pins
The D1 to D8 pins are the open-drain outputs of the 33879. For high-side drive configurations, the drain pins are connected to battery
supply. In low-side drive configurations, the drain pins are connected to the low-side of the load. All outputs may be configured individually
as desired. When configured as low-side drive, the 33879 limits the positive inductive transient to 45 V.
5.1.10 S1– S8 Pins
The S1 to S8 pins are the source outputs of the 33879. The source pins are connected directly to the load for high-side drive
configurations. In low-side drive configurations, the source is connected to ground. All outputs may be configured individually as desired.
When high-side drive is used, the 33879 will limit the negative inductive transient to negative 20 V.
5.1.11 Exposed Pad Pin
Device performs as specified with the Exposed Pad un-terminated (floating) however, it is recommended the Exposed Pad be terminated
to pin 1 (GND) and system ground.
5.2
MCU Interface Description
5.2.1
Introduction
The 33879 is an eight output hardware-configurable power switch with 16-bit serial control. A simplified internal block diagram of the 33879
is shown in Figure 2. The 33879 device uses high-efficiency up-drain power DMOS output transistors exhibiting low drain-to-source ON
resistance (RDS(on) = 0.75 Ω at 25 °C typical) and dense CMOS control logic. All outputs have independent voltage clamps to provide fast
inductive turn-off and transient protection.
In operation, the 33879 functions as an eight output serial switch, serving as an MCU bus expander and buffer with fault management
and fault reporting features. In doing so, the device directly relieves the MCU of the fault management functions. This device directly
interfaces to an MCU using a SPI for control and diagnostic readout. Figure 15 illustrates the basic SPI configuration between an MCU
and one 33879.
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MC68HCxx
Microcontroller
33879
DI
MOSI
Shift Register
Shift Register
MISO
DO
16 Bits
16 Bits
SCLK
Receive
Buffer
To
Logic
CS
Parallel
Ports
Figure 15. SPI Interface with Microcontroller
All inputs are compatible with 5.0 V and 3.3 V CMOS logic levels and incorporate positive logic. When a SPI bit is programmed to a
logic [0], the corresponding output is OFF. Conversely, when a SPI bit is programmed to logic [1] the output being controlled is ON.
Diagnostics are treated in a similar manner. Outputs with a fault feed back (via DO) a logic [1] to the microcontroller, while normal operating
outputs provide a logic [0].
Figure 16 illustrates the daisy chain configuration using the 33879. Data from the MCU is clocked daisy chain through each device while
the CS bit is commanded low by the MCU. During each clock cycle, output status from the daisy chain is transferred to the MCU via the
Master In Slave Out (MISO) line. On rising edge of CS, command data stored in the input register is then transferred to the output driver.
SCLK
Parallel Port
33879
CS
MC68HCxx
MISO
Microcontroller
DO
with
SPI Interface
DI
8 Outputs
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CS
SCLK
CS
DO
DI
DO
8 Outputs
SCLK
DI
8 Outputs
MOSI
Figure 16. 33879 SPI System Daisy Chain
Multiple 33879 devices can be controlled in a parallel input fashion using the SPI. Figure 17 illustrates the control of 24 loads using three
dedicated parallel MCU ports for chip select.
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MOSI
DI
SCLK
SCLK
MISO
8 Outputs
DO
CS
MC68HCxx
Microcontroller
with
SPI Interface
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DI
SCLK
DO
CS
8 Outputs
33879
Parallel
Ports
A
DI
B
SCLK
C
DO
8 Outputs
CS
Figure 17. Parallel Input SPI Control
5.3
SPI Definition
A 16-bit command word is sent to the 33879 on each SPI communication and a 16-bit status word is received from the 33879. The MSB
is sent and received first. As Table 7 shows, the Command Register defines the position and operation the 33879 performs on the rising
edge of CS. The Fault Register, shown in Table 8, defines the previous state status of the output driver. Table 9 identifies the type of fault
and the method by which the fault is communicated to the microprocessor
Table 7. Command Register Definition
MSB
LSB
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ON /
OFF
Open
Load
Detect
8
ON /
OFF
Open
Load
Detect
7
ON /
OFF
Open
Load
Detect
6
ON /
OFF
Open
Load
Detect
5
ON /
OFF
Open
Load
Detect
4
ON /
OFF
Open
Load
Detect
3
ON /
OFF
Open
Load
Detect
2
ON /
OFF
Open
Load
Detect
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ON /
OFF
OUT 8
ON /
OFF
OUT 7
ON /
OFF
OUT 6
ON /
OFF
OUT 5
ON /
OFF
OUT 4
ON /
OFF
OUT 3
ON /
OFF
OUT 2
ON /
OFF
OUT 1
0 = Bits 0 to 7, Output commanded OFF.
0 = Bits 8 to 15, Open Load Detection Current OFF.
1 = Bits 0 to 7, Output commanded ON.
1 = Bits 8 to 15 Open Load Detection Current ON.
Table 8. Fault Register Definition
MSB
LSB
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
OUT 8
Status
OUT 7
Status
OUT 6
Status
OUT 5
Status
OUT 4
Status
OUT 3
Status
OUT 2
Status
OUT 1
Status
0 = Bits 0 to 7, No Fault at Output.
1 = Bits 0 to 7, Output Short-to-Battery, Short-to-GND, Open Load, or TLIM.
Bits 8 to 15 will always return “0”.
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Table 9. Fault Operation
Serial Output (DO) Pin Reports
Overtemperature
Fault reported by serial output (DO) pin.
Overcurrent
DO pin reports short to battery/supply or overcurrent condition.
Output ON Open Load Fault
Not reported.
Output OFF Open Load Fault
DO pin reports output OFF open load condition only with Open Load Detection Current enabled.
DO pin will report “0” for Output OFF Open Load Fault with Open Load Detection Current disabled.
Device Shutdowns
Overvoltage
Total device shutdown at VPWR = VPWR(OV) V. Resumes normal operation with proper voltage. All outputs assuming
the previous state upon recovery from overvoltage.
Overtemperature
Only the output experiencing an overtemperature shuts down. Output assumes previous state upon recovery from
overtemperature.
5.4
Device Operation
5.4.1
Power Supply
The 33879 device has been designed with ultra-low Sleep mode currents. The device may enter Sleep mode via the EN pin or the VDD
pin. In the Sleep mode (EN or VDD ≤ 0.8 V), the current consumed by the VPWR pin is less than 5.0 μA. Placing the 33879 in Sleep mode
resets the internal registers to the Power-ON Reset state. The reset state is defined as all outputs off and open load detection current
disabled. To place the 33879 in the Sleep mode, either command all outputs off and apply logic low to the EN input pin or remove power
from the VDD supply pin. Prior to removing VDD from the device, it is recommended that all control inputs from the MCU be low.
5.4.2
Paralleling of Outputs
Using MOSFETs as an output switch conveniently allows the paralleling of outputs for increased current capability. RDS(on) of MOSFETs
have an inherent positive temperature coefficient providing balanced current sharing between outputs without destructive operation. This
mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching
higher currents. Performance of parallel operation results in a corresponding decrease in RDS(on), while the output OFF open load detection
currents and the output current limits increase correspondingly. Paralleling outputs from two or more different IC devices is possible, but
not recommended.
5.4.3
Fault Logic Operation
Fault logic of the 33879 device has been greatly simplified over other devices using SPI communications. As command word one is being
written into the shift register, a fault status word is being simultaneously written out and received by the MCU. Regardless of the
configuration, with no outputs faulted and open load detection current enabled, all status bits being received by the MCU are zero. When
outputs are faulted (off state open circuit or on state short-circuit / overtemperature), the status bits being received by the MCU are one.
The distinction between open circuit fault and short / overtemperature is completed via the command word. For example, when a zero
command bit is sent and a one fault is received in the following word, the fault is open / short-to-battery for high-side drive or open / shortto-ground for low-side drive. In the same manner, when a one command bit is sent and a one fault is received in the following word, the
fault is a short-to-ground / overtemperature for high-side drive or short-to-battery/overtemperature for low-side drive. The timing between
two write words must be greater than 300 μs to allow adequate time to sense and report the proper fault status.
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5.4.4
SPI Integrity Check
Checking the integrity of the SPI communication with the initial power-up of the VDD and EN pins is recommended. After initial system
start-up or reset, the MCU writes one 32-bit pattern to the 33879. The first 16 bits read by the MCU are 8 logic [0]s followed by the fault
status of the outputs. The second 16 bits are the same bit pattern sent by the MCU. By the MCU receiving the same bit pattern it sent,
bus integrity is confirmed. Note the second 16-bit pattern the MCU sends to the device is the command word and is transferred to the
outputs with rising edge of CS. Important: A SCLK pulse count strategy has been implemented to ensure integrity of SPI communications.
SPI messages consisting of 16 SCLK pulses and multiples of 8 clock pulses thereafter are acknowledged. SPI messages consisting of
other than 16 + multiples of 8 SCLK pulses are ignored by the device.
5.4.5
Overtemperature Fault
Overtemperature detection and shutdown circuits are specifically incorporated for each individual output. The shutdown following an
overtemperature condition is independent of the system clock or any other logic signal. Each independent output shuts down at 155 °C
to 185 °C. When an output shuts down owing to an overtemperature fault, no other outputs are affected. The MCU recognizes the fault
by a one in the fault status register. After the 33879 device has cooled below the switch point temperature and 15 °C hysteresis, the output
activates unless otherwise told to shut down by the MCU via the SPI.
5.4.6
Overvoltage Fault
An overvoltage condition on the VPWR pin causes the device to shut down all outputs until the overvoltage condition is removed. When
the overvoltage condition is removed, the outputs resume their previous state. This device does not detect an overvoltage on the VDD
pin. The overvoltage threshold on the VPWR pin is specified as VPWR(OV) V, with 1.0 V typical hysteresis. A VPWR overvoltage detection
is global, causing all outputs to be turned OFF.
5.4.7
Output OFF Open Load Fault
An output OFF open load fault is the detection and reporting of an open load when the corresponding output is disabled (input bit
programmed to a logic low state). The Output OFF Open Load fault is detected by comparing the drain-to-source voltage of the specific
MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose. An output OFF open
load fault is indicated when the drain-to-source voltage is less than the output threshold voltage (VOUT(FLT-TH)) of 2.5 V to 4.0 V. Hence,
the 33879 declares the load open in the OFF state when the output drain-to-source voltage is less than VOUT(FLT-TH).
This device has an internal 80 μA current source connected from drain to source of the output MOSFET. The current source may be
programmed on or off via the SPI. The Power-ON Reset state for the current source is “off” and must be enabled via the SPI. To achieve
low Sleep mode quiescent currents, the open load detection current source of each driver is switched off when VDD or EN is removed.
During output switching, especially with capacitive loads, a false output OFF open load fault may be triggered. To prevent this false fault
from being reported, an internal fault filter of 100 μs to 300 μs is incorporated. A false fault reporting is a function of the load impedance,
RDS(on), COUT of the MOSFET, as well as the supply voltage, VPWR. The rising edge of CS triggers the built-in fault delay timer. The timer
times out before the fault comparator is enabled and the fault is detected. Once the condition causing the open load fault is removed, the
device resumes normal operation. The open load fault, however, is latched in the output DO register for the MCU to read.
5.4.8
Shorted Load Fault
A shorted load (overcurrent) fault can be caused by any output being shorted directly to supply, or an output experiencing a current greater
than the current limit. There are two safety circuits progressively in operation during load short conditions providing system protection:
1. The device’s output current is monitored in an analog fashion using SENSEFET approach and current limited.
2. The device’s output thermal limit is sensed and when attained causes only the specific faulted output to shutdown. The output
remains off until cooled. The device then reasserts the output automatically. The cycle continues until fault is removed or the
command bit instructs the output off. Shorted load faults are reported properly through the SPI regardless of open load detection
current enable bits.
5.4.9
Undervoltage Shutdown
An undervoltage condition on VDD or VPWR results in the shutdown of all outputs. The VDD undervoltage threshold is between 0.8 and
3.0 V. VPWR undervoltage threshold is between 3.0 V and 5.0 V. When the supplies fall below their respective thresholds, all outputs are
turned OFF. As both supplies returns to normal levels, internal logic is reset and the device resumes normal operation.
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5.4.10 Output Voltage Clamp
Each output of the 33879 incorporates an internal voltage clamp to provide fast turn-off and transient protection of each output. Each clamp
independently limits the drain-to-source voltage to 45 V for low-side drive configurations and -20 V for high-side drive configurations. The
total energy clamped (E J) can be calculated by multiplying the current area under the current curve (I A) times the clamp voltage (V CL) (see
Figure 18). Characterization of the output clamps, using a single pulse non-repetitive method at 0.35 A, indicates the maximum energy
per output to be 50 mJ at 150°C junction temperature.
Drain-to-Source Clamp
Voltage (VCL = 45 V)
Drain Voltage
Clamp Energy
(E J = I A x V CL)
Drain Current
(ID = 0.3 A)
Drain-to-Source ON
Voltage (VDS(ON))
Current
Area (I A)
GND
Drain-to-Source ON
Time
Voltage (VDS(ON))
VS
BAT
GND
Time
Current
Area (I A)
Clamp Energy
(E J = I A x V CL)
Source Current
(IS = 0.3 A)
Source Clamp Voltage
(V CL = -15 V)
Source Voltage
Figure 18. Output Voltage Clamping
5.4.11 SPI Configurations
The SPI configuration on the 33879 device is consistent with other devices in the Octal Serial Switch (OSS) family. This device may be
used in serial SPI or parallel SPI with the 33298 and 33291. Different SPI configurations may be provided. For more information, contact
Freescale Analog Products Division or the local Freescale representative.
5.4.12 Reverse Battery
The 33879 has been designed with reverse battery protection on the VPWR pin. All outputs consist of a power MOSFET with an integral
substrate diode. During the reverse battery condition, current flows through the load via the substrate diode. Under this circumstance,
relays may energize and lamps turn on. Where load reverse battery protection is desired, a reverse battery blocking diode must be placed
in series with the load.
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Package Dimensions
Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search using the
“98ARL10543D” drawing number listed below. Dimensions shown are provided for reference ONLY.
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7
Revision History
Revision
Date
Description of Changes
2/2006
• Page 2, Figure 1; An exposed pad internal block and EP pin have been added to the internal block diagram.
• Page 4, Table 1; Table 1 has been updated to reflect the Exposed pad pin and pin definition.
• Page 6, Table 3; Logic Supply Sleep State Hysteresis and Note 7 have been removed. The VDD Supply contains
no hysteresis.
• Page 7, Table 3; Output Fault Detection Current @ Threshold, High-Side Configuration Max parameter has been
increased from 70uA to 90uA.
• Page 7, Table 3; Output OFF Open Load Detection Current, High-Side Configuration has been updated to reflect
the voltage of the VPWR pin during the parameter test.
• Page 7, Table 3; Output OFF Open Load Detection Current, Low-Side Configuration has been updated to reflect the
voltage of the VPWR pin during the parameter test.
• Page 7, Table 3; Output Leakage Current High-Side and Low-Side Configuration Max parameter has been
decreased from 7uA to 5uA.
• Page 15, Functional Pin Description; A description has been added for the Exposed Pad pin.
• Page 1, Device isometric; Corrected orientation of IC pin 1 from top left to bottom right.
• ALL Pages; Updated Data Sheet to reflect Freescale formatting.
6.0
6/2007
• Added 33879A version
• Added MCZ33879EK/R2 and MCZ33879AEK/R2 to the Ordering Information
• Added Device Variations on page 2
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Rations on
page 6. Added note with instructions from www.freescale.com.
• Changed Output Fault Detection Voltage Threshold Outputs Programmed OFF on page 7
• Renumbered X axis on Figure 14 - Open Load Detection Threshold vs. Temperature on page 13
• Changed Overvoltage on page 18 and Overvoltage Fault on page 19
7.0
8/2008
• Updated package drawing.
8.0
10/2009
• Updated data sheet status from Advance Information to Technical Data
• Updated to the current Freescale form and style
5.0
9.0
5/2012
• Removed MC33879EK from the ordering information
• Removed MCZ33879AEK and added MC33879APEK to the ordering information
• Removed MCZ33879EK and added MC33879TEK to the ordering information
• Updated Output Fault Detection Current @ Threshold, High-side Configuration Outputs Programmed OFF on page 7
• Updated Output OFF Open Load Detection Current, High-side Configuration on page 7
• Updated Output OFF Open Load Detection Current, Low-side Configuration on page 8
• Updated EN Pull-down Current, EN = 5.0 V on page 8
• Updated the Freescale form and style
6/2012
• Updated Output Fault Detection Voltage Threshold Outputs Programmed OFF on page 7
• Updated Output Fault Detection Current @ Threshold, Low-side Configuration Outputs Programmed OFF on page 7
• Updated the max limit for Output Fault Detection Current @ Threshold, High-side Configuration Outputs
Programmed OFF on page 7
4/2013
• No technical changes. Revised back page. Updated document properties.
11/2015
• Changed feature on page 1 to Designed to operate 5.5 V < VPWR < 27.5 V
• Updated Freescale form and style.
10.0
11.0
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Analog Integrated Circuit Device Data
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© 2015 Freescale Semiconductor, Inc.
Document Number: MC33879
Rev. 11.0
11/2015