MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN10 3x3, 0.5P (Leads 2 & 3 Tied) CASE 517CC ISSUE O SCALE 2:1 D PIN ONE REFERENCE 0.15 C 2X 2X 0.15 C ÉÉÉ ÉÉÉ ÇÇÇ A B ÍÍÍ ÍÍÍ ÍÍÍ EXPOSED Cu DETAIL B ALTERNATE CONSTRUCTION E (0.17) A DETAIL B L1 A3 L DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS A1 0.08 C NOTE 4 C SIDE VIEW SEATING PLANE D2 DETAIL A 1 6 10 L 10X e BOTTOM VIEW b 0.10 C A 0.05 C B NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 2.63 10X L DIM A A1 A3 b D D2 E E2 e L L1 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 3.00 BSC 2.39 2.59 3.00 BSC 1.59 1.79 0.50 BSC 0.35 0.45 --0.15 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G 5 E2 10X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MOLD CMPD TOP VIEW 0.10 C DATE 10 OCT 2011 0.62 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 0.50 PITCH 1.81 3.30 PACKAGE OUTLINE 1 9X 0.80 0.30 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: STATUS: NEW STANDARD: 98AON59624E ON SEMICONDUCTOR STANDARD http://onsemi.com UDFN10 3X3, 0.5P (LEADS 2 &13 TIED) © Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 − Rev. 0 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98AON59624E PAGE 2 OF 2 ISSUE O REVISION RELEASED FOR PRODUCTION. REQ. BY J. SAMUDIO. DATE 10 OCT 2011 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2011 October, 2011 − Rev. O Case Outline Number: 517CC