TLE 983 x EMC-Reference-Design and external protective circuit Applic atio n N ote V1.1 2012-12 Aut o moti ve P ow er EMC-Reference-Design TLE983x Revision History: V1.1, 2012-12 Previous Version: none Page Subjects (major changes since last revision) 6, 7 Figure 3 and Figure 4: Rerouting of VBAT_SENSE line Application Note 2 V1.1, 2012-12 EMC-Reference-Design Table of Contents Table of Contents 1 Overview ............................................................................................................................................. 4 2 LIN ground and LS ground tracing................................................................................................... 5 3 3.1 3.2 Power Supply (VS) Decoupling for Improved Emissions and Immunity ...................................... 6 Decoupling of the Power Supply (VS) with respect to emission from the TLE983x ............................ 6 Decoupling of the TLE983x circuits with respect to immunity to Power Supply (VS) transients ......... 7 4 Default hardware circuitry ................................................................................................................. 8 5 Component value recommendation ............................................................................................... 10 6 Abbreviations ................................................................................................................................... 10 7 Additional Information ..................................................................................................................... 11 Application Note 3 V1.1, 2012-12 EMC-Reference-Design Overview 1 Overview Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. The TLE983x is a highly integrated device consisting of multiple analog and digital functional blocks. The system and the interfaces are controlled by an embedded standard XC800 microcontroller core (8051 compatible). Further functional blocks include a LIN transceiver for communication, on chip low drop-out voltage regulators for power supply, High Side and Low Side switches, several general purpose inputs/outputs (GPIO), a 10 channel 8-bit ADC and an 8 channel 10-bit ADC. This mix of digital, analog and microcontroller functions must be considered when designing the PCB layout to optimize LIN performance and EMC behavior. This document provides recommendations that should be considered when designing the PCB layout. The designer should also reference the Infineon PCB Design Guidelines for Microcontrollers (AP24026), which gives general design rules recommendations for microcontroller PCB design. Figure 1 TLE983x reference schematic basic decoupling and ground connections Application Note 4 V1.1, 2012-12 EMC-Reference-Design LIN ground and LS ground tracing 2 LIN ground and LS ground tracing VS and GND are the supply pins of the TLE983x. All the voltages of the various integrated modules are generated internally from VS. To ensure a proper robustness of the TLE983x, especially the LIN-Bus EMC immunity, some basic design rules should be considered. Resistance to conducted and radiated disturbances can be improved by separating the higher current LIN (LINGND) and LS (LSGND) driver grounds from the general power supply grounds (separation of the ground traces in an analog and a digital group). The suggested reference design results from this requirement. As shown in Figure 2 this can be done by isolating, but not disconnecting, the ground plane, from the LINGND and LSGND traces. Figure 2 Separated ground traces for LINGND and LSGND. LINGND and LSGND. The distance of LINGND and LSGND to the LE983x ground plane is symbolically represented by the dotted lines. Blue area: Ground plane bottom Red area: Ground plane top Green: Vias, connecting top and bottom ground Orange: Pads of the TLE983x (Red: Ground and NC pads) Black: Isolated ground plane bottom, to separate analog from digital ground Application Note 5 V1.1, 2012-12 EMC-Reference-Design Decoupling of the Power-Supply (VS) 3 Power Supply (VS) Decoupling for Improved Emissions and Immunity 3.1 Decoupling of the Power Supply (VS) with respect to emission from the TLE983x There are two primary sources of microcontroller power supply emissions. Firstly, the synchronous clocked logic functions lead to a peak current at the MCU clock frequency. Secondly, pulse pattern and clock output at any port pin will draw current at the pulse pattern’s frequency. Decoupling capacitors are intended to buffer the charge needed to feed the required current pulses. For the TLE983x family the decoupling is slightly more challenging due to the additional integrated High Side, Low Side switches and the VDDEXT output functional modules. Figure 3 shows the recommended PCB layout of the decoupling capacitors together with the recommended ground pattern for a 2-layer PCB. Figure 3 Example for the location of the decoupling capacitors under consideration of the proper ground tracing described in Chapter 2. In this implementation, the battery supply VS and GND noise is filtered by capacitors C0 and C1. C0 and C1 typically provide bulk capacitance for the overall module at the point of entry of the VS supply to the module. C2 (placed on the bottom side in the diagram above) provides bulk capacitance for ECU, while C3 provides filtering for higher frequencies. The core supply pin VDDC should be connected to the capacitors C4 and C5 in order to reduce noise at the ground connection which can be caused by the synchronous logic clocked at the MCU frequency. The 5V VDDP output which serves as the supply for the port pin and other analog functions should Application Note 6 V1.1, 2012-12 EMC-Reference-Design Decoupling of the Power-Supply (VS) be stabilized by capacitors C6 and C7, while VDDEXT is decoupled by capacitor C8. C4, C6 and C8 should be placed close to the VDDC/VDDP/VDDEXT pins for best immunity and emissions results. The close placement of the capacitors to the voltage pads reduces trace resistance and inductance and ensures a fast response time to disturbances. The location of the capacitors C0, C1 (VS) and C9 (LIN) are, from the viewpoint of emissions, not as relevant and they can be placed at any suitable location. This is also valid for the related conducting paths and is symbolically represented by dashed traces in the figures. For the recommended capacitor values refer to the corresponding data sheet of the TLE983x. Top and bottom side layout details of the 2-layer PCB, as well as three dimensional views of the PCB, are shown in Figure 4 - Figure 7. Figure 4 Top layer view 3.2 Decoupling of the TLE983x circuits with respect to immunity to Power Supply (VS) transients Diode D1 protects capacitor C2 (electrolytic capacitor) and the TLE983x from reverse polarity. Capacitors C0 and C1 provide bulk capacitance, buffering lower frequency transients on the VS supply. C0 and C1 should be placed close to the power connection pad of the PCB. C2 provides filtering for medium frequency transients and balancing of the inductivity of the supply line and should be placed somewhere between C0, C1 and C3. Capacitor C3 provides decoupling for higher frequency VS transients which can be caused for example by switching of a HSS or LSS output (sudden load change within the TLE983x). The placement of C3 should be as close to the VS pin of the chip as possible (see Chapter 3.1). Some applications require ceramic capacitors from a supply voltage to ground to be implemented as series combination of two capacitors, to protect against potential low impedance\shorts caused by mechanical stress\damage. In this case the recommended values from the datasheet should be doubled for the two series capacitors. Application Note 7 V1.1, 2012-12 EMC-Reference-Design Decoupling of the Power-Supply (VS) 4 Default hardware circuitry One of the big advantages of the TLE983x is the integration of all functional units (ADC, CCU, MDU, LSS, HSS…) on one die. The power regulators which provide the needed voltages are integrated in the TLE983x as well. Therefore a minimum external protective circuit is necessary. All needed external hardware was already subject in the chapters above. The embedded power device TLE983x is fully functional with this external hardware. The capacitors C0 and C1 should be place close to the off board power connector (VBAT) of the PCB and should have a strong GND connection. The same applies to the capacitor C9 of the LIN bus. C9 should also be positioned close to the LIN off-board connector of the PCB. There is no stringent reason to place the capacitors C2 and C8 on the bottom layer. They can be placed on the top layer if the available space on the PCB permits it. Figure 5 Bottom layer view (mirrored) Application Note 8 V1.1, 2012-12 EMC-Reference-Design Decoupling of the Power-Supply (VS) Figure 6 3-dimensional view, top layer Figure 7 3-dimensional view, bottom layer Application Note 9 V1.1, 2012-12 EMC-Reference-Design Decoupling of the Power-Supply (VS) 5 Component value recommendation Table 1 Component recommendation Symbol Function Comment CVS blocking capacitor at VS pin > 20 μF Elco (C2) + 100 nF Ceramic (C3), ESR < 1 Ω CVDDP blocking capacitor at VDDP pin 1 μF typ. (C7) + 100 nF Ceramic (C6), ESR < 1 Ω CVDDEXT blocking capacitor at VDDEXT pin 10nF typ. (C8), ESR < 1 Ω CVDDC blocking capacitor at VDDC pin > 330 nF (C5) + 100 nF Ceramic (C4), ESR < 1 Ω CVAREF blocking capacitor at VAREF pin > 100 nF (C10), ESR < 1 Ω CVBAT buffering capacitor at VBAT connector to PCB defined by application design CLIN blocking capacitor at LIN trace 220 pF typ. (C9) (slave), 1 nF RVBAT_SENSE resistor at VBAT_SENSE pin 1 kΩ (R1) 6 Abbreviations The following acronyms and terms are used within this document. Table 2 Acronyms Acronym Name ADC Analog to Digital Converter CCU Capture Compare Unit ECU Electronic Control Unit EMC Electromagnetic Compatibility EP Exposed Pad (recommended to connect to GND) GPIO General Purpose Input Output HSS High Side Switch LIN Local Interconnect Network LSS Low Side Switch MCU Microcontroller Unit MDU Multiplication/Division Unit N.C. Not Connected PCB Printed Circuit Board VAREF ADC Reference Voltage VBAT Battery Supply VBAT_SENSE VBAT sense input VDDC Core supply voltage VDDEXT External voltage supply VDDP I/O Port supply voltage VS Voltage Supply input Application Note 10 V1.1, 2012-12 EMC-Reference-Design Abbreviations 7 Additional Information For further information you may contact http://www.infineon.com Application Note 11 V1.1, 2012-12 Edition 2012-12 Published by Infineon Technologies AG 81726 Munich, Germany © 2012 Infineon Technologies AG All Rights Reserved. LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. 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