NovalithIC™ half-bridge family BTN89xy

BTN8960 /62 /80 /82
NovalithICTM
High Current PN Half Bridge
Application Note
Rev. 0.4, 2015-07-02
Automotive Power
BTN8960 /62 /80 /82
High Current PN Half Bridge
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.2
Motor Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Half-bridge configuration for mono-directional motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
H-Bridge configuration for bidirectional motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3
3.1
Parasitic Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Measuring signals at NovalithICTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4
4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.4
4.5
Design guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Schematic and layout design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DC-link capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Calculation of the DC-link capacitor and Pi-filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Under-voltage toggling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Driving inductive loads over long wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PWM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5
5.1
5.1.1
5.1.2
5.1.3
5.2
5.3
5.4
5.4.1
5.5
5.5.1
5.5.1.1
5.5.1.2
5.5.2
5.5.2.1
5.5.2.2
Current Sense Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Characteristic of the dkILIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Supply voltage dependency of dkILIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TC 1000 life time tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Temperature drift of the dkILIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Offset compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Device specific dkILIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Device fine dkILIS and temperature compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
An example of the IIS failure with a rough temperature estimation . . . . . . . . . . . . . . . . . . . . . . . . . . 28
IS-pin current sensing and fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Current sense behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
BTN89yz - advanced current sense and fault diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
BTN79xy current sense limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Temperature drift of the IS-pin’s current in fault condition IIS(lim) . . . . . . . . . . . . . . . . . . . . . . . . . 36
Failure detection flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6
6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
6.3
6.3.1
6.3.2
Switching Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Timing behavior for rising edge on high side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
BTN8962TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
BTN8982TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Timing behavior for falling edge on high side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
BTN8962TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
BTN8982TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Timing behavior for rising edge on low side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
BTN8962TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
BTN8982TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Application Note
2
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
6.4
6.4.1
6.4.2
6.5
6.6
6.6.1
6.6.2
6.7
6.7.1
6.7.2
6.8
6.8.1
6.8.2
6.8.3
Timing behavior for falling edge on low side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
BTN8962TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
BTN8982TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Error of total delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Delay time calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Output voltage based calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Current sense based calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
ADC Timing for current measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Current sense ADC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Offset current calibration ADC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Allowed PWM setup for current sense ADC measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
BTN8962TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
BTN8982TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Example calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.5
7.6
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Power dissipation of the control chip (top chip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Conduction power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Power dissipation due to switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Entire power dissipation of the MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
PWM control and the duty cycle constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Entire power dissipation in the actuator MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Entire power dissipation in the freewheeling MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Entire power dissipation in the NovalithICTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Simplifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
8
8.1
8.2
8.2.1
8.2.2
Thermal Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Zth simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Thermal RC-network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Parameters for BTN8960/62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Parameters for BTN8980/82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Application Note
3
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Abstract
1
Abstract
Note: The following information is only given to help with the implementation of the device and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
This Application Note is intended to provide information and hints for a high current design, using PWM
control with the NovalithIC™ half-bridge family BTN8960 /62 /80 /82 for the automotive environment.
This contains one P-channel high side MOSFET and with an integrated driver IC in one package. The
NovalithIC™ is the interface between the microcontroler and the motor, equipped with diagnostic and
protection functions.
VS
Undervolt.
detection
Current
Sense
Overcurr.
Detection
HS
Overtemp.
detection
Gate Driver
HS
IS
Digital Logic
IN
LS off
HS off
OUT
Gate Driver
LS
INH
Overcurr.
Detection
LS
Slewrate
Adjustment
SR
GND
Figure 1
Block Diagram BTN8960 /62 /80 /82
Application Note
4
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Motor Configurations
2
Motor Configurations
Electrical motors are built with various architectures. Mechanically commutated motors with brushes, so
called DC motors or electrically commutated motors, so called BLDC motors (Brush Less DC motors). The
NovalithIC™ family can support all of them due to, the flexibility of the half-bridge concept.
Using NovalithIC™ controlling a DC-motor has the following advantages:
•
Extremely low parasitic inductances between high side and low side MOSFET.
•
Optimized switching performance of the MOSFET’s to reduce power losses and EMC emission.
•
Driving the motor with PWM for torque and speed control.
•
Integrated freewheeling transistor.
•
Integrated current measurement.
•
Integrated diagnosis and protection.
•
Microcontroller -compatible input pins.
•
Small and PCB-area saving package.
2.1
Half-bridge configuration for mono-directional motor control
Figure 2 shows the design of a mono-directional motor control with NovalithIC™. In most cases, the motor is
connected between “OUT” and “GND”. This is because the chassis of a car is “GND”, and therefore a short to
“GND” is much more probable than a short to “Vs”. For this reason it is statistically safer with a motor
connected to “GND”, because if a short accures in this case, the motor is not running.
Generally, it is also possible to use the NovalithIC™ to drive the motor between “OUT” and “Vs”. The inverted
“IN” signal must be respected.
Application Note
5
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Motor Configurations
Microcontroller
I/O
WO
Reset
RO
Q
Vdd
XC866
Vss
I/O
I/O
CQ
22µF
D
(IPD90P03P4L-04)
TLE
4278G
VS
L1
CI
470nF
DZ 1
10V
GND
BTN89xx
INH
IN
C9
100nF
C10
470µF/
CO 2V
220nF
1000µF
OUT
R12
1kΩ
R11
C2
0..51kΩ
100nF
M
COUT
220nF
IS
CIS
1nF
C1
47µF/
100µF
R3
10kΩ
VS
R1
10kΩ
I
CD
47nF
I/O
R2
10kΩ
Reverse Polarity
Protection
Voltage Regulator
SR
GND
Figure 2
Application circuit for a monodirectional motor with BTN8960 /62 /80 /82
2.2
H-Bridge configuration for bidirectional motor control
With the NovalithIC™ family it is easy to build an H-bridge for bidirectional DC motor control by simply
combining two devices in H-bridge configuration, as it is shown in Figure 3.
Application Note
6
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Motor Configurations
Microcontroller
XC866
Reverse Polarity
Protection
Voltage Regulator
I/O
WO
Reset
RO
Q
Vdd
Vss
CQ
22µF
D
(IPD90P03P4L-04)
TLE
4278G
I
VS
CI
470nF
L1
GND
C1
47µF/
100µF
R3
10kΩ
CD
47nF
A/D I/O I/O I/O A/D
DZ 1
10V
optional
R12
10kΩ
BTN89xy
BTN89xy
VS
R11
10kΩ
INH
IN
OUT
C1IS
1nF
C2 O2V
220nF
VS
IN
IS
C2OUT
C29
220nF 100nF
GND
R21
10kΩ
INH
OUT
M
1000µF
C1OUT
220nF
SR
C12
100nF
Figure 3
C1O 2V
220nF
C19
100nF
IS
R112
1kΩ
C10
470µF/
R22
10kΩ
R212
1kΩ
SR
GND
R211
0..51kΩ
R111
0..51kΩ
C2IS
1nF
C22
100nF
Application circuit for a bidirectional motor with BTN8960 /62 /80 /82 H-bridge
Application Note
7
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Parasitic Inductance
3
Parasitic Inductance
In high-current applications, which the NovalithIC™ family is designed for, special care must be taken for
parasitic inductors. The same is valid in case of very high frequencies, which are interesting with regard to EMC
considerations.
Each kind of wire in the application is an inductor, e.g. PCB wires, bond wires, etc. The wire inductance can be
estimated with
•
1mm PCB wire length approximately 1.2 nH
•
1 PCB via approximately 1 nH
The voltage drop of a wire can be calculated in the following way:
(3.1)
UL = L⋅
dI
dt
As can be seen from this equation, care must be taken with the parasitic wire inductors with increasing current
and decreasing switching time. The NovalithIC™ is designed to switch high currents very quickly. This means
in applications with NovalithIC™, the parasitic inductors are relevant and special care must be taken.
3.1
Measuring signals at NovalithICTM
The parasitic inductance also has an influence on the measurement results. To measure the true signals at the
NovalithIC™ it is mandatory to position the measurement probes directly at the device, as it is shown in
Figure 4. The probe is connected directly to the Vs-pin of the NovalithIC™ and the reference signal directly to
the GND-pin of the device.
Application Note
8
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Parasitic Inductance
Figure 4
Measuring Vs with Probe and Reference Directly Connected to NovalithICTM
Doing so enables to monitoring of the NovalithIC™ supply voltage when high currents are switched. For
example when a short-circuit current is switched, this is the only possibility for measurement if the DC-link
capacitor is sufficient to keep the supply voltage above the undervoltage detection threshold (also see
Chapter 4.2).
Application Note
9
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Design guideline
4
Design guideline
For a safe and sufficient motor control design, discrete components are needed. Some of them must be
dedicated to the motor application and some to the NovalithIC™.
4.1
Schematic and layout design rules
Figure 5 and Figure 6 show an example of a schematic plus a corresponding layout for a half-bridge motor
control with NovalithIC™.
47μF
The best performance in terms of parasitic inductance and EMC can be reached with a GND plane, which we
strongly recommend be used.
Figure 5
Example of a half-bridge schematic with NovalithICTM
Important design and layout rules:
The basis for the following items is the parasitic inductance of electrical wires, as described in Chapter 3.
•
C10, so called DC-link capacitor: This electrolytic capacitor is required to keep the voltage ripple at the VSpin of the NovalithIC™ low during switching operation (the measurement procedure for the supply voltage
is described in Chapter 3.1). It is strongly recommended that the voltage ripple at the NovalithIC™ Vs-pin
to GND-pin be kept below 1 V peak to peak. The value of C10 must be aligned accordingly. See
Equation (4.9).
Most electrolytic capacitors are less effective at cold temperatures. It must be assured that C10 is also
effective under the worst case conditions of the application.
The layout is very important. As shown in Figure 6, the capacitor C10 must be positioned with very short
wiring at the NovalithIC™. This must be done to keep the parasitic inductors of the PCB-wires as small as
possible.
•
C9: This ceramic capacitor supports C10 to keep the supply voltage ripple low and covers the fast
transients between the Vs-pin and the GND-pin. The value of this ceramic capacitor must be chosen so that
fast Vs-ripple at the NovalithIC™ does not exceed 1 V peak to peak.
The layout wiring for C9 must be shorter than for C10 to the NovalithIC™ to keep the parasitic PCB-wire
inductance as small as possible. In addition the parasitic inductance could be kept low by placing at least
two vias for the connection to the GND-layer.
•
C_O2V: This ceramic capacitor is important for EMI in order to avoid entering electro magnetic
disturbances into the NovalithIC™ as much as possible. Good results have been achieved with a value of
220 nF.
In terms of layout, it is important to place this capacitor between “OUT” and “Vs” without significant
additional wiring from C_O2V to the Vs- and OUT-line.
Application Note
10
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Design guideline
•
C_OUT: This ceramic capacitor helps improve the EMI and the ESD performance of the application. Good
results have been achieved with a value of 220 nF.
To keep the RF and ESD out of the board, the capacitor is most effective when positioned directly on the
board connector. In addition, the parasitic inductance could be kept low by placing at least two vias for the
connection to the GND-layer.
•
C1: This ceramic capacitor helps to improve the EMI and the ESD performance. In combination with L1 and
C10 plus C9 a Pi-filter improves the electro magnetic emission on the Vs-line.
Layout rules are the same as for C_OUT.
Application Note
11
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Design guideline
Figure 6
Example of an half-bridge layout with NovalithICTM (not true to scale)
Other components:
•
T1, D1 and R3: Reverse polarity protection. See Chapter 4.4.
•
R11: Slew rate resistor according to data sheet.
•
C2: Stabilization for slew rate resistor (R11).
Application Note
12
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Design guideline
•
R12: Resistor to generate a current sensing voltage from the IS current.
•
C_IS: Ceramic capacitor for EMI improvement. GND connection with at least two GND-vias. A good value is
1 nF.
In case the current should be measured during the PWM-phase, this capacitor must be adapted to the ONtime inside the PWM-phase.
•
R1 and R2: Device protection in case of µC pins shorted to Vs.
4.2
DC-link capacitor
For the stability of the DC-link voltage a sufficient capacitor is mandatory (in Figure 2, Figure 3 and Figure 5
it is C10). This is one of the most important component in a motor design with semiconductor switches.
The DC-link capacitor could be insufficient, because:
•
The capacitor value is too small.
•
The ESR of the capacitor is too high.
•
When cold the capacitor value is too small.
•
The distance between the DC-link capacitor and the NovalithIC™ is too large.
•
The wiring between the DC-link capacitor and the NovalithIC™ is too long (see Chapter 3).
The value must be chosen carefully, taking the under-voltage toggling into account, which is described in
Chapter 4.2.2.
4.2.1
Calculation of the DC-link capacitor and Pi-filter
As already mentioned in the design- and layout-rules of Figure 5 the voltage ripple at the NovalithIC™ Vs-pin
must not exceed 1 V peak to peak. The necessary DC-link capacitor can be estimated in the following way:
Motor control with PWM means for the DC-link voltage to provide energy pulses during the “ON-phase” of the
PWM cycle. The DC-link pulses are shown in Figure 7.
This energy must be provided by the DC-link capacitor. This can generally be described with
(4.1)
E=
1
⋅ C ⋅V 2 = P ⋅ T
2
(4.2)
C = C DC −link
The voltage at the DC-link capacitor consists of the DC-part and the delta voltage from the supply ripple:
(4.3)
V = VS , DC + ΔVS
The total power in this system consists of the DC-power plus the power of the energy pulse (Epulse), which
provides the energy to the motor during the ON-phase of the half bridge.
(4.4)
P = PDC + ΔP
Application Note
13
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Design guideline
The maximum pulse length is determined by the PWM frequency, theoretically at a duty cycle of 100%:
(4.5)
T = T pulse = TPWM =
1
f PWM
PWM
t
TPWM
IM
∆IOUT
Epulse
Vs
I OUT,min
t
ON
∆VS
VS,DC
t
Figure 7
PWM control (PWM = IN-pin-signal, IM = motor current and VS = VS-pin-voltage @ NovalithIC)
Application Note
14
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Design guideline
Insertion of Equation (4.2) to Equation (4.5) into Equation (4.1)
(4.6)
E=
1
⋅ C DC −link ⋅ (VS , DC + ΔVS ) 2 = ( PDC + ΔP) ⋅ TPWM
2
(4.7)
1
⋅ C DC −link ⋅ (VS2, DC + 2 ⋅ VS , DC ⋅ ΔVS + ΔVS2 ) = PDC ⋅ TPWM + ΔP ⋅ TPWM
2
(4.8)
1
1
⋅ C DC −link ⋅ VS2, DC + C DC −link ⋅ VS , DC ⋅ ΔVS + ⋅ C DC −link ⋅ ΔVS2 = PDC ⋅ TPW M + ΔP ⋅ TPW M
2
2
negligible
Finally the equation to calculate the DC-link capacitor is:
(4.9)
C DC − link ≥
ΔP ⋅ TPWM
V S , DC ⋅ ΔV S
Based on Equation (4.1) and refering to the energy of on single pulse, as marked with Epulse (≈ ΔP • TPWM) in
Figure 7:
(4.10)
ΔP = VS ⋅ I nom ≈ VS ⋅ ( I OUT ,min +
1
ΔI OUT )
2
The DC-link capacitor is primarily the energy buffer for the switching process of the PWM motor control.
Secondly it is part of the Pi-filter. This means first the DC-link capacitor must be calculated according to
Equation (4.9). Based on this, it is recommended that the second capacitor of the Pi-filter C1 be estimated
with:
(4.11)
C1 =
1
1
⋅ C DC − link =
⋅ C 10
10
10
Generally the border frequency of the L1-C1-filter is determined with
(4.12)
fg =
1
2 ⋅ Π ⋅ L1 ⋅ C1
Application Note
15
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Design guideline
We recommend setting the border frequency fg to half the value of the PWM -frequency fPWM.
(4.13)
fg =
1
1
⋅ f PWM =
2
2 ⋅ Π ⋅ L1 ⋅ C1
(4.14)
L1 =
1
Π ⋅
2
2
f PWM
⋅ C1
Summary:
First calculate the DC-link capacitor with Equation (4.9).
Second calculate the other capacitor of the Pi-filter with Equation (4.11).
Then calculate the inductor of the Pi-filter with Equation (4.14).
And last but not least, do not forget the important layout rules and how to measure the supply voltage
correctly.
4.2.2
Under-voltage toggling
The power supply cable of most modules in a car are several meters long. The longer the supply cable is, the
higher its parasitic inductance. In addition, most modules have a Pi-filter at the supply line with a inductor for
EMC reasons. The sum of the supply line inductances have a significant influence on the Vs-voltage. When
switching the motor ON during a normal motor start or PWM control, with a insufficient DC-link capacitor the
supply voltage drops below the under-voltage threshold and the NovalithIC™ is switched to tristate. The
supply voltage recovers above the under-voltage threshold and the NovalithIC™ switches on again, again
dropping below the under-voltage threshold ...
This effect can result in frequencies higher than 100 kHz, as is shown in Figure 8. The device will be damaged
by the power dissipation of the switching losses, which is faster than the reaction time of the over temperature
shut down, because of the high switching frequency.
The under-voltage toggling will be worse if the OUT is shorted to GND.
Application Note
16
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Design guideline
Figure 8
Under-voltage toggling started by short to GND and enabled by an insufficient DC-link
capacitor
With a sufficient DC-link capacitor the supply voltage drop is limited so as not to reach the under-voltage
threshold, as is shown in Figure 9.
Both measurements in Figure 8 and Figure 9 are conducted with the Infineon “NovalithIC Demo Board V2.1”
with BTN7933. The “ON-time” is limed to 100 µs by the IN-signal, as shown in Figure 9. Only the DC-link
capacitor is switched between the two measurements.
Application Note
17
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Design guideline
Figure 9
The sufficient DC-link capacitor avoided under-voltage -toggling in case of a short to GND
4.3
Driving inductive loads over long wires
Inductive loads have a lowpass filter characteristic, like a motor. Because of this, the wire from the NovalithIC™
OUT to the motor injects electro magnetic disturbances into the OUT-pin. This antenna effect increases as the
length of the motor wire increases.
The definition of a long motor wire strongly depends on the application and the environment. To provide a
general idea, wire lengths of approximately 20 cm and more are considered as "long wire". The motor wire
should therefore be as short as possible.
4.3.1
PWM operation
In case of a long motor wire and PWM operation the electro magnetic emission (EME) increases with the wire
length and with the switching speed (inversion of tr(HS), tr(LS), tf(HS) and tf(LS)). In this case it is advantageous to
reduce the switching speed with the slew rate resistor at the SR-pin (see Figure 5, R11). Reducing the switching
speed has probably a impact on the PWM-frequency, which may needs to be adapted. In any case the power
dissipation and the cooling concept needs to be reviewed. The slew rate resistor at the SR-pin should not
exceed the max. slew rate resistor value of the data sheet RSR ≤ 51 kΩ.
Application Note
18
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Design guideline
4.3.2
Current sense
A long motor wire can pick up electro magnetic disturbances which could influence the current sense signal
at the IS-pin. If a high accuracy of the current measurement is needed, it is recommended to use the IS-pin as
status flag diagnosis and perform the current measurement with an external shunt plus current sense
amplifier. An schematic example is shown in Figure 10.
VS
L1
VS
I/O
R2 10kΩ
INH
I/O
R1 10kΩ
IN
I/O
OUT
C9
100nF
C10
470µF/
CIS
220nF
RS
1-5mΩ
SR
R11
C2
0..51kΩ
100nF
CO 2V
220nF
1000µF
IS
R12
1kΩ
C1
47µF/
100µF
R3
10kΩ
BTN89xx
Microcontroller
DZ1
10V
COUT
220nF
M
GND
GND
OP
ADC
Figure 10
BTN89xx with external current measurement
4.4
Reverse polarity protection
The semiconductor technology of NovalithIC™ used has a parasitic PN -diode from “GND” to the supply
voltage pin “Vs”. If the supply voltage is inverted, a huge current will flow through this parasitic PN -diode and
will damage the device. With reverse polarity protection, the reverse current is not possible and the
semiconductor components of the design are protected.
In the schematic in Figure 5, reverse polarity protection is provided with a P-channel MOSFET (IPD90P03P4L04), a zener-diode (D1) and a resistor (R3).
Normal operation Vs > GND:
•
P-MOSFET OFF: The application is supplied by the body-diode of the reverse polarity protection transistor
(IPD90P03P4L-04), e.g. in case of a power-up. The status “P-MOSFET ON” will quickly be reached.
•
P-MOSFET ON: After the power-up in which the body diode was used as a supply path, the zener diode plus
the resistor will generate a gate-source voltage in the range of 10 V and the P-MOSFET is in ON-state. Only
the RDS,on is in the power supply path.
Reverse polarity condition Vs < GND:
•
The gate source voltage of the reverse polarity protection transistor is continuously “LOW” and the
transistor is switched OFF. No current can flow in this state. The application will not be damaged.
Application Note
19
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Design guideline
4.5
Cooling
The NovalithIC™ half-bridge, driving high current generates power dissipation. These are RON losses and
switching losses in case of PWM control, which heat up the device. For details, please see Chapter 7. The
package PG-TO263-7-1 provides a low thermal resistance which can be combined with a heat sink on the PCB
to avoid exceeding the absolute maximum temperature values of the data sheet.
In Figure 6 a cooling area (brown top layer, where the NovalithIC™-OUT is connected) has already been drawn.
Depending on the power dissipation, other thermal sources on the PCB and the ambient temperature, the
cooling needs to be carefully adapted to each application.
In addition the reverse polarity protection transistor T1 (Figure 5 and Figure 6) generates RDS,on power losses
and the cooling concept for this transistor must ensure that the device does not exceed the absolute
maximum junction temperature.
Application Note
20
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
5
Current Sense Improvement
The NovalithICTM half-bridge-family has a current sense function with an IS-pin which provides the output
current divided by a factor, so called dkILIS. The precision of the current measurement could be significantly
improved by eliminating the IS-offset, dkILIS-production spread and respecting the temperature dependency
of the dkILIS.
The table below provides an overview of possible combinations of procedures to reduce current
measurement errors.
Table 1
Current sense procedure and benefits
Procedures
Load current
tolerance
Offset compensation
±28%
Offset compensation
Device dkILIS
measurement
Offset compensation
Device dkILIS
measurement
Temperature estimation
Offset compensation
Device dkILIS
measurement
Temperature compensation ±3%
5.1
±10%
±6%
Characteristic of the dkILIS
The dkILIS has characteristic dependencies. The most important ones with respect to the supply voltage Vs and
with respect to the temperature, are described in this chapter.
5.1.1
Supply voltage dependency of dkILIS
The dependency of the dkILIS of the supply voltage Vs is negligible, as Figure 11 shows. This means the supply
voltage can be ignored when calculating the load current.
Application Note
21
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
Figure 11
dkILIS vs. the supply voltage Vs
5.1.2
TC 1000 life time tests
Life time tests of 1000 hours with a dedicated device stress set up and with many devices from different
production lots showed the dkILIS is decreasing over life time up to -3%.
5.1.3
Temperature drift of the dkILIS
Figure 12 and Figure 13 show the characteristics of the dkILIS vs. temperature and production spread with a
scaling at 25°C, including a series of lab measurement points for one device.
Application Note
22
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
dkILIS(T)/dkILIS(25°C)
Current Sense Improvement
Figure 12
BTN8960 /62 dkILIS vs. temperature
The function f(T) is dependent on the temperature coefficient of the shunt resistance in the control chip (a),
the temperature coefficient of the shunt (b) and DT = T - 25 °C.
Application Note
23
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
dkILIS(T)/dkILIS(25°C)
Current Sense Improvement
Figure 13
BTN8980 /82 dkILIS vs. temperature
The function f(T) is dependent on the temperature coefficient of the shunt resistance in the control chip (a),
the temperature coefficient of the shunt (b) and DT = T - 25 °C.
5.2
Offset compensation
The BTN89xy series is featured with an artificial offset current at the IS-pin. This is shown in Figure 14.
Application Note
24
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
Normal operation:
current sense mode
VS
IIS(offset)
ESD-ZD
IIS~ ILoad
IIS(lim)
Figure 14
IS
Sense
output
logic
RIS VIS
IS-Pin Internal Structure
With this structure, it is possible to always have a measurable offset at IS without a load current. This makes it
easy to measure the offset with the microcontroller, store the offset value and process this in the current
measurement procedure.
The offset must be compensated to allow a precise current measurement with the IS-pin.
The offset should be compensated before activating the load. When an application such as a fuel pump runs
constantly with PWM, you can perform the offset compensation when INH=high and IN=low. In the PWMphase, the best measurement results are achieved just before the rising edge of the IN-signal.
With this procedure, the specified dkILIS of ±28% could be reached, even for small load currents. This includes
production spread, temperature dependency and aging. Most errors are caused by production spread, which
could be compensated by measuring of the dkILIS of each device (device-specific dkILIS). Details of this
approach are described in the relevant chapter.
5.3
Device specific dkILIS
With a measurement of the offset current and one IS-value at a certain load current at 25 °C (e.g. 20 A), it is
possible to determine the individual dkILIS-device and store it permanently to the microcontroller of the
application. With this value, the graphs in Figure 12 and in Figure 13 are valid. The extreme values are
indicated by the blue line (+3sigma):
•
dkILIS-max-C = 1.08 (blue @ -40 °C)
•
dkILIS-min-H = 0.93 (blue @ 150 °C)
Taking into account the aging of the device (see Chapter 5.1.2) the minimum value of Figure 12 and
Figure 13 (blue line) must be reduced by 3% (multiplying 0.97). This means the extreme values are as follows:
•
dkILIS-max-C = 1.08 (blue @ -40 °C)
•
dkILIS-min-H-old = dkILIS-min-H * 0.97 = 0.9
This could be assumed as an error of ±10% including temperature drift and aging.
In this case, the typical value should be assumed as follows:
•
dkILIS-typ = 0.99
Application Note
25
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
The device calibration could be implemented in the module test sequence.
IOUT-20 = 20A
I IS-20 = measured
IOUT-0 = 0A
I IS-0 = measured
(I IS-offset)
dkILIS-device
=
(IOUT-20 – IOUT-0)/(IIS-20 – IIS-0)
Device
calibration
Application
processing
IIS-20
I IS-0
I OUT-0
I OUT-20
IOUT
IIS
10
ROM
%
10 %
µC
IIS
IIS
(I L processing)
I OUT-mes
IOUT-mes
Figure 15
Generating the device fine dkILIS-device.
5.4
Device fine dkILIS and temperature compensation
On the other hand, the dkILIS is dependent on the temperature, which is shown in Figure 12 and Figure 13.
These figures show a characteristic temperature drift with a low content of production spread. This makes it
possible to measure the temperature on the PCB and reduce the temperature dependency by means of a
calculation in the microcontroller. This procedure is illustrated in Figure 16.
Application Note
26
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
IOUT-0 = 0A
I IS-0 = measured
(I IS-offset)
IOUT-20 = 20A
I IS-20 = measured
dkILIS-device
=
(IOUT-20 – IOUT-0)/(IIS-20 – IIS-0)
Production
calibration
Application
processing
IIS-20
I IS-0
I OUT-0
I OUT-20
IOUT
ROM
µC
(I L processing)
IIS
3%
IIS
IIS
3%
IOUT-mes
RAM
Offset calibration
IOUT-mes
Temperature measurement
Figure 16
Load current “IOUT” calculation with temperature compensation
Taking the extreme values from Figure 13:
•
dkILIS-max-C = 1.08 (blue @ -40 °C)
•
dkILIS-min-C = 1.05 (green @ -40 °C)
•
dkILIS-max-H = 0.955 (green @ 150 °C)
•
dkILIS-min-H = 0.925 (blue @ 150 °C)
Multiplying the min. values with a factor of 0.97 (-3% aging) produces the following values:
•
dkILIS-max-C = 1.08 (blue @ -40 °C)
•
dkILIS-min-C-old = 1.0185 (green @ -40 °C)
•
dkILIS-max-H = 0.955 (green @ 150 °C)
•
dkILIS-min-H-old = 0.9 (blue @ 150 °C)
Calculating the typical value for:
•
dkILIS-typ-C = 1.05
•
dkILIS-typ-H = 0.928
These values could be compensated with a temperature measurement and the characteristic from Figure 12
and Figure 13 to provide the value of dkILIS-typ = 1.
With this compensation, the new min. and max. values are:
•
dkILIS-max-C-T = 1.03 (blue @ -40 °C)
•
dkILIS-min-C-old-T = 0.9685 (green @ -40 °C)
Application Note
27
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
•
dkILIS-max-H-T = 1.027 (green @ 150 °C)
•
dkILIS-min-H-old-T = 0.972 (blue @ 150 °C)
After temperature compensation, the min. and max. values are dkILIS-min-H-old-T and dkILIS-max-C-T.
Ultimately, a current measurement with a precision of ±3% could be achieved!
If higher tolerances are acceptable, the temperature measurement can be less precise.
5.4.1
An example of the IIS failure with a rough temperature estimation
Assuming the dkILIS was calibrated during production at 25 °C, the IIS measurement failure could be reduced to
±6%, only by estimating if the temperature is above or below 25 °C. This estimation could be done e.g. by using
the temperature characteristic of the IIS-offset, which is included in the data sheet.
Temperature below 25° C:
•
dkILIS-max-C = 1.08 (blue @ -40 °C)
•
dkILIS-min-25°C = 1
Reducing the min. values with the -3% aging (multiplying with 0.97) the following values will be calculated:
•
dkILIS-max-C = 1.08 (blue @ -40 °C)
•
dkILIS-min-25°C-old = 0.97
For temperatures above 25 °C the calculation method is essentially the same.
Ultimately, a current measurement with a precision of ±6% could be achieved without any external
temperature measurement!
5.5
IS-pin current sensing and fault detection
The BTN8960 /62 /80 /82 provides several additional sense and diagnosis functionalities, which will be
explained here.
5.5.1
Current sense behavior
In comparison to its predecessor BTN79xy, the BTN89xy family's current sense output functionality has an
advanced feature. For illustration purposes, both the BTN7960 and the BTN8960 were deployed in the same
high side switching scenario, where an inductive load to ground was toggled with a duty cycle of 50%. Both
measurements were conducted with the Infineon “NovalithIC™ Demo Board V2.2”. The resulting
measurements are shown in Figure 19 for the BTN7960 and in Figure 18 for the BTN8960. As described in
Figure 14, both types have a similar behavior in the case of an error. Instead, their current sense functionality
differs in normal operating mode. While the BTN79xy blanks the IS output to 0A when the high side MOSFET is
switched off, the BTN89xy provides the offset current IIS(offset) instead.
For monitoring purposes, the behavior of both the BTN79xy and the BTN89xy can be used for continuous
current monitoring, even in freewheeling mode: In bi-directional motor applications with two BTN98xy, the
freewheeling current can be monitored at the high side MOSFET in forward direction. As shown in Figure 17,
the freewheeling current IFW,HS can be observed with both high side MOSFETs being closed. In the scenario
shown, the IS output of the left BTN89xy provides the current dependent signal, while the IFW,HS flows through
the right BTN89xy in reverse direction.
Application Note
28
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
VS
BTN89xx
VS
VS
IFW,HS
BTN89xx
VS
INH
OFF ON
IN
INH
OUT
M
OUT
IS
IN
ON OFF
IS
SR
GND
IFW,LS
SR
GND
Figure 17
Two freewheeling path options for bi-directional motor applications, implemented with
two BTN8960 /62 /80 /82.
5.5.1.1
BTN89yz - advanced current sense and fault diagnosis
In comparison to the BTN79xy, the BTN89xy does not mute the IS current sense output signal, which is always
present. This results in the following behavior and additional diagnostic possibilities:
•
Offset compensation of IIS(offset):
If no current is flowing through the high side MOSFET, the current sense offset IIS(offset) can be monitored at
the IS-pin. This can be ensured while the high side switch is being switched off via the IN-pin and the
freewheeling path doesn't go through the high side MOSFET. If measured, this value can be used for an
online offset calibration of IIS(offset), according to Chapter 5.2. In Figure 18 this scenario is marked with (2).
In the case of a fault condition, the IS-pin will provide a constant current of IIS(lim), which can be clearly
distinguished from the lower offset current IIS(offset).
•
Online calibration of IIS(offset) and continuous current monitoring:
If two BTN89xy devices are deployed in H-bridge configuration, the user can choose between either
monitoring the freewheeling current or the online calibration of IIS(offset) by adapting the freewheeling path
accordingly. An offset calibration of IIS(offset) for both the left and right BTN89xy can be carried out by
choosing a freewheeling path through both low side MOSFETs, with the freewheeling current IFW,LS
displayed in Figure 17. As previously described, the current can be monitored continuously with a
freewheeling current IFW,HS flowing through the two high side MOSFETs.
Application Note
29
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
Figure 18
Measurement of a BTN8960, switching an inductive load to GND. (1): current sense signal,
(2): current sense offset current IIS(offset)
5.5.1.2
BTN79xy current sense limitations
The current is sensed to the IS output pin, if the high side (HS) MOSFET is activated and the INH and IN-pins
are high (marked with (1) in Figure 19). This results in a current dependent IS output signal. For all other cases,
the switching on (3) / off (4) phases of the high side MOSFET and for low IN inputs (2), the IS output signal is 0
A, as shown in Figure 19. In the case of a fault condition, the IS-pin will provide a constant current of IIS(lim) that
can be uniquely identified for a low IN-pin.
Application Note
30
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
Figure 19
Measurement of a BTN7960, switching an inductive load to GND. (1): current sense signal,
(2): current sense functionality switched off
5.5.2
Fault detection
The current sense accuracy depends on the spread of the two parameters dkILIS and IIS(offset). The resulting
maximal, typical and minimal behavior is displayed in Figure 20 for the BTN8960/62 and in Figure 21 for the
BTN8980/82. Here, the limits for the sense current in fault condition IIS(lim) are also shown.
Application Note
31
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
7
max. IIS(lim)
6
typ. IIS(lim)
min. IIS(lim)
IS (mA)
5
4
max. IS
typ. IS
min. IS
3
2
1
0
0
Figure 20
5
10
15
IL − load current (A)
20
25
30
Behavior of the BTN8960/62’s IS output pin for current sense and fault condition according
to parameter tolerances
7
max. IIS(lim)
6
typ. IIS(lim)
min. IIS(lim)
IS (mA)
5
4
max. IS
typ. IS
min. IS
3
2
1
0
0
Figure 21
5
10
15
20
25
30
35
IL − load current (A)
40
45
50
55
Behavior of the BTN8980/82’s IS output pin for current sense and fault condition according
to parameter tolerances
The possibility to distinguish whether a current sense signal or the constant sense current IIS(lim), indicating a
fault condition, can be measured at the IS-pin is also an important issue. Therefore the fault distance between
the two states is further considered. The combined (possible) output options for both states can be seen in
Figure 20 for the BTN8960/62 and in Figure 21 for the BTN8980/82. For a worst case combination of the three
Application Note
32
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
parameters IIS(lim), dkILIS and IIS(offset), provided in the data sheet for the given tolerances, there is a current
range, where it is not possible to distinguish the right operation mode, whether there is a fault or not.
The corresponding break-even point for the BTN8960/62 can be calculated for the load current IL accordingly:
(5.1)
IL = dkILIS · (IIS − IIS(of f set) ) = dkILIS · (IIS(lim) − IIS(of f set) )
(5.2)
IL = 7, 2 · 10 · (4mA−440μA) ≈ 25, 6A
3
For such a system, it wouldn’t be possible to distinguish easily between the fault condition current IIS(lim) and
a current sense signal, for IL > 25 A if the BTN8960/62 is used, and IL > 50 A for the BTN8980/82. For a more
precise consideration, also the temperature dependency of IIS(lim), dkILIS and IIS(offset) has to be considered. For
the given critical area for load currents IL > 25 A, especially the parameters dkILIS and IIS(lim) have the greatest
influence. The temperature dependency of dkILIS is described in Chapter 5.1.3, and of IIS(lim) in
Chapter 5.5.2.1:
•
For a rising temperature, the fault condition current IIS(lim) increases, and vice versa.
•
For a rising temperature the dkILIS decreases and vice versa.
This relationship is also illustrated by Figure 22.
IIS
IIS(lim)
hot
IIS(lim)
IIS(lim)
∆IIS
rising temperature
cold
dkILIS
∆IIS
30A
load current - IL
Figure 22
Illustration of the temperature dependencies of the fault distance and relevant parameters
Additionally the difference between the fault condition current IIS(lim) and the sensed current IIS(IL) can be
calculated as follows:
(5.3)
Application Note
33
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
ΔIIS = IIS(lim) − IIS(IL ) = IIS(lim) −
IL
+ IIS(of f set)
dkILIS
Equation (5.3) shows, that for a rising temperature, both IIS(lim) and IIS(IL) (due to IL / dkILIS) increase.
Combining the spread of dkILIS and IIS(lim) over temperature, this behavior results in a ΔIISthat, at the min.
current limitation detection level ICLx0,min, is typically above 0,5 mA for the BTN8960/62, as shown in Figure 23
and Figure 24 and above 0,75 mA for the BTN8980/82, shown in Figure 25 and Figure 26. To summarize, we
can say that it is possible to distinguish between a current sense signal IIS(IL) and a fault condition current IIS(lim)
for any temperature.
3
2.5
∆IIS (mA)
2
1.5
1
T=−40 °C (456 lots)
0.5
T=150 °C (425 lots)
0
0
Figure 23
50
100
150
200
250
Test Nr.
300
350
400
450
500
Temperature dependent ΔIIS for BTN8960/62, according to Equation (5.3), for the median
value of each lot and temperature at the min. current limitation detection level IL = ICLx0,min
= 30 A.
Application Note
34
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
2
1.8
1.6
1.4
∆IIS (mA)
1.2
1
0.8
0.6
0.4
0.2
T=−40 °C (164 device)
0
0
Figure 24
20
40
60
80
Test Nr.
100
120
140
160
180
Temperature dependent ΔIIS for BTN8960/62, according to Equation (5.3), calculated
individually for each device of lot 447 for −40°C in Figure 23, with IL = ICLx0,min = 30 A.
3
2.5
∆IIS (mA)
2
1.5
1
T=−40 °C (713 lots)
0.5
T=150 °C (642 lots)
0
0
Figure 25
100
200
300
400
Test Nr.
500
600
700
800
Temperature dependent ΔIIS for BTN8980/82, according to Equation (5.3), for the median
value of each lot and temp. at the min. current limitation detection level IL = ICLx0,min = 55 A.
Application Note
35
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
2.5
2
∆IIS (mA)
1.5
1
0.5
T=−40 °C (83 device)
0
0
10
20
30
40
Test Nr.
50
60
70
80
90
Figure 26
Temperature dependent ΔIIS for BTN8982, according to Equation (5.3) calculated
individually for each tested device of lot 85 for −40°C in Figure 25, with IL = ICLx0,min = 55 A.
5.5.2.1
Temperature drift of the IS-pin’s current in fault condition IIS(lim)
The characteristics of the IIS(lim) vs. temperature and production spread is shown in Figure 27 for the
BTN8960/62 and in Figure 28 for the BTN8980/82, including a series of lab measurement points for one device.
Application Note
36
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
7
Lab
a = 4.87
b = 4.3∙ 10‐03
f(T) = a + b∙T
6.5
f(‐40) 456 lots
f(150) 425 lots
6
+ 3σ
IIS(lim) (mA)
‐ 3σ
5.5
5
4.5
4
‐60
Figure 27
‐40
‐20
0
20
40
T (°C)
60
80
100
120
140
160
60
80
100
120
140
160
BTN8960/62 IIS(lim) vs. temperature
7
Lab
a = 4.78
b = 4.1∙ 10‐03
f(T) = a + b∙T
6.5
f(‐40) 630 lots
f(150) 579 lots
6
+ 3σ
IIS(lim) (mA)
‐ 3σ
5.5
5
4.5
4
‐60
Figure 28
‐40
‐20
0
20
40
T (°C)
BTN8980/82 IIS(lim) vs. temperature
Application Note
37
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
5.5.2.2
Failure detection flow chart
The consideration of ΔIIS above provides a procedure for detecting fault conditions (IIS(lim)), which is also
summarized in Figure 29:
•
Calibration of IIS(lim)(T0) for a specific temperature T0: Calculation of offset a with the given / typical slope b.
Ideally measurement of IIS(lim)(T1) for a second temperature T1, to perform a two point calibration and
calculate both offset a and slope b for each individual device.
•
Calculation of temperature dependent IIS(lim)(T) = f(T) while the device is operating according to
Chapter 5.5.2.1.
•
If a current limit of IIS = IIS(lim)(T) - 0,5 mA (BTN8960/62, respectively 0,75 mA for the BTN8980/82) is
exceeded, a fault condition is detected.
7
Calibration (25°C)
6.5
f(T) = a + b∙T
a = 4.69
b = 4.3∙ 10‐03
f(T) – 0,5 mA
6
IIS(lim) (mA)
5.5
5
0,5 mA
4.5
4
3.5
3
‐60
Figure 29
‐40
‐20
0
20
40
T (°C)
60
80
100
120
140
160
One point calibration of IIS(lim) and the resulting fault detection level over temperature for
the BTN8960/62
Additional measures are available for ascertaining fault conditions. Figure 30 describes a possible procedure.
Carrying out a plausibility check after detecting a potential fault allows you to determine if a specific load
current value in the current range of IIS(lim) is possible at a specific operating point.
If this is the case, check whether that value stays in a certain range by performing a series of measurements.
Depending on the application, the scattering of the current sense signal of an electric motor should be much
higher than that of the constant fault current. An additional way of validating a fault condition is by measuring
the IS output pin for a low IN input pin. As illustrated in Figure 17, the fault condition can be monitored by
choosing the low side freewheeling path, ensuring that no current is flowing through the high side MOSFETs.
The fault condition current IIS(lim) can be clearly distinguished from the lower offset current IIS(offset). For
applications running with a PWM duty cycle of 100 %, the duty cycle must be reduced for certain cycles in order
to validate a fault condition. This fault detection procedure is summarized in Figure 30.
Application Note
38
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Current Sense Improvement
no
Measured IS value in fault current range?
yes
Corresponding load current plausible?
no
yes
no
Current value constant over time / several samples?
yes
PWM DC < 100% for no several PWM cycles. Still constant / same current value? yes
No Fault
Figure 30
Fault detected
Possible fault condition validation process flow
Application Note
39
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
6
Switching Timing
For the ADC measurement of the IS-pin, the timing behavior of the BTNx9yz needs to be considered. As the
current sense output is proportional to the current through the high side switch, only the high side switch
behavior is considered here exemplary. The behavior of the low side switch can be considered in an equal
fashion. An overview of the rising and falling switching procedure is shown in Figure 31.
t r(HS ),t ot al
t f(HS ),t ot al
IN
t dr (HS )
t r(HS )
VOUT
t
t df (HS )
t f(HS )
80%
80%
ΔVOUT
ΔVOUT
20%
20%
t
Figure 31
Timing behavior overview of a BTNx9yz high side switch
6.1
Timing behavior for rising edge on high side switch
As shown in the data sheet, the time between the IN-pin rising from a 0 to 1 corresponding voltage level and
the BTN8960 /62 /80 /82 output voltage rising from (around) 0 V to 80 % of the final output voltage (typically:
VOUT ≈ VS) can be summed up to the following delay, as shown in Figure 31:
(6.1)
tr(H S),total = tdr(H S) + tr(H S)
Depending on the chosen resistor value for RSR, both the switch ON delay time tdr(HS) and the rise-time tr(HS) get
affected. The dependencies are shown in Figure 32 (BTN8962TA) / Figure 35 (BTN8982TA) for the switch ON
delay time tdr(HS) and in Figure 33 (BTN8962TA) / Figure 36 (BTN8982TA) for the rise-time tr(HS). The resulting
dependency of the resistor RSR on the total delay time tr(HS),total is displayed in Figure 34 (BTN8962TA) /
Figure 37 (BTN8982TA).
Application Note
40
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
6.1.1
BTN8962TA
tdr(HS) − rising delay−time HSS (μs)
16
14
+ 6σ
typ.
− 6σ
12
10
8
6
4
2
0
0
Figure 32
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the rising delay time of the high side switch
tdr(HS): BTN8962TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
1.8
tr(HS) − rising−time HSS (μs)
1.6
1.4
+ 6σ
typ.
− 6σ
1.2
1
0.8
0.6
0.4
0.2
0
0
Figure 33
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the rising time of the high side switch tr(HS):
BTN8962TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
Application Note
41
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
tr(HS),total − total rising−time HSS (μs)
16
14
+ 6σ
typ.
− 6σ
12
10
8
6
4
2
0
0
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the total rising time of the high side switch with
tr(HS),total = tr(HS) + tdr(HS): BTN8962TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to
Rload), single pulse)
6.1.2
BTN8982TA
tdr(HS) − rising delay−time HSS (μs)
Figure 34
20
15
10
5
0
0
Figure 35
+ 6σ
typ.
− 6σ
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the rising delay time of the high side switch
tdr(HS): BTN8982TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
Application Note
42
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
tr(HS) − rising−time HSS (μs)
2.5
2
1.5
1
0.5
0
0
tr(HS),total − total rising−time HSS (μs)
Figure 36
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the rising time of the high side switch tr(HS):
BTN8982TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
20
+ 6σ
typ.
− 6σ
15
10
5
0
0
Figure 37
+ 6σ
typ.
− 6σ
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the total rising time of the high side switch with
tr(HS),total = tr(HS) + tdr(HS): BTN8982TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to
Rload), single pulse)
Application Note
43
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
6.2
Timing behavior for falling edge on high side switch
For a falling edge on the IN input pin, the delay time between the falling edge of the IN input pin and the lower
deviation of 20 % of the VOUT ≈ VS voltage level of the output pin OUT is considered:
(6.2)
tf (H S),total = tdf (H S) + tf (H S)
The dependencies of the resistor RSR on the delays are shown in Figure 38 (BTN8962TA) / Figure 41
(BTN8982TA) for tdf(HS), Figure 39 (BTN8962TA) / Figure 42 (BTN8982TA) for tf(HS) and resulting in the total
delay time tf(HS),total in Figure 40 (BTN8962TA) / Figure 43 (BTN8982TA).
6.2.1
BTN8962TA
tdf(HS) − falling delay−time HSS (μs)
14
12
10
8
6
4
2
0
0
Figure 38
+ 6σ
typ.
− 6σ
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the falling delay time of the high side switch
tdf(HS): BTN8962TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
Application Note
44
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
1.6
tf(HS) − falling−time HSS (μs)
1.4
+ 6σ
typ.
− 6σ
1.2
1
0.8
0.6
0.4
0.2
0
0
Figure 39
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the falling time of the high side switch tf(HS):
BTN8962TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
tf(HS),total − total falling−time HSS (μs)
14
12
10
8
6
4
2
0
0
Figure 40
+ 6σ
typ.
− 6σ
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the total falling time of the high side switch with
tf(HS),total = tf(HS) + tdf(HS): BTN8962TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to
Rload), single pulse)
Application Note
45
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
6.2.2
BTN8982TA
tdf(HS) − falling delay−time HSS (μs)
18
16
14
+ 6σ
typ.
− 6σ
12
10
8
6
4
2
0
0
Figure 41
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the falling delay time of the high side switch
tdf(HS): BTN8982TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
2
tf(HS) − falling−time HSS (μs)
1.8
1.6
+ 6σ
typ.
− 6σ
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
Figure 42
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the falling time of the high side switch tf(HS):
BTN8982TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
Application Note
46
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
tf(HS),total − total falling−time HSS (μs)
18
16
14
+ 6σ
typ.
− 6σ
12
10
8
6
4
2
0
0
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Figure 43
Dependency of the slew rate resistor RSR on the total falling time of the high side switch with
tf(HS),total = tf(HS) + tdf(HS): BTN8982TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to
Rload), single pulse)
6.3
Timing behavior for rising edge on low side switch
Both the switch ON delay time tdr(LS) and the rise-time tr(LS) depend on the resistance of RSR. The dependencies
are shown in Figure 44 (BTN8962TA) / Figure 46 (BTN8982TA) for the switch ON delay time tdr(LS) and in
Figure 45 (BTN8962TA) / Figure 47 (BTN8982TA) for the rise-time tr(LS), according to the definition from the
data sheet, which is also shown in Figure 31.
Application Note
47
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
6.3.1
BTN8962TA
tdr(LS) − rising delay−time LSS (μs)
20
18
16
+ 6σ
typ.
− 6σ
14
12
10
8
6
4
2
0
Figure 44
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the rising delay time of the low side switch tdf(HS):
BTN8962TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
1.8
tr(LS) − rising−time LSS (μs)
1.6
1.4
+ 6σ
typ.
− 6σ
1.2
1
0.8
0.6
0.4
0.2
0
0
Figure 45
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the rising time of the low side switch tf(HS):
BTN8962TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
Application Note
48
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
6.3.2
BTN8982TA
tdr(LS) − rising delay−time LSS (μs)
25
+ 6σ
typ.
− 6σ
20
15
10
5
0
Figure 46
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the rising delay time of the low side switch tdf(HS):
BTN8982TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
tr(LS) − rising−time LSS (μs)
2.5
2
+ 6σ
typ.
− 6σ
1.5
1
0.5
0
0
Figure 47
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the rising time of the low side switch tf(HS):
BTN8982TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
Application Note
49
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
6.4
Timing behavior for falling edge on low side switch
The dependencies of the resistor RSR on the delays are shown in Figure 48 (BTN8962TA) / Figure 50
(BTN8982TA) for tdf(LS), Figure 49 (BTN8962TA) / Figure 51 (BTN8982TA) for tf(LS), based on the data sheet’s
definition, which is shown in Figure 31.
6.4.1
BTN8962TA
tdf(LS) − falling delay−time LSS (μs)
9
8
7
+ 6σ
typ.
− 6σ
6
5
4
3
2
1
0
0
Figure 48
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the falling delay time of the low side switch
tdf(LS): BTN8962TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
Application Note
50
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
1.8
tf(LS) − falling−time LSS (μs)
1.6
1.4
+ 6σ
typ.
− 6σ
1.2
1
0.8
0.6
0.4
0.2
0
0
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Figure 49
Dependency of the slew rate resistor RSR on the falling time of the low side switch tf(LS):
BTN8962TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
6.4.2
BTN8982TA
tdf(LS) − falling delay−time LSS (μs)
12
10
8
6
4
2
0
0
Figure 50
+ 6σ
typ.
− 6σ
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Dependency of the slew rate resistor RSR on the falling delay time of the low side switch
tdf(LS): BTN8982TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
Application Note
51
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High Current PN Half Bridge
Switching Timing
tf(LS) − falling−time LSS (μs)
2.5
+ 6σ
typ.
− 6σ
2
1.5
1
0.5
0
0
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Figure 51
Dependency of the slew rate resistor RSR on the falling time of the low side switch tf(LS):
BTN8982TA (VS = 13,5 V, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse)
6.5
Error of total delay time
The resulting relative error for the ±6σ values, compared to the typical tx(HS),total value, is summarized in
Figure 52 (BTN8962TA) / Figure 53 (BTN8982TA). The error is calculated as follows:
(6.3)
tx(H S),min/max − tx(H S),typ
rel.error =
tx(H S),typ
This parameter spread needs to be taken into account especially for short PWM cycle times, respectively high
PWM frequencies. If the relative tr(HS),total / tf(HS),total error is in the same order of magnitude as the application’s
PWM cycle time, a separate calibration can be considered to measure the delay times of the individual BTx9yz
devices.
Application Note
52
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High Current PN Half Bridge
Switching Timing
50
40
rel. error tx(HS)total (%)
30
20
6σ tf(HS)total
10
6σ tr(HS)total
0
−6σ tr(HS)total
−10
−6σ tf(HS)total
−20
−30
−40
−50
0
Figure 52
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Relative error of the total delay time tr(HS),total for rising and tf(HS),total for falling edges.
Relative error according to Equation (6.3) for BTN8962TA (VS = 13,5 V, Rload = 2 Ω 30 µH < Lload
< 40 µH (in series to Rload), single pulse)
60
50
rel. error tx(HS)total (%)
40
30
20
6σ tf(HS)total
10
6σ tr(HS)total
0
−6σ tr(HS)total
−10
−6σ tf(HS)total
−20
−30
−40
−50
0
Figure 53
5
10
15
20
25
RSR (kΩ)
30
35
40
45
50
Relative error of the total delay time tr(HS),total for rising and tf(HS),total for falling edges.
Relative error according to Equation (6.3) for BTN8982TA (VS = 13,5 V, Rload = 2 Ω 30 µH < Lload
< 40 µH (in series to Rload), single pulse)
Application Note
53
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High Current PN Half Bridge
Switching Timing
6.6
Delay time calibration
One possibility to determine the total rising time tr(HS),total and the falling time tf(HS),total respectively, is by
measuring the time once in an end of line test. For such a (single) measurement, the influence of certain
parameters like the supply voltage or the load current has to be considered as well and the test setup has to
be adjusted accordingly.
It is also possible to use continuous calibration during operation. With such a method, the influence of
changing outside parameters is constantly taken into account.
In the following two chapters, an output voltage (Chapter 6.6.1) and current sense based calibration
(Chapter 6.6.2) is suggested.
6.6.1
Output voltage based calibration
This method can be implemented if both the supply voltage VS and the BTN8960 /62 /80 /82’s output voltage
VOUT at the OUT-pin are measured. In that case it would be possible to measure the time between setting the
IN input pin from low to high (or from high to low for tf(HS),total) and the point of time, the output voltage VOUT is
greater than or equal to 0,8 VS. The measurement procedure is illustrated in Figure 54.
The procedure for the total falling delay time tf(HS),total measurement can be performed in a similar fashion: the
delay time between the falling edge of the IN-pin and the lower deviation of 20 % of the VOUT ≈ VS voltage level
is considered.
If these two voltage levels are monitored during operation, an online calibration can be performed
periodically, too.
Start timer
IN
t
Event generation (Interrupt)
VOUT
Upper Boundary
VS·80%
Stop timer
t
tr(HS),total
Figure 54
Measurement procedure for the total rising time tr(HS),total based on two voltage
measurements
Application Note
54
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BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
6.6.2
Current sense based calibration
Two different calibration methods are available when only the current sense signal is monitored. One of these
can be implemented as an end of line test, while the other is performed during live operation.
Microcontroller
I/O
WO
Reset
RO
Vdd
XC866
Vss
I/O
I/O
CQ
22µF
Q
D
(IPD90P03P4L-04)
TLE
4278G
C9
100nF
C10
470µF
CO2V
220nF
OUT
COUT
220nF
IS
Figure 55
C1
100nF
BTN89xxTA
IN
R12
1kΩ
DZ1
10V
R3
10kΩ
INH
CIS
1nF
L1
CI
470nF
GND
VS
R1
10kΩ
VS
I
CD
47nF
I/O
R2
10kΩ
Reverse Polarity
Protection
Voltage Regulator
Rtest
SR
R11
C2 0..51kΩ
100nF
GND
End of line test setup for timing calibration with ohmic load Rtest
To determine the delay for a rising edge tr(HS),total, the voltage limit is set to the corresponding current level,
which is reached with a voltage drop of 80 % of VOUT ≈ VS over the test resistor Rtest, as shown in the test setup
in Figure 55. As this test is based on the concurrency of the output voltage and current IL, only an ohmic load
should be used. This setup results in the direct proportional context of IL = VS ⁄ Rtest and with the current sense
function from Figure 5.5:
(6.4)
IIS =
IL
Vs
+ IIS(of f set) =
+ IIS(of f set)
dkILIS
dkILIS · Rtest
The resulting voltage VADC on the microcontroller’s ADC input pin (according to Figure 55):
(6.5)
VADC = R12 · IIS =
Vs · R12
+ IIS(of f set) · R12
dkILIS · Rtest
This means that the comparator threshold should be set to a corresponding voltage level of:
(6.6)
VADC,80%Vs = 0, 8 ·
Application Note
Vs · R12
+ IIS(of f set) · R12
dkILIS · Rtest
55
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High Current PN Half Bridge
Switching Timing
This procedure allows to measure the input delay tr(HS),total with a microcontroller’s ADC in a predefined end of
line test, with a known resistor Rtest. The test is summarized in Figure 56. The time measurement is started in
parallel to the rising edge of the IN input pin. If the voltage level of VADC, as described in Equation (6.6), is
reached, the resulting delay time tr(HS),total can be calculated.
Start timer
IN
t
VOUT
( = Rtest·I L)
VS·80%
VADC =
R12·I IS
Event generation
t
Upper Boundary
80%
Stop timer
t
tr(HS),total
Figure 56
Measurement procedure for the total rising time tr(HS),total based on a current sense
measurement
This procedure, which is described here for a rising edge, can be implemented in a similar manner to measure
the total delay for a falling edge, tf(HS),total, on the IN-pin, too.
6.7
ADC Timing for current measurement
One way to measure the current value for motor control applications is in the center of the PWM duty cycle.
The corresponding measuring time frame is summarized in Figure 57. Based on the value of resistor RSR, the
time frame is limited by the worst case (min./max.) switching times, tf(HS),total,min and tr(HS),total,max. Alternatively,
the timing could be based on the delay time calibration/measurement described in the previous Chapter 6.6.
Application Note
56
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High Current PN Half Bridge
Switching Timing
6.7.1
Current sense ADC timing
Based on Figure 57, the time window for an ADC measurement th(HS),meas for a high output signal can be
calculated as follows:
(6.7)
th(H S),meas = TON + tdf (H S),min − tr(H S),total,max
As previously described, the on-time TON is based on the following relationship:
(6.8)
TON = TP W M · DC
TPWM is the PWM-period-time (TPWM = 1 / fPWM) and DC corresponds to the duty cycle. This results in:
(6.9)
th(H S),meas = TP W M · DC + tdf (H S),min − tr(H S),total,max
If the measurement should be started in the center of the ADC time window th(HS),meas, the sample delay tsample
has to be set to the following:
(6.10)
tsample = tr(H S),total,max +
th(H S),meas
2
If the ADC measurement time window should be placed right in the center of th(HS),meas for a given ADC
conversion time tADC, the sample delay time tsample can be calculated as follows:
(6.11)
tsample = tr(H S),total,max +
th(H S),meas − tADC
2
This measurement scenario is illustrated in Figure 57.
Application Note
57
Rev. 0.4, 2015-07-02
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High Current PN Half Bridge
Switching Timing
TON
IN
tr(HS),total,max
th(HS),meas
tr(HS),total
VOUT
t
tdf(HS)
tdf(HS),min
80 %
ADC
20 %
∆tr(HS),total
tADC
t
tsample
Figure 57
Timing for current measurement for high input on IN-pin, with ideal ADC sampling time
window
6.7.2
Offset current calibration ADC timing
With an additional ADC measurement at low input signals, an online compensation of the IS-pin’s offset
current IIS(offset) can be executed. Based on Figure 58 and comparable to the current measurement in the
previous Chapter 6.7.1, the different sampling timings for a low input level can be calculated in a similar
fashion. The time window of the ADC measurement tf(HS),meas for a low output signal can be calculated as
follows:
(6.12)
tf (H S),meas = TP W M · (1 − DC) + tdr(H S),min − tf (H S),total,max
If the ADC measurement should be triggered right in the center of the time window th(HS),meas, the required
sample delay t ’sample can be calculated according to Figure 58:
(6.13)
tsample = tf (H S),total,max +
tf (H S),meas
2
The resulting trigger point with the sample delay time t ’sample is marked in Figure 58 (red).
Application Note
58
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High Current PN Half Bridge
Switching Timing
If the ADC sampling window should be placed in the center of th(HS),meas, the sample delay time t ’sample should
be set to:
(6.14)
tsample = tf (H S),total,max +
tl(H S),meas − tADC
2
In the case of a fault condition, the IS-pin will provide a constant current of IIS(lim), instead of the current sense
functionality. This current IIS(lim) can be clearly distinguished from the lower offset current IIS(offset). Further
details are described in Chapter 5.5.1.1.
IN
TOFF
t
tf(HS),total,max
tl(HS),meas
tf(HS),total
VOUT
tdr(HS),min
tdr(HS)
80 %
20 %
∆tf(HS),total
t
t'sample
Figure 58
Timing for current measurement for low input on IN-pin
6.8
Allowed PWM setup for current sense ADC measurements
Based on the previous Chapter 6.7, a relationship between the lowest possible duty cycle DCmin,
corresponding to the minimal time TON,min, and the PWM frequency can be set up. The worst case (max.) ADC
conversion time window is tADC,max. For a worst case analysis, the following assumption must be respected in
any case, as the time window for the ADC measurement th(HS),meas, according to Equation (6.9), has to be
greater than tADC,max:
(6.15)
tADC,max ≤ TP W M · DC + tdf (H S),min − tr(H S),total,max
For certain typical values for resistor RSR (1 kΩ 5 kΩ 10 kΩ) and certain maximal ADC conversion times tADC,max,
the minimal duty cycles should be respected, as shown in Figure 59 (BTN8962TA) / Figure 62 (BTN8982TA) for
Application Note
59
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
RSR = 1 kΩ, Figure 60 (BTN8962TA) / Figure 63 (BTN8982TA) for RSR = 5 kΩ and Figure 61 (BTN8962TA) /
Figure 64 (BTN8982TA) for RSR = 10 kΩ.
6.8.1
BTN8962TA
50
45
min. duty cycle (%)
40
tADC max = 0.5 µs
tADC max = 1.0 µs
tADC max = 2.0 µs
35
tADC max = 5.0 µs
30
tADC max = 10 µs
25
20
15
10
5
0
0
Figure 59
2
4
6
8
10
fPWM (kHz)
12
14
16
18
20
Minimal allowed duty cycle DCmin for a given PWM frequency fPWM, a ADC conversion time tADC
and RSR = 1 kΩ, for BTN8962TA
50
45
min. duty cycle (%)
40
tADC max = 0.5 µs
tADC max = 1.0 µs
tADC max = 2.0 µs
35
tADC max = 5.0 µs
30
tADC max = 10 µs
25
20
15
10
5
0
0
Figure 60
2
4
6
8
10
fPWM (kHz)
12
14
16
18
20
Minimal allowed duty cycle DCmin for a given PWM frequency fPWM, a ADC conversion time tADC
and RSR = 5 kΩ, for BTN8962TA
Application Note
60
Rev. 0.4, 2015-07-02
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High Current PN Half Bridge
Switching Timing
50
45
min. duty cycle (%)
40
tADC max = 0.5 µs
tADC max = 1.0 µs
tADC max = 2.0 µs
35
tADC max = 5.0 µs
30
tADC max = 10 µs
25
20
15
10
5
0
0
2
4
6
8
10
fPWM (kHz)
12
14
16
18
20
Figure 61
Minimal allowed duty cycle DCmin for a given PWM frequency fPWM, a ADC conversion time tADC
and RSR = 10 kΩ, for BTN8962TA
6.8.2
BTN8982TA
55
50
45
min. duty cycle (%)
40
35
tADC max = 0.5 µs
tADC max = 1.0 µs
tADC max = 2.0 µs
tADC max = 5.0 µs
tADC max = 10 µs
30
25
20
15
10
5
0
0
Figure 62
2
4
6
8
10
fPWM (kHz)
12
14
16
18
20
Minimal allowed duty cycle DCmin for a given PWM frequency fPWM, a ADC conversion time tADC
and RSR = 1 kΩ, for BTN8982TA
Application Note
61
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
55
50
45
min. duty cycle (%)
40
35
tADC max = 0.5 µs
tADC max = 1.0 µs
tADC max = 2.0 µs
tADC max = 5.0 µs
tADC max = 10 µs
30
25
20
15
10
5
0
0
Figure 63
2
4
6
8
10
fPWM (kHz)
12
14
16
18
20
Minimal allowed duty cycle DCmin for a given PWM frequency fPWM, a ADC conversion time tADC
and RSR = 5 kΩ, for BTN8982TA
55
50
45
min. duty cycle (%)
40
35
tADC max = 0.5 µs
tADC max = 1.0 µs
tADC max = 2.0 µs
tADC max = 5.0 µs
tADC max = 10 µs
30
25
20
15
10
5
0
0
Figure 64
2
4
6
8
10
fPWM (kHz)
12
14
16
18
20
Minimal allowed duty cycle DCmin for a given PWM frequency fPWM, a ADC conversion time tADC
and RSR = 10 kΩ, for BTN8982TA
Application Note
62
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BTN8960 /62 /80 /82
High Current PN Half Bridge
Switching Timing
6.8.3
Example calculation
For an example application with the BTN8962TA ,the following parameter values are assumed:
•
PWM frequency fPWM= 20 kHz, resulting in TPWM= 1 / fPWM = 50µs
•
DCmin= 25 %
•
RSR = 1 kΩ resulting in tdf(HS),min = 1,971 µs and tr(HS),total,max = 4,321 µs
This setup results in the max. ADC conversion time window tADC,max:
(6.16)
tADC,max = TP W M · DC + tdf (H S),min − tr(H S),total,max
(6.17)
tADC,max = 50μs · 0, 25 + 1, 971μs − 4, 321μs ≈ 10, 2μs
Application Note
63
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High Current PN Half Bridge
Power dissipation
7
Power dissipation
The device dissipates some power. This power dissipation is generated in the top chip and in the individual
MOSFETs. The high currents in the MOSFETs generate most of the power dissipation. The following
consideration is based on several assumptions, so the result is ultimately an estimation which should help you
understand the general trend.
The power dissipation in the MOSFETs consists mainly of conducted losses and switching losses. Losses in the
body diode only occur during the cross current protection phase. They are therefore not taken into
consideration.
7.1
Power dissipation of the control chip (top chip)
The control chip consumes a certain amount of current, and this causes power dissipation.
In DC-mode the following equation describes the power dissipation in the control chip:
(7.1)
PCC − DC = ( I Vs ( ON ) + I IS ) ⋅ V S
In PWM-mode, an additional current is needed to charge/discharge the MOSFET gates. This leads to the
following PWM power dissipation:
(7.2)
PCC − PWM = Q tot ⋅ V S ⋅ f PWM
The gate charges for the BTN89xx are specified in the table below:
Table 2
Qtot of BTN896x and BTN898x
Product
Total gate charge
BTN8960 /62
450 nC
BTN8980 /82
550 nC
Power dissipation in the control chip can be calculated as follows:
(7.3)
PCC = PCC − DC + PCC − PWM = ( IVs ( ON ) + I IS ) ⋅ V S + Q tot ⋅ V S ⋅ f PWM
7.2
Conduction power dissipation
In the ON-state, a MOSFET has a specific RON which is listed in the data sheet. RON is different for the high side
(HS) and the low side (LS) MOSFETs. This means that RON must be selected according to the driving situation.
A current flowing through this transistor generates the following conducted losses:
(7.4)
PCL = I 2 ⋅ R ON
In case the NovalithIC™ is driven in a static condition, Equation (7.4) can be used to estimate the static
conducted losses for the high side or low side MOSFET.
Application Note
64
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Power dissipation
7.3
Power dissipation due to switching
With PWM control, switching losses need to be taken into account because they generate most of the power
dissipation for high PWM frequencies. The NovalithICTM devices are designed to drive motors or other
inductive loads. This chapter deals with switching losses that are generated while driving an inductive load.
VDS(HS)
I HS
ILS
Vs
S
HS
I HS
ONBOFF
D
OUT
D
LS
OFF
VDS(HS)
VOUT
S
ESL
VRon,act
M
tSL1
tHS-off
VOUT
IOUT
ILS
GND
ESL
tHS-off
Figure 65
t
tSL2
VBE
VRon,FW
t
High Side switching scenario of BTN8960 /62 /80 /82
The current in an inductor cannot be changed abruptly (rule of Lenz). As shown in Figure 65, the current in the
high side (HS) MOSFET is driven by the motor inductance as long as the OUT voltage drops one VBE below GND
and the current is flowing through the body diode of the low side (LS) MOSFET. This means that the current IHS
is flowing in the high side (HS) MOSFET, even though this is in linear mode during tHS-off.
The NovalithICTM has a cross-current protection mechanism which ensures that an output MOSFET is turned
on only when the other one is off. This causes a free wheeling current through the MOSFET body diode (VBE in
Figure 65) before the resistive path is switched on. The power dissipation caused by the body diode is
negligible and thus not taken into account in this estimation.
The rise- and fall- time in the data sheet is the period during which the output voltage decreases from 80% to
20%. In order to determine the switching losses, we need to determine the time required to decrease the
output voltage from 100% to 0%. The tHS-off can be estimated from the data sheet parameters with the
Equation (7.5) accordingly.
(7.5)
t HS − off =
t f ( HS )
0 .5
Factor 0.5 is related to ∆VOUT from 0% to 100%
For the other switching times (tHS-on, tLS-off and tLS-on) Equation (7.5) can be used to perform the same
calculation using the corresponding data sheet parameters (tr(HS), tf(LS) and tr(LS)).
Other assumptions, with a minor effect on the result, include the following:
•
The load current during the switching process is constant.
•
VOUT and VDS(HS) have linear behaviour.
Application Note
65
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Power dissipation
•
The switching times are assumed as equal and in the following always referred to as tHS-off.
The switching energy ESL is shown in Figure 65 and can be estimated using Equation (7.6) below:
(7.6)
E SL =
t SL 2
∫ V S ⋅ I OUT ⋅ dt =
t SL 1
V S ⋅ I OUT
⋅ t HS − off
2
From the switching energy ESL the average power loss PSL can be determined with two switching times per
PWM period. This is shown in Equation (7.7):
(7.7)
PSL =
7.4
V S ⋅ I OUT
⋅ 2 ⋅ t HS − off ⋅ f PWM = V S ⋅ I OUT ⋅ t HS − off ⋅ f PWM
2
Entire power dissipation of the MOSFETs
The average power dissipation in PWM-mode consists of the switching losses plus the conducted losses, as
shown in Figure 66. We must take into account that the losses occur in the high side (HS) and low side (LS)
MOSFET. In the example of Figure 65, where the motor is connected to GND, the switching losses occur in the
high side (HS) MOSFET. The conducted losses occur in the high side (HS) MOSFET during the ON-phase and in
the low side (LS) MOSFET in the free wheeling phase, as shown in Figure 66.
In PWM-mode, the PWM-period-time is:
(7.8)
T PWM =
1
f PWM
The duty cycle (DC) of the PWM-mode is the relation between the ON-time and the PWM-period-time in
percent.
(7.9)
DC =
T ON
T PWM
Application Note
66
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Power dissipation
VIN
TON = TPWM · DC
t
TPWM
conducted
losses
(ON-phase )
switch ing
lo sse s
switch ing
lo sse s
VOUT
conducted
losses
(free wheeling )
t
actuator losses
Figure 66
Entire power dissipation of BTN8960 /62 /80 /82 with the motor connected to GND
In Chapter 7.4.2 and Chapter 7.4.3 the power dissipation is estimated separately for the high side (HS) and
low side (LS) MOSFET.
7.4.1
PWM control and the duty cycle constraints
If tFW is close to or below zero, no freewheeling occurs. VOUT does not go below GND. This means that only
switching losses are generated. Thus, a duty cycle generating tFW ≤ 0 is insufficient to control the motor current
and therefore not taken into account in the following calculations. In this case, the high side (HS) MOSFET
should be permanently on.
The same is valid for tON ≤ 0. In this case, the low side (LS) MOSFET should be permanently on.
Extremely low or high duty cycle values required by real applications can be achieved by increasing the
switching speed and/or by increasing TPWM.
7.4.2
Entire power dissipation in the actuator MOSFET
In the motor-to-GND scenario the actuator MOSFET is the high side (HS) MOSFET, as in Figure 65 and in motorto-Vs scenario, the actuator MOSFET is the low side (LS) MOSFET. The entire power dissipation consists of two
times the switching losses plus the cunducted losses in the ON-phase, as shown in Figure 66. The time of the
ON-phase in PWM-mode is provided by the following formulae:
(7.10)
t ON = TON − t HS − on
As mentioned in “Other assumptions,” on Page 65 switching times are assumed as equal and named as tHSoff:
(7.11)
t ON = T ON − t HS
Application Note
− off
67
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Power dissipation
Equation for estimate the total conducted energy in the actuator MOSFET:
(7.12)
2
E act = 2 ⋅ E SL + E ON = V S ⋅ I OUT ⋅ t HS − off + I OUT
⋅ RON ,act ⋅ t ON
From Equation (7.12) the average power dissipation in the actuator MOSFET can be determined by
multiplying Equation (7.12) by fPWM:
(7.13)
2
Pact = E act ⋅ f PWM = (V S ⋅ I OUT ⋅ t HS − off + I OUT
⋅ RON ,act ⋅ t ON ) ⋅ f PWM
Equation (7.13) is an estimation of the average power dissipation in the actuator MOSFET. In Figure 65, this
is the high side (HS) MOSFET.
7.4.3
Entire power dissipation in the freewheeling MOSFET
In the motor-to-GND scenario , the freewheeling MOSFET is the low side (LS) MOSFET, as in Figure 65, and in
the motor-to-Vs scenario, the freewheeling MOSFET is the high side (HS) MOSFET. The entire power dissipation
consists of the conducted losses in the freewheeling phase, as shown in Figure 66. The duration of the
freewheeling phase in PWM-mode is provided by the equation below:
(7.14)
t FW = T PWM − TON − t HS − off
Important note: For the proper use of Equation (7.14) refer to Chapter 7.4.1.
Equation to determine the entire freewheeling energy in the freewheeling MOSFET:
(7.15)
2
2
E FW = I OUT
⋅ RON ,FW ⋅ t FW = I OUT
⋅ RON ,FW ⋅ (TPWM − TON − t HS − off )
From Equation (7.15) the average power dissipation in the freewheeling MOSFET can be determined by
multiplying Equation (7.15) by fPWM:
(7.16)
2
PFW = E FW ⋅ f PWM = I OUT
⋅ RON , FW ⋅ (TPWM − TON − t HS − off ) ⋅ f PWM
Equation (7.16) is an estimation of the average power dissipation in the freewheeling MOSFET. In Figure 65,
this is the low side (LS) MOSFET.
7.5
Entire power dissipation in the NovalithICTM
To determine the entire power dissipation in the NovalithICTM, combine Equation (7.13), Equation (7.16) and
Equation (7.3).
(7.17)
P Nova = Pact + PFW + PCC
Application Note
68
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Power dissipation
Equation (7.17) is the average of the different power losses in one PWM period, as shown in Figure 66, plus
the power losses in the control chip.
7.6
Simplifications
Because the losses in the control chip are typically negligible in comparison with the losses in the MOSFETs,
they are neglected in this simplification.
Taking into account that the high side (HS) and the low side (LS) MOSFET are in a similar RON range, the
equation for determining the entire power dissipation in the NovalithICTM can be significantly reduced by
using the same RON for both the high side (HS) and the low side (LS) MOSFET. The more conservative approach
is to use the higher RON of both.
The idea behind this is to have the same RON for the conducted losses of the ON- and the freewheeling phase,
according to Figure 66. Due to this simplification the energy in one PWM- period is two times the switching
losses ESL and RON losses during the remaining time:
(7.18)
E Nova = 2 ⋅ E SL + PCL ⋅ (T PWM − 2 ⋅ t HS − off )
(7.19)
E Nova = 2 ⋅
V S ⋅ I OUT
2
⋅ t HS − off + I OUT
⋅ RON ⋅ (T PWM − 2 ⋅ t HS − off )
2
From the the simplyfied NovalithICTM energy to the simplified NovalithICTM power dissipation by multiplying
Equation (7.19) by fPWM:
(7.20)
2
PNova , S = (V S ⋅ I OUT ⋅ t HS − off + I OUT
⋅ RON ⋅ (TPWM − 2 ⋅ t HS − off )) ⋅ f PWM
Application Note
69
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Thermal Performance
8
Thermal Performance
The PCB used for the simulation is compliant with JEDEC 2s2p (JESD 51-5, JESD 51-7) and JEDEC 1s0p (JESD
51-3), as described in Table 3. For 1s0p, a cooling area of 600 mm2 and 300 mm2 is additionally considered.
Table 3
PCB specification
λtherm [W/m • K]
Dimensions
76.2 × 114.3 × 1.5 mm3
Material
FR4
0.3
Metalization
JEDEC 2s2p (JESD 51-7) + (JESD 51-5)
JEDEC 1s0p (JESD 51-3) + Cooling Area
388
Cooling Area
600 mm2, 300 mm2, footprint
Thermal Vias
Ø = 0.3 mm; plating 25 µm; 40 pcs.
Package Attach [50 µm]
Solder
55
The cross section of JEDEC 2s2p is shown in Figure 67.
70µm‚ modeled (traces)
1,5 mm
35µm / 100%*
4 layer PCB
35µm / 100%*
70µm / 5%*
*: means percentual Cu metalization on each layer
Figure 67
Cross section JEDEC 2s2p
The cross section of JEDEC 1s0p is shown in Figure 68.
1,5 mm
70µm‚ modeled (traces, cooling area)
4 layer PCB
70µm / 5%*
*: means percentual Cu metalization on each layer
Figure 68
Cross section JEDEC 1s0p
Application Note
70
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Thermal Performance
8.1
Zth simulation results
80
70
Zth-ja [K/W]
60
50
LSS - 1s0p / 600mm²
HSS - 1s0p / 600mm²
LSS - 1s0p / 300mm²
HSS - 1s0p / 300mm²
LSS - 1s0p / footprint
HSS - 1s0p / footprint
40
30
LSS - 2s2p
HSS - 2s2p
20
10
0
0.00001
0.001
0.1
10
1000
time [sec]
Figure 69
Zth-ja for BTN8960/62, in PG-TO263-7-1, (LSS: low side switch, HSS: high side switch)
80
70
Zth-ja [K/W]
60
50
LSS - 1s0p / 600mm²
HSS - 1s0p / 600mm²
LSS - 1s0p / 300mm²
HSS - 1s0p / 300mm²
LSS - 1s0p / footprint
HSS - 1s0p / footprint
40
30
LSS - 2s2p
HSS - 2s2p
20
10
0
0.00001
0.001
0.1
10
1000
time [sec]
Figure 70
Zth-ja for BTN8980/82, in PG-TO263-7-1, (LSS: low side switch, HSS: high side switch)
Application Note
71
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Thermal Performance
2.5
BTN8980/82TA - LSS
BTN8980/82TA - HSS
BTN8960/62TA - LSS
BTN8960/62TA - HSS
Zth-jc [K/W]
2.0
1.5
1.0
0.5
0.0
0.00001
0.001
0.1
10
1000
time [sec]
Figure 71
Zth-jc for BTN8960/62/80/82, in PG-TO263-7-1, (LSS: low side switch, HSS: high side switch)
8.2
Thermal RC-network
The thermal behavior of the BTN89xy can be simulated based on the thermal RC-network shown in Figure 72.
The abbreviations can be found in Table 4.
Table 4
Abbreviations for the thermal RC-network of BTN89xy
Abbreviation
Description (temperature level)
GND
thermal ground, corresponds to ambient temperature
CC
Control chip with temperature sensor for overtemperature detection
LS
low side MOSFET
HS
high side MOSFET
Application Note
72
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Thermal Performance
CC
C5
C4
R4
R5
C23
C24
R25
R1
R26
R2
R3
C13
LS
C14
R15
C10
C1
C2
C3
HS
R6
R10
R9
C6
R11
C15
R16
C12
R14
C16
R17
C11
R7
R12
C7
R13
R18 C17
R20
R21
R22
R8
R19
C8
C18
C19
C20
R23
Figure 72
Schematic of the thermal RC-network for BTN89xy
Application Note
73
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Thermal Performance
8.2.1
Parameters for BTN8960/62
For the thermal RC-network, which is shown in Figure 72, the values of the BTN8960/62 for the resistors can
be found in Table 5 and for the capacities in Table 6, depending on the test condition (PCB).
Table 5
Thermal RC-network resistor values for BTN8960/62
Parameter
1s0p
2s2p
300 mm2
600 mm2
R1
4.13479
6.14635
4.36197
3.28848
R2
9.49529
6.99412
8.86409
10.2156
R3
6.04676
6.24923
6.00779
5.73654
R4
1997.68
1999.98
9989.45
9989.4
R5
24.6962
14.3669
26.5405
23.2126
R6
0.765526
0.825716
0.784931
0.793983
R7
709.461
21.7132
712.375
703.027
R8
24.0397
959.748
98.4013
83.6365
R9
0.509237
0.277148
0.267684
0.257237
R10
0.0201271
0.219217
0.159445
0.17652
R11
0.0134086
0.753008
0.0120334
0.0123115
R12
48.4465
75.4798
187.262
157.461
R13
2.15834
0.703103
41.9972
47.1135
R14
827.333
312.256
793.297
744.845
R15
1.89889
1.16198
1.93861
1.90089
R16
5.67666
1.27492
3.89945
3.75373
R17
30.7871
257.22
3.29846
4.09169
R18
954.388
1715.55
685.267
466.671
R19
0.666271
183.372
1.66419
2.4898
R20
9.17544
11.5243
49.7984
49.454
R21
8.86655
132.758
4.50777
5.96947
R22
3.64248
4.55264
20.7864
22.0143
R23
1.54282
47.1593
9.53249
12.2849
R25
0.0115874
0.0111131
0.0120082
0.0107333
R26
59.2163
3.41491
16.2884
10.0589
Application Note
74
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Thermal Performance
Table 6
Thermal RC-network capacitor values for BTN8960/62
Parameter
1s0p
2s2p
300 mm2
600 mm2
C1
9.01E-07
8.11E-06
9.00E-06
1.33E-05
C2
0.0096747
0.00768932
0.00857854
0.0093771
C3
0.00328475
0.00461763
0.00376799
0.00326148
C4
0.00117103
0.0011541
0.0011511
0.00116079
C5
1.92349
0.419775
2.01168
2.98621
C6
0.259815
0.361034
0.236595
0.25227
C7
2.30445
1.17886
0.502516
0.85818
C8
0.0924509
0.169357
0.147342
0.233769
C10
0.0759261
0.000081424
0.146105
0.138098
C11
0.874947
0.681589
0.005741
0.00594316
C12
0.0219339
0.641786
0.40078
0.441664
C13
0.00211971
0.00072605
0.00200476
0.00193489
C14
0.0518487
0.0149359
0.0742448
0.0420656
C15
0.45993
0.0446105
0.746801
0.67808
C16
0.264822
0.17218
0.253172
0.228248
C17
2.00613
0.960968
0.182447
0.152115
C18
0.0477427
0.157112
0.3562
0.3517
C19
2.21387
7.70672
1.95155
1.56875
C20
5.75675
17.92
2.706
1.05419
C23
0.482909
0.455128
0.00175319
0.00109187
C24
0.00483449
0.00210439
0.0014892
0.00143505
Application Note
75
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Thermal Performance
8.2.2
Parameters for BTN8980/82
For the thermal RC-network, which is shown in Figure 72, the values of the BTN8980/82 for the resistors can
be found in Table 7 and for the capacities in Table 8, depending on the test condition (PCB).
Table 7
Thermal RC-network resistor values for BTN8980/82
Parameter
1s0p
2s2p
300 mm2
600 mm2
R1
14.7357
14.607
14.5115
14.4932
R2
1.41757
2.99853
0.892556
0.662104
R3
4.68444
2.59111
4.77943
5.04297
R4
417.267
996.831
999.052
962.665
R5
112.975
18.9927
52.4443
41.5135
R6
0.631354
0.586299
0.663352
0.592812
R7
32.786
17.7176
12.9216
10.8754
R8
238.436
60.6471
141.19
133.593
R9
0.010794
0.253683
0.0664578
0.0534714
R10
0.697554
0.0136973
0.843804
0.729177
R11
0.457247
0.800679
0.0121925
0.527079
R12
3.16907
0.309781
0.0990132
0.729318
R13
0.863968
608.83
4.30397
0.308658
R14
122.484
743.102
993.339
108.893
R15
0.922458
0.943908
1.03571
0.725828
R16
63.0068
28.9428
23.0979
13.6581
R17
16.2261
14.9297
20.1678
13.6112
R18
14.9109
0.01
18.7873
15.8732
R19
269.376
711.221
999.114
998.955
R20
31.986
15.9504
33.3671
24.8793
R21
14.5539
11.788
2.37429
2.66703
R22
19.4019
24.147
18.495
13.1898
R23
15.6402
1.70354
20.424
20.3062
R25
0.0102647
0.0180739
0.0147595
0.0992122
R26
5.9597
2.67745
2.46301
2.16571
Application Note
76
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Thermal Performance
Table 8
Thermal RC-network capacitor values for BTN8980/82
Parameter
1s0p
2s2p
300 mm2
600 mm2
C1
0.0109887
0.0122742
0.0117668
0.0114942
C2
4.38961E-06
1.75918E-06
1.13147E-05
0.00010077
C3
0.00361686
0.00382319
0.00452151
0.00335106
C4
0.00117385
0.00118004
0.0011766
0.00117587
C5
0.0144137
0.400558
0.186452
0.249974
C6
0.064702
0.0424699
0.0426304
0.0280119
C7
0.124171
0.0566395
0.407592
0.66619
C8
0.0184178
0.840657
0.061641
0.224521
C10
0.127647
0.0215798
0.0135012
0.130117
C11
0.219454
0.965128
0.201947
0.289226
C12
0.0757321
0.0222976
0.280791
0.460985
C13
0.0020413
0.00210601
0.00223527
0.0013234
C14
0.0489809
0.0743878
0.105303
0.018626
C15
0.28671
0.102
0.411468
0.464271
C16
0.00598831
0.0157598
0.00766389
0.00254175
C17
0.000668051
0.171968
0.0555266
0.0541936
C18
0.801461
3.05061
1.75168
0.000842353
C19
0.00214924
4.84858
0.365562
0.0312806
C20
5.63547
6.30449
2.98494
7.0397
C23
0.348292
0.184817
0.3862
0.261893
C24
0.0995441
0.242926
0.180138
0.116301
Application Note
77
Rev. 0.4, 2015-07-02
BTN8960 /62 /80 /82
High Current PN Half Bridge
Revision History
9
Revision History
Revision
Date
Changes
0.4
2015-07-02
Page 19, Figure 10: Motor shunt replaced.
Page 67, Figure 66: TON and DC new description.
Chapter 5.5 added.
Chapter 6 added.
Chapter 8 added.
Style Guide update (EDD41).
Editorial changes.
0.3
2014-08-29
Page 18 - Chapter 4.3: Added.
Page 20 - Chapter 7.2: Text update.
Page 64 - Chapter 7: Added.
Chapter 2: Updated application circuits (C1 and DC-link)
0.2
2013-01-16
Page 5 - Chapter 2: Added benefits.
Page 6 - Figure 2; Page 7 - Figure 3; Page 12 - Other Components: Changed
resistor name from R1 to R3 and CIS-value to 1nF and CIS-text.
Page 14: Updated Figure 7.
Page 6 - Figure 2, Page 7 - Figure 3: Update value of C1.
Page 12 - Figure 6: Update footnote of figure.
Page 21: New Chapter 5.
0.1
2012-07-09
Initial release.
Application Note
78
Rev. 0.4, 2015-07-02
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