SI-7321M Application Note

Product Information
SI-7321M Motor Driver IC
Introduction
This document describes the function and features of
SI-7321M, a unipolar 2-phase stepping motor driver IC.
This device uses PWM constant current-control, and
provides user-configurable sequencer parameters. The
clock-in type input interface allows simplified control logic,
and options for built-in sense current detection and load
circuit short or open protection (patent pending) provide
lower loss. Lower thermal resistance results from the
innovative multi-chip internal structure, which separates
the main control IC (MIC) from the four heat-generating
MOSFETs, and places wide output terminals at package
corners to enhance thermal dissipation. The built-in
excitation distribution circuit (sequencer) allows motor
control using only the Clock signal for simple operations
(forward, reverse, brake, coast, hold), with motor speed
control by frequency input into Clock pin, and rotation
direction control by a dedicated logic input. This eliminates
logic signal lines required for conventional phase-input
methods, and reduces demand on heavily-used CPUs.
Features and benefits include the following:
▪ Power supply voltage, VBB , 46 V maximum, 10 to 44 V
normal operating range
▪ Logic supply voltage, VDD , 3.3 to 5.5 V
▪ Maximum output current: 1.5 A
▪ Four NMOS output MOSFETs, RDS(on) = 0.25 Ω typical
▪ Built-in sequencer
▪ Simplified clock-in stepping control
▪ Full- and half-stepping and 1/4 , 1/8 , and 1/16 microstepping
▪ Surface mount type 44-pin molded package for automatic
assembly and low profile
▪ Self-excitation PWM current control with fixed off-time
▪ Microstepping off-time adjusted automatically by step
reference current ratio
▪ Built-in synchronous rectifying circuit reduces losses at
PWM switch-off
▪ Synchronous PWM chopping function prevents motor
noise in Hold mode
All performance characteristics given are typical values for
circuit or system baseline design only and are at the nominal
operating voltage and an ambient temperature of 25°C, unless otherwise stated.
SI-7321M-AN Rev. 2.0
Figure 1. The HSOP is a fully molded, low-profile (2.3 mm overall
height), 44-pin HSOP surface-mount package with four enlarged
pins for enhanced thermal dissipation. Configuration is suitable for
automated placement on application PCBs.
▪ Built-in current sensing for each phase, set externally
▪ Dual sleep modes reduce IC input current in stand-by state
▪ Built-in protection against motor coil opens and shorts
• User-configurable operation options, set by external logic
input:
▫ Blanking time: 1.8 μs or 3.6 μs
▫ Sequencer timing on Clock input rising (POS) edge or
both rising and falling (POS/NEG) edges
▫ Protection features enable or disable
Applications include printers, copiers, ticket-vending
machines, ATMs, and industrial robots.
Contents
Introduction
Functional Block Diagram
Package Outline Drawing
Functional Description
Protection Functions
PWM Current Control
Electrical Specifications
Step Sequencing
Application Information
Thermal Design Information
SANKEN ELECTRIC CO., LTD.
http://www.sanken-ele.co.jp/en/
1
2
3
4
6
8
11
14
20
25
Functional Block Diagram
PreDriver
Sequencer
and
Sleep Circuit
Protect
Protect
DAC
+
Comp
-
DAC
Synchro
Control
PWM
Control
+
Comp
-
PWM
Control
OSC
19
26
RsB
NC
NC
NC
NC
NC
3 20 25 35 37 42
NC
Gnd1
Gnd1
Gnd1
6 17 28 39
Gnd1
Gnd3
Gnd2
9
Sync
38
34
Gnd4
29
RsA
4
RsB
OSC
RsA
OutB
OutB
OutB
GB
Reg.
PreDriver
41
18 27 21 22 23 24
36
MIC
OutB
7 15 14 13 10 12 11
GB
VBB
Reset
Clock
M1
CW / CCW
M2
M3
8
E_SEL
30 31 16
33
P_SEL
Mo
32
B_SEL
5
Flag
Ref /Sleep1
VDD
2 40
GA
OutA
1
GA
OutA
OutA
OutA
43 44
Pin-out Diagram
44
1
Terminal List Table
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Name
¯ū¯¯¯tĀ¯
Ō
¯ū¯¯¯tĀ¯
Ō
NC
RsA
GĀ
Gnd1
E_SEL
P_SEL
Sync
CW/CCW
Reset
Clock
M1
M2
M3
B_SEL
Gnd1
GB̄
RsB
NC
¯ū¯¯¯tB̄¯
Ō
¯ū¯¯¯tB̄¯
Ō
SI-7321M-AN Rev. 2.0
2
Function
Output of phase Ā
Output of phase Ā
Non connected pin
Phase A sense resistor connection
Phase Ā MOSFET Gate
Gnd1
Edge select input
Protection enable/disable input
PWM control switch input
Sequence rotation switch
Reset for internal logic
Stepping clock input
Commutation and Sleep2 setting
Blanking time select input
Gnd1
Phase Ā MOSFET Gate
Phase B̄ sense resistor connection
Non connected pin
Output of phase B̄
Output of phase B̄
Number
Name
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
OutB
OutB
NC
RsB
GB
Gnd1
Gnd2
Flag
Mo
VDD
Ref/Sleep1
Gnd3
NC
VBB
NC
Gnd4
Gnd1
GA
RsA
NC
OutA
OutA
SANKEN ELECTRIC CO., LTD.
Function
Output of phase B
Output of phase B
Non connected pin
Phase B sense resistor connection
Phase B MOSFET gate
Gnd1
Gnd2
Output of protection circuit monitor
Output from monitor of 2-phase excitation status
Power supply to logic
VREF PWM control input / Sleep1 enable input
Gnd3
Non connected pin
Main power supply (for motor)
Non connected pin
Gnd4
Gnd1
Phase A MOSFET gate
Phase A sense resistor connection
Non connected pin
Output of phase A
Output of phase A
2
Package Outline Drawing
18.6 ±0.3
10°
0°
44
0.15 +0.01
–0.05
Branding
Area
XXXXXXXX
7.50 ±0.2
XXXXXXXX
9.9 ±0.3
XXXXXXXX
1
2
0.65
0.5 ±0.2
1.50 TYP
44X
2.2 ±0.1
0.10
2.17
0.10 ±0.05
40X 0.22 ±0.05
0.12 M
Terminal core material: Cu
Terminal treatment: Ni plating and Pb-free solder dip
Package: HSOP-44
Dimensions in millimeters
Branding codes (exact appearance at manufacturer discretion):
1st line, type: SI7321M
2nd line, lot:
YMW
Where: Y is the last digit of the year of manufacture
M is the month (1 to 9, O, N, D)
W is the week
3rd line, tracking code: NNNN
Device composition 100% lead (Pb) free
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
3
Functional Description
This section provides a description of the main features of the
SI-7321M.
Control Logic Overview
The control logic is integrated in a single IC, the main IC (MIC)
for high reliability and stability. The MIC also drives the four
DMOS output MOSFETS, which control the current flow into the
motor in accordance with signals from the MIC.
There are two drive phases, each with a pair of outputs. The drive
structure is identical to that of the SLA7070M family. It provides
operation in the following modes:
• PWM mode current level-controlled stepping and microstepping
• Commutation mode for continuous high-speed operation
• Hold mode for stopping motor rotation while continuing to supplying current into a motor, with the SI-7321M powered
• Two sleep modes: Sleep1 in which logic circuits respond to
inputs, and Sleep2 in which the logic interface also shuts down
Sequencer Logic The single Clock input is used for step
timing. Motor rotation direction is controlled by the CW / CCW
input. In PWM stepping modes, each pair of outputs is controlled
by a fixed off-time PWM current-control circuit. The internal
oscillators (OSC in the Functional Block diagram) set the PWM
Table 1. Truth Table for Common Input Pins
Logic Level
Pin Name
Low
High
Reset
Normal operation
Logic reset
CW/ CCW
Forward
Reverse
M1
Commutation / Sleep2 function
(see table 2)
M2
M3
Normal operation / Sleep1 function
(see Reference Voltage Ranges section)
Ref / Sleep1
Sync
Asynchronous
PWM control
Synchronous
PWM control
B_SEL
Short Blanking Time (1.8
μs)
Long Blanking Time (3.6 μs)
Clock input: POS/NEG
edge
Clock input: POS edge
E_SEL
P_SEL
Protection circuits
enabled
Protection circuits disabled
fixed off-time. In high-speed rotation Commutation mode, current ratios are controlled by the combination of the M1, M2, and
M3 input logic levels. For details, refer to tables 1 and 2 and
figure1.
The low pass filter incorporated with the logic input pins (Reset,
Clock, CW /CCW, M1, M2, M3, and Sync) improves noise rejection. The logic inputs are CMOS input compatible, and therefore
they are in high impedance state. Use the IC at fixed input low
and high logic levels.
Input Logic Timing
This device includes clock-in type of control that simplifies the
interface.
Clock Input There are two options for applying Clock inputs:
POS edge and POS/NEG edge, as shown in table 1 and figure 1. Setting the E_SEL pin high selects POS edge clocking,
and E_SEL low selects POS/NEG clocking. In POS clocking,
a low-to-high transition on the Clock input indexes the translator / sequencer. In POS/NEG clocking, low-to-high and high-tolow transitions index the translator / sequencer.
Clock pulse width should be set to more than 2 μs in both positive and negative polarities. Therefore, Clock response frequency
is 250 kHz.
Reset Input The RESET input sets the translator / sequencer
logic to a predefined home state and turns off all of the MOSFET
outputs. The Reset function is asynchronous (see Synchronous
Operation section).
If the input on the Reset pin is high, the internal logic circuit
is reset. At this point, if the Ref/Sleep1 pin stays low, then the
MOSFET outputs turn on at the starting point of excitation. Note
that by default the protection circuits are enabled by a reset.
Table 2. Truth Table for Commutation / Sleep2 Function
Input Pins
M1
M2
M3
Operation Mode
Phases*
Stepping
Current Ratio
Mode
L
L
L
2
Full
8 only
H
L
L
2
Full
F only
L
H
L
1-2
Half
8, F
H
H
L
1-2
Half
L
L
H
W1-2
F
Quarter
4, 8, C, F
2, 4, 6, 8, A, C, E, F
H
L
H
2W1-2
Eighth
L
H
H
4W1-2
Sixteenth
H
H
H
Sleep2 Mode Enable
1 through F
–
*W = double
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
4
The Reset pulse width (the high pulse level hold time) should be
greater than the 2 μs Clock input pulse width. A low pass filter is
incorporated into the Reset circuit; therefore, a greater than 5 μs
delay is required between the falling edge of the Reset input and
the rising edge of the next Clock input.
CW / CCW, M1, M2, and M3 Inputs Logic inputs CW / CCW,
M1, M2, and M3 set the translator step direction (CW / CCW)
and step mode (M1, M2, and M3), as shown in tables 1 and 2.
Changes to these inputs do not take effect until the next Clock
edge (rising if POS option selected, either rising or falling if
POS/NEG selected).
Logic changes are allowed either before or after Clock edges,
but provide a 1 μs minimum delay both before and after adjacent
Clock edges, as setup and hold times (refer to figure 1). The
sequencer logic circuitry might malfunction if the logic polarity
is changed during these setup and hold times. Note that, depending on the type and state of a motor, there may be anomalies in
motor operation. A thorough evaluation on the sequence timing
should be carried out with the application.
Synchronous Operation This function prevents occasional
motor noise during Hold mode, which normally results from
asynchronous PWM operation of both motor phases. A logic
high at the Sync input selects synchronous operation. A logic low
selects asynchronous operation.
The use of synchronous operation during rotation in Commutation mode is not recommended because it produces less motor
torque and can cause motor vibration due to staircase current.
The use of synchronous operation when the motor is not in continuous rotation is allowed only in full- and half-step sequence
timing, due to the difference in the current controlled and PWM
off-time at other stepping rates.
The Sync function is active only during 2-Phase Excitation timing. (2-Phase Excitation timing is enabled when the step reference current ratios of both phase A and phase B are in Mode 8.)
If this function were available in any other timing, the overall
balance might collapse because PWM off-time and the set current
are different in each phase A and phase B control scenario.
DACs (D-to-A Converter) Operation During microstepping,
the current level for each step is set by the value of the external
sense resistor for that phase (RSExtx), a reference voltage (VREF ,
on the Ref/Sleep1 pin), and the output voltage of the internal
DACs, controlled by the output of the translator / sequencer. Refer
to the Step Sequencing Charts section for more information.
Reset
2 μs (min)
5 μs (min)
E_SEL
1 μs (min)
Clock
POS Edge
2 μs (min)
CW/CCW
M1
M2
M3
1 μs (min)
1 μs (min)
2 μs (min)
2 μs (min)
2 μs (min)
1 μs (min)
1 μs (min)
Reset
2 μs (min)
5 μs (min)
E_SEL
POS/NEG Edge
Clock
2 μs (min)
CW/CCW
M1
M2
M3
1 μs (min)
1 μs (min)
1 μs (min)
2 μs (min)
1 μs (min)
1 μs (min)
1 μs (min)
Figure 1. Step timing options. POS/NEG timing allows Clock edge to indexing logic pin settings twice in each Clock period
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
5
Regulator Circuit An integrated regulator circuit is used in
driving the output MOSFET gates and powering other internal
linear circuits.
Sleep Functions There are two low-power sleep modes available in the SI-7321M. These set load supply current, IBB , to
100 μA (max), and disable the MOSFET outputs.
• Sleep1 mode is used to minimize power consumption when the
SI-7321M is not in use. Although it disables much of the internal circuitry, including the output MOSFETs and regulator, the
translator / sequencer circuit is active and logic circuits operate
according to input signals. Therefore, during the Sleep1 function, a signal from an external microcontroller can set the step
starting point for the next operation. Sleep1 is enabled during
normal operation by a logic high at the Ref / Sleep1 pin (VREF).
Normal operation is restored by setting VREF low. A delay of
100 μs is required before sending the initial Clock pulse after
emerging from Sleep1.
• Sleep2 mode is used to further reduce power consumption by
also deactivating the translator / sequencer, in addition to the the
output MOSFETs and regulator. This puts the SI-7321M into
a stand-by state during which logic inputs are ignored and the
internal logic states remain in the same state as when Sleep2
began. Sleep2 is enabled from normal operation by setting
the three Mx pins high, and then setting VREF low. Normal
operation is restored by setting VREF high. A delay of 100 μs is
required before sending the initial Clock pulse after emerging
from Sleep2.
Reference Voltage Ranges The reference voltage, VREF
(applied on the Ref/Sleep1 pin), is used for setting the motor
drive current level and for Sleep mode settings (see the Sleep
Functions section). When in normal operating mode, apply-
Protection Disabled
VREF
Sleep Mode Range
VDD
VREF
Sleep Mode Range
Monitor Outputs The Mo pin and the Flag pin are used to
indicate the operating status of the SI-7321M, as shown in
table 3.
Protection Functions
The SI-7321M includes motor coil short-circuit and motor coil
open protection circuits. Protection functions are enabled by
setting the P_SEL pin to logic low, and disabled by setting the
P_SEL pin high.
When enabled, protection is activated by sensing voltage on the
Rsx inputs, with the threshold level determined by external sense
resistors, RSExtx. Therefore, an overcurrent condition cannot be
detected which results from the OUTx pins or Rsx pins, or both,
shorting to Gnd.
Protection against motor coil opens is available only during
PWM operation. Therefore, it does not work in Commutation
mode constant voltage driving, when the motor is rotating at
high speed.
The protection functions are described as follows:
• Motor Coil (Load) Short-Circuit. This overcurrent protection
(OCP) circuit begins to operate when the SI-7321M detects an
2.0 V
2.0 V
VREF should be less than 1.5 V for setting motor current in
normal operation. As shown in figure 2, to prevent inadvertently
causing a Sleep logic event, a guard band should be maintained
between logic high and logic low ranges. If the protection functions are enabled (via the P_SEL pin), it is necessary to take
into consideration the voltage threshold for overcurrent protection (OCP), 0.7 V. The VREF guard band should be extended to
provide a margin below VOVP , such as restricting motor current
setting voltages to less than 0.5 V.
Operation of the protection circuit disables all of the MOSFET
outputs. The Flag pin is set to logic high. To come out of protection mode, cycle the logic supply, VDD.
Protection Enabled
VDD
ing VREF > 2.0 V (logic high) activates Sleep1 mode. If the
IC is in normal operation mode and the three Mx pins have
been set high, applying a logic low enables Sleep2 mode. If
the SI-7321M is already in Sleep2 mode, applying logic high
restores the IC to normal operation.
Guard Band
1.5 V
Guard Band
Table 3. Truth Table for Monitor Outputs
Motor Current Set Range
VOCP
0.7 V
0.5 V
Motor Current Set Range
0V
0V
Pin Name
Low Level
High Level
Mo
Not operating in
2-Phase Excitation
Operating in
2-Phase Excitation
Flag
Normal operation
Protection circuit operating
Figure 2. Reference voltage, VREF , ranges
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
6
increase in the Rsx input voltage level . The voltage at which
motor coil short-circuit protection starts its operation, VOCP , is
set at approximately 0.7 V. In order for the motor coil shortcircuit protection circuit to operate, VRSx must be greater than
VOCP . Excessive current that flows without passing the external
sense resistors (RSEextx) is undetectable. The function is shown
in figure 3.
• Motor Coil (Load) Open. Details of this function is not disclosed yet due to our patent policy (patent pending).
VM
Coil Short Circuit
+V
Coil Short Circuit
Stepper Motor
Normal Operation
Output Disable
VOCP
VREF
Vg
VS
VS
RSExt
0
t
Figure 3. Motor coil short circuit protection circuit operation. Overcurrent that flows without passing the
sense resistor is undetectable. To recover the circuit after protection operates, VDD must be cycled and
started up again.
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
7
PWM Current Control
Blanking Time The actual operating waveforms on the Rsx
pins when driving a motor are shown in figure 1. Immediately
after PWM turns off, ringing (or spike) noise on the Rsx pins is
observed for a few microseconds. Ringing noise can be generated
by various causes, such as capacitance between motor coils and
inappropriate motor wiring.
Each pair of outputs is controlled by a fixed off-time (7.5 to 13 μs,
depending on stepping mode) PWM current-control circuit that
limits the load current to a target value, ITRIP. Initially, an output
is enabled and current flows through the motor winding and the
current-sense resistors. When the voltage across the current-sense
resistor equals the DAC output voltage, VTRIP , the current-sense
comparator resets the PWM latch. This turns off the driver for
the fixed off-time, during which the load inductance causes the
current to recirculate for the off-time period. Therefore, if the
ringing noise on the sense resistor equals and surpasses VTRIP ,
PWM turns off.
To prevent this phenomenon, the blanking time is set to override
signals from the current-sense comparator for a certain period
right after PWM turns on (figure 2).
Blanking Time and Seeking Phenomenon By shortening
blanking time, current control can be improved, but the ability to
prevent ringing noise will be reduced, and a seeking phenomenon
might occur, shown in figure 3. As a countermeasure against the
seeking phenomenon, the SI-7321M offers two blanking times,
selectable via the B_SEL pin, 1.8 μs and 3.6 μs. Torque reduction or motor noise issues caused by the phenomenon may be
improved by using the longer time.
Comparison of Blanking Times The following table shows
the comparison data of characteristics based on the difference of
blanking time setting. The operating conditions and circuit factors
such as the motor, motor voltage, and Ref/Sleep1 input voltage
are the same.
t1
t1
5 μs /div
0.5 μs /div
ITRIP
IO = 0 V
(Expanded Time Scale)
Figure 1. Operating waveforms on the Rsx pins during PWM chopping
20 μs /div
PWM Pulse Width
A
tON
tOFF
(Fixed)
ITRIP
ITRIP
0
IO = 0 V
A
Blanking Time
Figure 2. Rsx pins pattern during PWM control
SI-7321M-AN Rev. 2.0
Figure 3. Rsx pins pattern during seeking behavior
SANKEN ELECTRIC CO., LTD.
8
Minimum On-Time During PWM The SI-7231M features a
fixed blanking time, with the device kept in active status (on)
throughout this period, even if the on-time, ton , is shortened to
reduce the current level. PWM minimum on-time, ton(min) , is
defined as the actual on-time of the output MOSFET when the
output status is On during this blanking period. Thus, the shorter
blanking time means smaller ton(min).
Minimum Coil Current Minimum coil current represents
reducing the coil current when the SI-7231M is operating with
PWM control at minimum on time, ton(min) . The result is that,
with reduced coil current as the device powers down, current
value decreases to a greater extent in the shorter blanking time.
a sine wave. Because the motor coil current is PWM-controlled,
referenced to ITRIP value, coil current can be controlled so that it
becomes a sine wave. In practice, there is some delay before the
coil current reaches the target value of the inductance component
of the coil.
In general, if the relationship between the convergence time,
tconv , (given tconv ≤ ITRIP), and the input clock cycle (tclk) is
tconv < tclk in all modes, then the envelope of the coil current follows ITRIP. The threshold limit of tconv is determined by power
supply voltage and the coil time constant as current increases. As
current decreases, it is determined by power supply voltage, coil
time constant, and minimum on-time.
Coil Current Waveform Distortion at High Speed
Rotation The ITRIP value varies according to the values specified
by input on the Clock pin during microstepping. The ITRIP value
(internal standard voltage split ratio) is set up so that it becomes
With increasing frequency of the Clock input signal, tclk gets
smaller normally, so that there are cases in which the coil current
cannot converge to the ITRIP value during one clock period. In
these situations, the envelope of the coil current varies from a
true sine wave.
Table 1. Blanking Times
Sanken calls this status waveform distortion. Figure 4 shows the
comparison of waveform distortion with the two different blanking time options. The same power supply voltage, current setting
value, and motors were used.
Relative Blanking Time
Parameter
Short
Minimum on-time during PWM
Long
Smaller
Anti-ringing noise tolerance
Bigger
Minimum coil current
Smaller
Coil current at high speed rotation,
with waveform distortion (microstep)
Bigger
Blanking Time 1.8 μs typical
As shown the areas circled in figure 4, the envelope on the Rsx
terminal waveform (same as the current waveform) with 1.8 μs
blanking time forms a sine wave, but the waveform with 3.6 μs
blanking time varies from a true sine wave.
Blanking Time 3.6 μs typical
Clock
RsA Current
RsB Current
500 μs/div
500 μs/div
Figure 4. Rsx pins waveforms during high speed rotation. Circles indicate regions of waveform distortion.
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
9
The term Bigger in the table 1, represents that, considered under
same conditions, the longer the blanking time, the lower the
frequency at which waveform distortion occurs. Also, if the clock
frequency is the same, the waveform distortion gets bigger at
shorter blanking times.
However, even if such waveform distortion appears, it does not
necessary mean that motor performance is affected. So, thorough
evaluation of the trade-offs is necessary.
PWM Off-Time The PWM off-time, toff , for the SI-7321M is
controlled at a fixed duration by an internal oscillator. It also
is switched at 3 levels by current proportion (see the Electrical
Characteristics table).
In addition, the SI-7321M provides a synchronous rectification
function that decreases losses occurring when the PWM turns
off. This function dissipates back EMF stored in the motor coil at
MOSFET turn-on, as well as at PWM turn-on.
Figure 5 shows the back EMF generative system. The SI-7321M
performs on-off operations using only the MOSFET on the
PWM-off side. To prevent simultaneous switching of the
MOSFETs at synchronous rectification operation, the IC has a
dead time of approximately 0.5 μs. During dead time, the back
EMF flows through the body diode on the MOSFETs.
+V
VBB
Ion
Vg
Ioff
PWM On
PWM Off
Dead
Time
PWM On
Dead
Time
FET Gate 0
Signal
Stepper Motor
Vg
Vg
Vg
Back EMF at
Dead Time
VS
t
VREF
VS
0
RSENSE (external)
t
Figure 5. Synchronous rectification operation. During dead time, the back EMF
flows through the body diodes of the MOSFETs on the PWM-off side.
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
10
Electrical Specifications
Absolute Maximum Ratings
Characteristic
Rating
Units
VM
46
V
Main Power Supply Voltage
VBB
46
V
Logic Supply Voltage
VDD
6
V
1.5
A
–0.3 to VDD+0.3
V
Load Supply Voltage
Symbol
Notes
Current ratio mode F; output current rating may be
limited by duty cycle, ambient temperature, and
heat sinking; under any set of conditions, do not
exceed the specified junction temperature, TJ
Output Current
IO
Logic Input Voltage
VIN
REF Input Voltage
VREF
–0.3 to VDD+0.3
V
Sense Voltage
VRS
tw < 1 μs not considered
±2
V
Power Dissipation
PD
Using Sanken evaluation board at 25°C; rating
significantly affected by the application PCB layout
3.5
W
Junction Temperature
TJ
150
°C
Ambient Temperature
TA
–20 to 80
°C
Storage Temperature
Tstg
–30 to 150
°C
Min.
Typ.
Max.
Unit
3
–
44
V
Recommended Operating Conditions
Characteristic
Symbol
Load Supply Voltage
VM
Main Power Supply Voltage
VBB
Logic Supply Voltage
VDD
REF Input Voltage
VREF
Case Temperature
TC
SI-7321M-AN Rev. 2.0
Conditions
10
–
44
V
Surge voltage at VDD pin should be less
than ±0.5 V to avoid malfunctioning in
operation
3.3
–
5.5
V
Protection features disabled
0.04
–
1.0
V
Protection features enabled
0.04
–
0.5
V
–
–
85
°C
Measured at center of case on branded
side
SANKEN ELECTRIC CO., LTD.
11
ELECTRICAL CHARACTERISTICS, valid at TA = 25°C, VBB = 24 V, VDD = 5 V, unless otherwise specified
Characteristics
Main Power Supply Current
Logic Supply Current
Symbol
Min.
Typ.
Max.
Units
IBB
Normal operation
Test Conditions
–
–
15
mA
IBBS
Sleep1 or Sleep2 modes
–
–
100
μA
–
–
5
mA
IDD
100
–
–
V
RDS(on)
IDS = 1.5 A
–
0.25
0.4
Ω
MOSFET Body Diode
Forward Voltage
VF
IF = 1.5 A
–
0.95
1.2
V
Maximum Clock Frequency1
fclk
Clock duty cycle = 50%, at rising clock edge
250
–
–
kHz
MOSFET Breakdown Voltage
MOSFET Output On-Resistance
Logic Input Voltage
Logic Input Current
VDSS
VIL
–
–
0.25 × VDD
V
VIH
0.75 × VDD
–
–
V
IIL
–
±1
–
μA
IIH
–
±1
–
μA
VREF
REF Input Voltage Range2
VREFS
REF Input Current
IREF
SENSE Voltage
VSENSE
SENSE Current
ISENSE
Overcurrent Protection
Threshold Voltage
VOCP
Flag Pin Logic Output Voltage
Flag Pin Logic Output Current3
Mo Pin Logic Output Voltage
Mo Pin Logic Output Current3
VBB = 44 V, IDS = 1 mA
Protection functions disabled
0.04
–
1.5
V
Protection functions enabled
0.04
–
0.6
V
Sleep1 mode, output off, sequencer enabled, IBBS
within specification
2.0
–
VDD
V
–
±10
–
μA
VREF = 0 to VDD
VREF = 0.2 V, current ratio mode F
Motor coil short circuit, VSENSE ≥ VOCP
VFLAGL
IFLAGL = 1.25 mA
VFLAGH
IFLAGH = –1.25 mA
–
0.2
–
V
–
±10
–
μA
0.65
0.7
0.75
V
–
–
1.25
V
VDD – 1.25
–
–
V
IFLAGL
–
–
1.25
mA
IFLAGH
– 1.25
–
–
mA
–
–
1.25
V
VMOL
IMOL = 1.25 mA
VMOH
IMOH = –1.25 mA
VDD – 1.25
–
–
V
IMOL
–
–
1.25
mA
IMOH
– 1.25
–
–
mA
1Operation
at a step frequency greater than the specified minimum value is possible but not warranted.
2V
REF setting range affected by whether or not protection features are enabled.
3Negative current is defined as coming out of the specified pin.
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
12
STEPPING CHARACTERISTICS valid at TA = 25°C, VBB = 24 V, VDD = 5 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Switching Time
PWM Minimum On-Time
–
100.0
–
%
–
98.1
–
%
Mode D
–
95.7
–
%
Mode C
–
92.4
–
%
Mode B
–
88.2
–
%
Mode A
–
83.1
–
%
–
77.3
–
%
–
70.7
–
%
Mode 7
–
63.4
–
%
Mode 6
–
55.5
–
%
Mode 5
–
47.1
–
%
Mode 4
–
38.2
–
%
Mode 3
–
29.0
–
%
Mode 2
–
19.5
–
%
Mode 1
–
9.8
–
%
Load Disconnection
Undetected Time
VREF = VRSx = 100 %, VREF = 0.04 to 1.5 V
tSE
Sleep1 and Sleep2 modes
100
–
–
μs
tcon
Measured from Clock edge to output on
–
2.0
–
μs
tcoff
Measured from Clock edge to output off
–
1.5
–
μs
B_SEL = low
–
1.8
–
μs
ton(min)
PWM Off-Time
Units
Mode F
Mode 8
Sleep-Enable Recovery Time
Max.
Mode E
Mode 9
Step Reference Current Ratio
Typ.
B_SEL = high
–
3.6
–
μs
toff1
Current ratio modes 8 through F
–
13
–
μs
toff2
Current ratio modes 4 through 7
–
9.5
–
μs
toff3
Current ratio modes 1 through 3
–
7.5
–
μs
topp
Measured from PWM off
1.5
2
2.5
μs
Characteristic Data
Output MOSFET On-Voltage, VDS(on)
Output MOSFET Body Diode Forward Voltage, VF
0.90
MOSFET Body Diode Forward Voltage, VF, (V)
0.8
MOSFET On Voltage, VDS(on), (V)
0.7
0.6
0.5
0.4
IO= 1.5 A
0.3
IO= 1.0 A
0.2
IO= 0.5 A
0.1
0
-25
0
25
50
75
100
125
0.85
0.80
0.75
0.70
IO= 1.0 A
IO= 0.5 A
0.65
0.60
0.55
0.50
-25
Case Temperature, TC (°C)
SI-7321M-AN Rev. 2.0
IO= 1.5 A
SANKEN ELECTRIC CO., LTD.
0
25
50
75
100
125
Case Temperature, TC (°C)
13
Step Sequencing
All illustrations in this section are based on step sequencing using the POS edge option. When the POS/NEG edge option is used, step sequences occur
at both the rising edge and the falling edge of the Clock pulse.
Full step
M1: Low, M2: Low, M3: Low (Mode 8)
R ES ET
…
C LO C K
0
2
1
B
CW
A
A
0
70.7
0
70.7
CCW
B
M1: High, M2: Low, M3: Low (Mode F)
R ES ET
…
C LO C K
0
1
2
B
CW
A
A
0
0
CCW
0
10
B
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
14
Half step
M1: Low, M2: High, M3: Low (Mode 8, F)
RESET
…
CLOCK
0
1
2
3
4
3
4
B
CW
A
A
0
70.7
70.7
0
10
0
CCW
B
M1: High, M2: High, M3: Low (Mode F)
RESET
…
CLOCK
0
1
2
B
CW
A
A
0
0
CCW
0
10
B
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
15
0
2
B
B
3
4
CCW
A
5
6
7
㧤
…
Quarter step
M1: Low, M2: Low, M3: High
1
38.2
CW
0
10
92.4
70.7
38.2
A
CLOCK
RESET
0
92.4
0
70.7
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
16
0
4
B
B
5
6
7
8
CCW
9
A
10
11
12
13
14
15
16
…
Eighth step
M1: High, M2: Low, M3: High
3
19.5
2
38.2
CW
70.7
83.1
92.4
0
1
55.5
92.4
98.1
0
10
83.1
70.7
55.5
38.2
19.5
A
CLOCK
RESET
0
98.1
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
17
98.1
92.4
A
0
0
10
95.7
83.1
88.2
77.3
70.7
63.4
55.5
47.1
38.2
29.0
19.5
9.8
CW
95.7
98.1
SANKEN ELECTRIC CO., LTD.
92.4
2
70.7
1
3
55.5
0
4
47.1
88.2
83.1
CLOCK
5
38.2
SI-7321M-AN Rev. 2.0
6
7
8
B
B
0
RESET
9
10
11
12
13
14
16
CCW
15
17
A
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
…
Sixteenth step
M1: Low, M2: High, M3: High
18
9.8
19.5
29.0
63.4
77.3
Excitation Mode State Tablea
Direction
CCW
CW
aThe
Internal Sequence State
Phase A
Phase B
PWM
Mode
PWM
Mode
A
A
A
A
A
A
A
A
–
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
Ā
–
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
8
7
6
5
4
3
2
1
–
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
F
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
–
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
F
F
E
D
C
B
A
9
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
–
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
B̄
–
B
B
B
B
B
B
B
8
9
A
B
C
D
E
F
F
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
–
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
F
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
–
1
2
3
4
5
6
7
Full Step
Mode 8
Mode F
X
Xb
Step Sequencing
Half Step
 Step

Mode 8, F
Mode F
X
Xb
X
1/
8
Step
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Xb
X
Xb
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Xb
X
Xb
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Xb
X
Xb
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1/
16
Step
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
change behavior is determined by the settings of the excitation pins (M1, M2, and M3) before and after the Clock edge.
state is Mode 8, but step reference current ratio is Mode F. Mode F has step reference current ratio of 100%, and PWM off-time of 14 μs.
bSequence
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
19
Application Information
VS = 10 to 44 V
R1
C1
VDD OutA
(44)
OutA
(1)
Reset
Clock
CW/CCW
M1
M2
M3
Sync
E_SEL
P_SEL
B_SEL
Mo
Flag
Ref/Sleep1
CB
R2 R3
C2
Logic Ground
OutB
(22)
OutB
(23)
OutA(43)
OutA( 2)
OutB(21)
OutB(24)
CA
GA
GA
GB
GB
SI-7321M
Gnd1
Gnd1
Gnd1
Gnd1
Gnd2
Gnd3
Gnd4
Microcomputer
VBB
RsB
RsB
Sleep
Q1
RsA
RsA
VCC = 3.3 to 5.5 V
RsA
NC
NC
NC
NC
NC
NC
RsB
Star Ground
Power Ground
Figure 6. Typical application circuit
• Take precautions to avoid noise on the VDD line; noise levels
greater than 0.5 V on the VDD line may cause device malfunction. Noise can be reduced by separating the logic ground and
the power ground on a PCB from the Gnd pins.
• Constants, for reference use only:
R1, R3 = 10 kΩ
CA = 100 μF / 50 V
R2 = 1 kΩ (RV)
CB = 10 μF / 10 V
C1, C2 = 0.1 μF
SI-7321M-AN Rev. 2.0
• Unused logic input pins (CW /CCW, M1, M2, M3, Reset, and
Sync) must be pulled up / down to VDD or ground. If those
unused pins are left open, the device malfunctions.
• Unused logic output pins (Mo, Flag) must be kept open.
SANKEN ELECTRIC CO., LTD.
20
where:
Motor Current Ratio Setting (R1, R2, RSx)
The calculated value of motor current, IO , is determined by
the ratios of external components R1, R2, and RSX (refer to the
application example circuit, figure 6). The following is a formula
for calculating IO :
VDD
R2
R1 + R2
IO =
RSx
(1)
,
when VREF is within specification. If VREF is set less than 0.1 V,
variation or impedance of the wiring pattern may influence the
IC and the possibility of less accurate current sensing becomes
high.
The standard voltage of current ITRIP that controls is partially
divided by the internal DAC:
VREF
ITRIP =
RSx
Current Mode Ratio .
(2)
Lower Limit of Control Current
Thus, average current decrease and motor torque also decrease.
The point intermittent current starts flowing to the coil is considered as the lower limit of the control current. The lower limit
of control current differs by the motor characteristics and other
factors, but it is calculated from the following formula:
A
IO
LM , and
(4)
VM is the motor supply voltage,
RDS(on) is the MOSFET on resistance,
IO is the target current level,
RM is the motor winding resistance,
LM is the motor winding reactance, and
tOFF is the PWM off-time.
Even if the control current value is set at less than the lower limit
of the control current, there is no setting at which the IC fails to
operate. However, control current will worsen against setting
current.
Avalanche Energy
The SI-7321M uses a self-oscillating PWM current control
topology in which the off- time is fixed. As energy stored in
motor coil is eliminated within fixed the PWM off-time, coil
current flows intermittently, as shown in figure 7.
VM + RDS(on)
IO(min) =
RM
TC = RM
⎛ tOFF
+ exp ⎜⎜ T
⎝ C
−1
⎞
⎟⎟ − 1 ,
⎠
(3)
In the unipolar topology of the SI-7321M, a surge voltage
(ringing noise) that exceeds the MOSFET capacity to withstand
might be applied to the IC. To prevent damage, the SI-7321M
MOSFET are designed with sufficient avalanche resistance to
withstand this surge voltage. Therefore, even if surge voltages
occur, users will be able to use the IC without any problems.
However, in cases in which the motor harness is long or the IC
is used above its rated current or voltage, there is a possibility
that an avalanche energy could be applied that exceeds Sanken
design expectations. Thus, users must test the avalanche energy
applied to the IC under actual application conditions.
ITRIP(Big)
ITRIP(Small)
0
A
Figure 7. Control current lower limit model waveform. The circled area indicates the interval in which the coil
current generated is 0 A.
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
21
The following procedure can be used to check the avalanche
energy in an application. The schematic in figure 8 illustrates
the location for the voltage test points and circuit characteristics.
The timing diagram illustrates the waveform characteristics
resultant.
the avalanche energy, EAV , can be calculated using the following
formula:
EAV = VDS(av) 0.5 ID t
= 140 V 0.5 1A 10-6
= 0.035 mJ
Given:
(5)
By comparing the calculated EAV to the graph shown in figure 9, the application can be evaluated if it is safe for the IC by
being within the avalanche energy-tolerated dose range of the
MOSFET.
VDS(av) = 1 A,
ID = 1 A, and
t = 0.5 μs,
On-Off Sequence of Power Supply (VBB and VDD)
VM
ID
Stepper
Motor
There is no restriction of the on-off sequence of the main power
supply, VBB, and the logic supply, VDD.
8 & 5
# 8 Motor Supply Voltage (VM) and Main Power Supply
Voltage (VBB)
VDS(AV)
+&
Because the SI-7321M series has a structure that separates the
control IC (MIC) and the power MOSFETs (as shown in the
Functional Block diagram), motor supply and main power supply are separated. Therefore, it is possible to drive the IC using
different power supplies and different voltages for motor supply
and main power supply. However, extra caution is needed
because the supply voltage ranges differ among power supplies.
RSExt
V
Figure 8. Test points and characteristics (left panel) and breakdown
waveform timing (right)
12
EAV (mJ )
10
8
6
4
2
0
0
10
20
30
40
50
60
70
80
90
100
Product Temperature, Tc (°C)
Figure 9. Iterated avalanche energy tolerated dose, EAV(max).
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
22
Internal Logic Circuits
Reset The sequencer circuit of this product is initialized after
logic supply (VDD) is applied, and the power on reset function
operates. To initialize the sequencer, the output immediately
after power-on indicates that the status that the power circuits are
in the home state. In a case where the sequencer must be reset
after motor has been operating, a reset signal must be applied
to the Reset pin. In a case in which external reset control is not
necessary, and the Reset pin is not used, it must be tied to ground
on the application circuit board.
Clock When the Clock input signal stops, excitation changes to
the motor Hold state. At this time, there is no difference if the
Clock input signal is at logic low or logic high. The SI-7321M
is designed to move 1 step at a time, when a Clock pulse edge is
detected (rising if POS option selected, either rising or falling if
POS/NEG selected).
Chopping Synchronous Circuit The SI-7321M has a chopping synchronous function to protect from abnormal noises that
may occasionally occur during the motor Hold state. This function can be operated by setting the Sync terminal at logic high.
However, if this function is used during motor rotation, control
current does not stabilize, and therefore this may cause reduction of motor torque or increased vibration. So, Sanken does
not recommend using this function while the motor is rotating.
In addition, the synchronous circuit should be disabled in order
to control motor current properly in case it is used other than in
dual excitation state (Modes 8 and F) or single excitation Hold
state.
In normal operation, generally the input signal for switching can
be sent from an external microcomputer. However, in applications where the input signal cannot be transmitted adequately
due to limitations of the port, the following method can be taken
to use the functions.
The schematic diagram in figure 10 shows how the IC is
designed so that the Sync signal can be determined by the Clock
input signal. When a logic high signal is received on the Clock
pin, the internal capacitor, C, is charged, and the Sync signal
is set to logic low level. However, if the Clock signal cannot
rise above logic low level (such as when the circuit between
the microcomputer and the IC is not adequate), the capacitor is
discharged by the internal resistor, R, and the Sync signal is set
to logic high, causing the IC to shift to synchronous mode.
The RC time constant in the circuit should be determined by the
minimum clock frequency used. In the case of a sequence that
keeps the Clock input signal at logic high, an inverter circuit
must be added. In a case where the Clock signal is set at an
undetermined level, or when the POS/NEG edge option is used,
an edge detection circuit (figure 10) can be used to prepare the
signal for the Clock input, allowing correct processing by the
circuit shown in figure 11.
Output Disable (Sleep1 and Sleep2) Circuits There are
two methods to set this IC at motor free-state (coast, with outputs disabled). One is to set the Ref/Sleep1 pin to more than 2 V
(Sleep1), and the other (Sleep2) is to set the excitation signals
(pins M1, M2, and M3). In either way, the IC will change to
Sleep mode, stopping the main power supply at the same time,
and decreasing circuit current. The difference between the two
methods is that, in the first way, the internal sequencer remains
in an enabled state, and in the latter method, the IC enters the
Hold state. Moreover, in the method using the excitation signals
(Sleep2), excitation timing remains in a standby state, even if a
signal is inputted on the Clock pin during Sleep2 mode.
VCC
Clock
74HC14
74HC14
Sync
Step
Clock
R
C
Figure 10. Clock signal shutoff detection circuit; using 74HC14s
SI-7321M-AN Rev. 2.0
Clock
Figure 11. Clock signal edge detection circuit; inputs to example circuit
shown in figure 10
SANKEN ELECTRIC CO., LTD.
23
When awaking to normal operating mode (motor rotation) from
disabled (Sleep1 or Sleep2) mode, set an appropriate delay time
from cancellation of the disable mode to the initial Clock input
edge. In doing so, consider not only of rise time for the IC, but
also of the rise time for the motor excitation current, is important
(see figure 12). When using POS/NEG edge option, the case can
occur in which the Clock signal negative edge should be used for
calculating the delay.
Ref/Sleep1 Pin The Ref/Sleep1 pin provides access to the following functions:
exercised. These are shown in figure 13:
• Range A. In this range, the control current value also varies in
accordance with VREF. Therefore, losses in the IC and the sense
resistors must be given extra consideration.
• Range B. In this range, the voltage that switches output enable
and disable (Sleep mode) exists. At enable, the same cautions
apply as in range A. In addition, for some cases, there are possibilities that the output status will become unstable as a result
of iteration between enable and disable.
• Output enable-disable control input
Logic Input Pins If a logic input pin (Clock, Reset, CW/CCW,
M1, M2, M3, or Sync) is not used (fixed logic level), the pin
must be tied to VDD or Gnd. Please do not leave them floating,
because there is possibility of undefined effects on IC performance when they are left open.
Figure 2 shows the general relationship between the reference
voltage, VREF , (Ref/Sleep1 pin) setting voltage and performance.
There are, however, situations in which extra caution should be
Output Pins The Mo and Flag output pins are designed as
monitor outputs, and inside of the IC is an output inverter (see
figure 14). Therefore, let these pins float if they are not used.
• Standard voltage setting for output current level setting
VDD
Ref/Sleep1 or
M1, M2, and M3
Static electricity
protection circuit
100 μs
(minimum)
Mo or Flag
Clock
Internal Control Current Setting Voltage
(Mode F) (V)
Figure 12. Timing delay between disable cancellation and the
next Clock input
Figure 14. Mo pin and Flag pin general internal circuit layout
2.5
Output disable (Sleep mode)
setting voltage range
2.0
Range B
1.5
Range A
1.0
Control current input voltage range
0.5
Recommended input voltage range
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.1
Ref/Sleep1 Pin Voltage, VREF (V)
Figure 13. Relationship between external and internal reference voltages and performance
SI-7321M-AN Rev. 2.0
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Thermal Design Information
It is not practical to calculate the power dissipation of the
SI-7321M accurately, because that would require factors that are
variable during operation, such as time periods and excitation
modes during motor rotation, input frequencies and sequences,
and so forth. Given this situation, it is preferable to perform an
approximate calculation at worst case conditions. The following
are simplified formulas for calculation of power dissipation:
PD = I 2O
RDS(on)
2 ,
(6)
where:
1. Measure the ambient temperature, TA.
2. With the device mounted but not operating, measure the
temperature of the device case at the center of the branded side.
3. Power-on the device, and after it reaches operating
temperature, take the measurement again.
4. Subtract the value found in step 2 from the value found in
step 3. This will provide a value for ∆TCA.
PD is the power dissipation in the IC,
IO is the operating output current, and
RDS(on) is the on resistance of the output MOSFET.
Based on the PD calculated using the above formula, the
expected increase in operating junction temperature, ∆TJ , of the
IC can be estimated using figure 15.
This result must be added to the worst case ambient temperature
when operating, TA(max). Based on the calculation, there is no
problem unless TA(max) + ∆TJ > 150°C. However, final confirmation must be made by measuring the IC temperature during
operation and then verifying power dissipation and junction
temperature in the graph.
When the IC ground is connected to a large area of exposed copper on the PCB that acts as a heat sink, device package thermal
resistance, RθJA, is a variable used in calculating ∆TJA.
The value of RθJA is calculated from the following formula:
RθJA+RθJC = RθJA–RθCA .
(7)
∆TJA can be calculated using the value of RθJA:
ΔTJ = ΔTJC+PD RθJC
The following procedure should be used to measure product
temperature in actual operation and then estimate junction temperature:
.
(8)
5. Refer to figure 15 and locate the value found in step 4 on the
∆TCA trace.
6. Determine the corresponding power dissipation, PD.
7. Substitute the values into equation 8.
CAUTION: The SI-7321M is designed as a multichip, with
separate power elements (MOSFET) and control IC (MIC).
Consequently, because the control IC cannot accurately detect
the temperature of the power elements (which are the primary
sources of heat), the ICs do not provide a protection function
against overheating. For thermal protection, users must conduct
sufficient thermal evaluations to be able to ensure that the junction temperature does not exceed the warranty level (150°C).
This thermal design information is provided for preliminary
design estimations only. The thermal performance of the IC will
be significantly determined by the conditions of the application,
in particular the state of the mounting PCB, exposed copper
area heat sink, and the ambient air. Before operating the IC in an
application, the user must experimentally determine the actual
thermal performance.
Increase in Junction Temperature
∆TJ (°C)
140
120
100
∆TJ-A = 35.7 x PD
80
60
∆TC-A = 20 x PD
40
20
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Maximum Allowable Power Dissipation, PD(max) (W)
Figure 15. Temperature increase relationship
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
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Because reliability can be affected adversely by improper storage
environments and handling methods, please observe the following:
Cautions for Storage
•
Ensure that storage conditions are within 5°C to 40°C and relative
humidity < 30%; avoid storage locations that experience extreme
changes in temperature or humidity.
•
Avoid locations where dust or harmful gases are present and
avoid direct sunlight.
•
Reinspect for rust on leads and solderability of products that have
been stored for a long time.
Soldering
•
The product is in a surface mount package. The product should
not be mounted on warped direction of the PCB.
•
When the product is mounted by means of solder reflow and the
resin is unusually damp, solder dipping may cause interfacial
defoliation. This occurs when a drastic temperature change
causes moisture in the resin to evaporate and to swell. Therefore,
attention must be paid to the following:
•
Examine the moisture-resistant packing before opening. If
the indicator color (blue) of the desiccant (such as silica gel)
has disappeared, the product must be prebaked as described
below.
•
After the product packing is opened and staged for assembly,
soldering should be carried out as soon as practicable.
•
During handling, ambient conditions should be 5°C to 30°C,
with relative humidity < 70%
•
After 120 hours of exposure, prebake is recommended
before soldering; bake-out at 60±5°C for more than 10 hours
Cautions for Testing and Handling
•
After soldering, no mechanical force or excessive vibration should
be applied to the product until the product has cooled down to
normal room temperature. Quick cooling must be avoided.
•
When soldering the products, please be sure to minimize the
working time, within the following limits:
Precautions During Use
•
Never apply an external force, stress, or excess vibration to resin
or terminals when at high temperature.
Electrostatic Discharge
•
When handling the products, operator must be grounded.
Grounded wrist straps worn should have at least 1 MΩ of
resistance to ground to prevent shock hazard.
•
Workbenches where the products are handled should be
grounded and be provided with conductive table and floor mats.
•
When using measuring equipment such as a curve tracer, the
equipment should be grounded.
•
When soldering the products, the head of soldering irons or the
solder bath must be grounded in other to prevent leak voltages
generated by them from being applied to the products.
•
•
•
The products should always be stored and transported in our
shipping containers or conductive containers, or be wrapped in
aluminum foil.
Exposure to any overvoltage exceeding the Absolute Maximum
Rating of the products may cause damage to, or possibly result in
destruction of, the products. Buyer shall take absolutely secured
countermeasures against static electricity and surge when
handling the products.
Typical anti-static and anti-surge reference circuits are shown
below. The circuits shown are for reference only, and the buyer
must make a sufficient experimental verification of the static and
surge levels when employing the product.
SI-7321M-AN Rev. 2.0
•
Soldering Iron Temperature
(°C)
Time
(s)
380±10
3 (once only)
Reflow soldering can be performed a maximum of 2 times, with
preheat conditions of 150°C to 180°C (at the device surface)
for 60 to 120 s, and soldering conditions less than 40 s at more
than 220°C, with a peak temperature less than 260°C, using the
following recommended profile:
Temperature of Device Package Surface (°C)
When tests are carried out during inspection testing and other
standard test periods, protect the products from power surges
from the testing device, shorts between adjacent products, and
shorts to the heat sink.
Reflow Soldering Profile
300
260
Peak 250°C Max
245°C
220
180
140
Pre-heat
60 to 120 s
100
10 ±1 s
60
20
0
50
100
150
200
Soldering Time (s)
250
300
Between the first and second reflow sessions, follow the
guidelines in the Cautions for Storage section, above.
SANKEN ELECTRIC CO., LTD.
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• The contents in this document are subject to changes, for improvement and other purposes, without notice. Make sure that this is the
latest revision of the document before use.
• Application and operation examples described in this document are quoted for the sole purpose of reference for the use of the products herein and Sanken can assume no responsibility for any infringement of industrial property rights, intellectual property rights or
any other rights of Sanken or any third party which may result from its use.
• Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products at a certain rate is inevitable. Users of Sanken products are requested to take, at their own risk, preventative measures
including safety design of the equipment or systems against any possible injury, death, fires or damages to the society due to device
failure or malfunction.
• Sanken products listed in this document are designed and intended for the use as components in general purpose electronic equipment or apparatus (home appliances, office equipment, telecommunication equipment, measuring equipment, etc.).
When considering the use of Sanken products in the applications where higher reliability is required (transportation equipment and
its control systems, traffic signal control systems or equipment, fire/crime alarm systems, various safety devices, etc.), and whenever
long life expectancy is required even in general purpose electronic equipment or apparatus, please contact your nearest Sanken sales
representative to discuss, prior to the use of the products herein.
The use of Sanken products without the written consent of Sanken in the applications where extremely high reliability is required
(aerospace equipment, nuclear power control systems, life support systems, etc.) is strictly prohibited.
• In the case that you use Sanken products or design your products by using Sanken products, the reliability largely depends on the
degree of derating to be made to the rated values. Derating may be interpreted as a case that an operation range is set by derating the
load from each rated value or surge voltage or noise is considered for derating in order to assure or improve the reliability. In general,
derating factors include electric stresses such as electric voltage, electric current, electric power etc., environmental stresses such
as ambient temperature, humidity etc. and thermal stress caused due to self-heating of semiconductor products. For these stresses,
instantaneous values, maximum values and minimum values must be taken into consideration.
In addition, it should be noted that since power devices or IC's including power devices have large self-heating value, the degree of
derating of junction temperature affects the reliability significantly.
• When using the products specified herein by either (i) combining other products or materials therewith or (ii) physically, chemically
or otherwise processing or treating the products, please duly consider all possible risks that may result from all such uses in advance
and proceed therewith at your own responsibility.
• Anti radioactive ray design is not considered for the products listed herein.
• Sanken assumes no responsibility for any troubles, such as dropping products caused during transportation out of Sanken's distribution network.
• The contents in this document must not be transcribed or copied without Sanken's written consent.
SI-7321M-AN Rev. 2.0
SANKEN ELECTRIC CO., LTD.
27