LTC3822-1 No RSENSETM, Low Input Voltage, Synchronous Step-Down DC/DC Controller DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Dual N-Channel MOSFET Synchronous Drive No Current Sense Resistor Required Optimized for 3.3VIN and Li-Ion Applications Constant Frequency Current Mode Operation for Excellent Line and Load Transient Response ±1% 0.6V Reference Low Dropout Operation: 99% Duty Cycle Phase-Lockable or Adjustable Frequency: 250kHz to 750kHz Internal Soft-Start Circuitry Tracking and Adjustable Soft-Start Input Selectable Maximum Peak Current Sense Threshold Selectable Burst Mode®/ Forced Continuous/Pulse Skipping Mode at Light Load Digital RUN Control Pin Output Overvoltage Protection Micropower Shutdown: IQ = 7.5µA Tiny Thermally Enhanced 12-Pin (3mm × 3mm) DFN or 16-Pin Narrow SSOP Packages APPLICATIONS ■ ■ The LTC®3822-1 is a synchronous step-down switching regulator controller that drives external N-channel power MOSFETs using few external components. The constant frequency current mode architecture with MOSFET VDS sensing eliminates the need for sense resistors and improves efficiency. Burst Mode operation provides high efficiency at light loads. The 99% maximum duty cycle provides low dropout operation, extending operating time in battery-powered systems. The operating frequency can be programmed up to 750kHz, allowing the use of small surface mount inductors and capacitors. For noise sensitive applications, the LTC3822-1 can be synchronized to an external clock from 250kHz to 750kHz. The LTC3822-1 is available in the tiny footprint thermally enhanced 12-pin DFN package or 16-pin narrow SSOP package. LTC3822-1 LTC3822 Continuous, Discontinuous Discontinuous Mode or Burst Mode Operation DD12 (3mm × 3mm), GN16 DD10 (3mm × 3mm), MS10E Tracking/Soft-Start Yes Internal Soft-Start Only External Sync Yes No PGOOD Pin GN16 Only No Light Load Operation Package Single Cell Li-Ion Powered Systems 3.3VIN Systems , LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by Patents, including 5481178, 5929620, 6580258, 6304066, 5847554, 6611131, 6498466, 5705919. Efficiency/Power Loss vs Load Current TYPICAL APPLICATION VIN RUN PLLLPF TG LTC3822-1 ITH SW 10.2k BOOST 1nF SYNC/MODE TRACK/SS GND VFB 0.47µH VIN 3.3V VOUT 1.8V 47µF 8A ×2 0.1µF Burst Mode EFFICIENCY 80 60 50 118k 0.1 Burst Mode POWER LOSS 40 30 BG GND 10 0.01 VIN = 3.3V VOUT = 1.8V FIGURE 10 CIRCUIT 0 59k 1 70 20 38221 TA01 10 POWER LOSS (W) 47µF ×2 90 EFFICIENCY (%) IPRG 100 10 100 1000 LOAD CURRENT (mA) 0.001 10000 38221 TA01b 38221f 1 LTC3822-1 ABSOLUTE MAXIMUM RATINGS (Note 1) Input Supply Voltage (VIN) ........................ –0.3V to 4.5V BOOST Voltage .......................................... –0.3V to 10V PLLLPF, RUN, IPRG, SYNC/MODE, TRACK/SS Voltages .......................–0.3V to (VIN + 0.3V) VFB, ITH Voltages ....................................... –0.3V to 2.4V SW Voltage ............................................ –2V to VIN + 1V Operating Temperature Range (Note 2) ... –40°C to 85°C Storage Ambient Temperature Range DD ..................................................... –65°C to 125°C GN ..................................................... –65°C to 150°C Junction Temperature (Note 3) ............................. 125°C Lead Temperature (Soldering, 10 sec) GN Only ............................................................ 300°C PACKAGE/ORDER INFORMATION TOP VIEW TOP VIEW GND 1 16 SW PLLLPF 1 12 SW PLLLPF 2 15 SENSE– SYNC/MODE 2 11 VIN SYNC/MODE 3 14 VIN TRACK/SS 3 10 BOOST VFB 4 ITH 5 RUN 6 13 9 TG 8 BG 7 IPRG DD PACKAGE 12-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB PGOOD 4 13 BOOST TRACK/SS 5 12 TG VFB 6 11 BG ITH 7 10 IPRG RUN 8 9 GND GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 110°C/W ORDER PART NUMBER DD PART MARKING ORDER PART NUMBER GN PART MARKING LTC3822EDD-1 LCMS LTC3822EGN-1 38221 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS 2.75 3.3 4.5 V 360 105 7.5 10 525 150 20 20 µA µA µA 1.95 2.15 2.25 2.45 2.55 2.75 V V 0.7 1.1 1.4 V 0.6 0.606 0.025 0.1 Main Control Loops VIN Operating Voltage Range Input DC Supply Current Normal Operation Sleep Mode Shutdown UVLO (Note 4) Undervoltage Lockout Threshold VIN Falling VIN Rising RUN = 0 VIN = UVLO Threshold – 200mV ● ● Shutdown Threshold Of RUN Pin Regulated Feedback Voltage (Note 5) Output Voltage Line Regulation 2.75V < VIN < 4.5V (Note 5) ● 0.594 V %/V 38221f 2 LTC3822-1 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise noted. PARAMETER CONDITIONS MIN Output Voltage Load Regulation ITH = 1.3V to 0.9V (Note 5) ITH = 1.3V to 1.7V TRACK/SS Pull-Up Current TRACK/SS = 0V VFB Input Current (Note 5) Overvoltage Protect Threshold Measured at VFB TYP MAX UNITS 0.1 –0.1 0.5 –0.5 % % 0.65 1 1.35 µA 10 50 nA 0.66 0.68 0.70 V Overvoltage Protect Hysteresis 20 mV Top Gate (TG) Drive Rise Time CL = 3000pF 40 ns Top Gate (TG) Drive Fall Time CL = 3000pF 40 ns Bottom Gate (BG) Drive Rise Time CL = 3000pF 50 ns Bottom Gate (BG) Drive Fall Time CL = 3000pF 40 ns Maximum Duty Cycle In Dropout 99 % Maximum Current Sense Voltage (VIN – SW) (ΔVSENSE(MAX)) IPRG = Floating IPRG = 0V IPRG = VIN Soft-Start Time Time for VFB to Ramp from 0.05V to 0.55V ● ● ● 110 70 185 125 82 200 140 95 220 mV mV mV 650 µs Oscillator Oscillator Frequency PLLLPF = Floating PLLLPF = 0V PLLLPF = VIN 480 240 640 550 300 750 600 340 850 kHz kHz kHz Phase-Locked Loop Lock Range SYNC/MODE Clocked Minimum Synchronizable Frequency Maximum Synchronizable Frequency 200 1000 250 750 kHz kHz Phase detector Output Current Sinking Sourcing fOSC > fSYNC/MODE fOSC < fSYNC/MODE –5 5 µA µA PGOOD Voltage Low IPGOOD Sinking 1mA 100 mV PGOOD Trip Level VFB with Respect to Set Output Voltage VFB < 0.6V, Ramping Postive VFB < 0.6V, Ramping Negative VFB > 0.6V, Ramping Negative VFB > 0.6V, Ramping Positive PGOOD Output (GN Package Only) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3822E-1 is guaranteed to meet specified performance from 0°C to 85°C. Specifications over the –40°C to 85°C operating range are assured by design characterization, and correlation with statistical process controls. –13 –16 7 10 –10.0 –13.3 10.0 13.3 –7 –10 13 16 % % % % Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • θJA) Note 4: Dynamic supply current is higher due to gate charge being delivered at the switching frequency. Note 5: The LTC3822-1 is tested in a feedback loop that servos ITH to a specified voltage and measures the resultant VFB voltage. 38221f 3 LTC3822-1 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency/Power Loss vs Load Current 100 10 80 EFFICIENCY EFFICIENCY (%) 1 60 50 0.1 40 POWER LOSS 30 POWER LOSS (W) 70 VOUT AC COUPLED 200mV/DIV VOUT AC COUPLED 200mV/DIV INDUCTOR CURRENT 2A/DIV INDUCTOR CURRENT 2A/DIV FIGURE 10 CIRCUIT 0.01 Burst Mode OPERATION PULSE SKIPPING CONTINUOUS MODE 0.001 100 1000 10000 LOAD CURRENT (mA) 20 10 0 10 Load Step (Pulse Skip Mode) Load Step (Continuous Mode) 100 VIN = 3.3V, VOUT = 1.8V 90 TA = 25°C unless otherwise noted. 38221 G02 50µs/DIV FIGURE 10 CIRCUIT 38221 G04 50µs/DIV FIGURE 10 CIRCUIT 38221 G01 INDUCTOR CURRENT 2A/DIV 0.604 2.55 0.603 2.50 0.602 2.45 INPUT VOLTAGE (V) FEEDBACK VOLTAGE (V) VOUT AC COUPLED 200mV/DIV Undervoltage Lockout Threshold vs Temperature Regulated Feedback Voltage vs Temperature Load Step (Burst Mode Operation) 0.601 0.600 0.599 VIN RISING 2.40 2.35 2.30 VIN FALLING 0.598 2.25 0.597 2.20 38221 G05 50µs/DIV FIGURE 10 CIRCUIT 0.596 –50 0 50 TEMPERATURE (°C) 100 2.15 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 38212 G06 Shutdown (RUN) Threshold vs Temperature 1.10 1.05 1.00 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 38221 G08 Oscillator Frequency vs Temperature 10 IPRG = FLOAT NORMALIZED FREQUENCY SHIFT (%) MAXIMUM CURRENT SENSE THRESHOLD (mV) RUN VOLTAGE (V) 1.15 135 130 125 120 115 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 100 38221 G07 Maximum Current Sense Threshold vs Temperature 1.20 80 80 100 3822 G09 8 6 4 2 0 –2 –4 –6 –8 –10 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 38221 G10 38221f 4 LTC3822-1 TYPICAL PERFORMANCE CHARACTERISTICS Shutdown Quiescent Current vs Input Voltage Maximum Current Sense Voltage vs ITH Pin Voltage Oscillator Frequency vs Input Voltage 100 80 CURRENT LIMIT (%) 3 2 1 0 –1 –2 –3 18 Burst Mode OPERATION (ITH RISING) Burst Mode OPERATION (ITH FALLING) FORCED CONTINUOUS MODE PULSE SKIPPING MODE 4 60 40 16 SHUTDOWN CURRENT (µA) 5 NORMALIZED FREQUENCY SHIFT (%) TA = 25°C unless otherwise noted. 20 0 14 12 10 8 6 4 2 –4 –5 2.5 –20 3.0 3.5 4.0 INPUT VOLTAGE (V) 4.5 0.5 0 2.5 3.0 3.5 4.0 INPUT VOLTAGE (V) 38221 G03 38221 G11 Quiescent Current in Normal Operation vs Input Voltage 2 1 1.5 ITH VOLTAGE (V) 4.5 38221 G12 Start-Up with External Soft-Start Capacitor Start-Up with Internal Soft-Start 390 VRUN 1V/DIV QUIESCENT CURRENT (µA) 380 VRUN 1V/DIV VTRACK/SS 1V/DIV 370 VOUT 1V/DIV 360 VOUT 1V/DIV 350 340 330 2.5 3.0 3.5 4.0 INPUT VOLTAGE (V) 4.5 200µs/DIV FIGURE 10 CIRCUIT VIN = 3.3V VOUT = 1.8V RLOAD = 1.5Ω 38221 G14 4ms/DIV FIGURE 10 CIRCUIT VIN = 3.3V VOUT = 1.8V RLOAD = 1.5Ω CSS = 0.01µF 38221 G15 3822 G13 Soft-Start with Tracking Continuous Mode Operation VTRACK/SS 500mV/DIV VSW 2V/DIV VOUT 20mV/DIV AC COUPLED VOUT 1V/DIV IL 2A/DIV 4ms/DIV FIGURE 10 CIRCUIT VIN = 3.3V VOUT = 1.8V RLOAD = 1.5Ω 38221 G16 2µs/DIV FIGURE 10 CIRCUIT VIN = 3.3V VOUT = 1.8V, 100mA 38221 G17 38221f 5 LTC3822-1 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted. Pulse Skip Mode Operation Burst Mode Operation VSW 2V/DIV VSW 2V/DIV VOUT 20mV/DIV AC COUPLED VOUT 20mV/DIV AC COUPLED IL 2A/DIV IL 2A/DIV 2µs/DIV FIGURE 10 CIRCUIT VIN = 3.3V VOUT = 1.8V, 100mA PIN FUNCTIONS 38221 G18 10µs/DIV FIGURE 10 CIRCUIT VIN = 3.3V VOUT = 1.8V, 100mA 38221 G19 (DD/GN) PLLLPF (Pin 1/Pin 2): This pin serves as the frequency select input and PLL lowpass filter compensation point. When SYNC/MODE has a DC voltage on it, tying this pin to GND selects 300kHz operation; tying this pin to VIN selects 750kHz operation. Floating this pin selects 550kHz operation. When SYNC/MODE has a clock applied to it, connect an R-C network from this pin to ground. SYNC/MODE (Pin 2/Pin 3): This pin performs two functions: 1) external clock synchronization input for phaselocked loop and 2) Burst Mode, pulse skipping or forced continuous mode select. Applying a clock with frequency between 250kHz and 750kHz causes the internal oscillator to phase-lock to the external clock and disables Burst Mode operation, but allows pulse skipping at low load currents. To select Burst Mode operation at light loads, tie this pin to VIN. Grounding this pin selects forced continuous operation, which allows the inductor current to reverse. Tying this pin to a voltage greater than 0.4V and less than 1.2V selects pulse skipping mode. In these cases, the frequency of the internal oscillator is set by the voltage on the PLLLPF pin. TRACK/SS (Pin 3/Pin 5): Tracking Input for the Controller or Optional External Soft-Start Input. This pin allows the start-up of VOUT to “track” the external voltage at this pin using an external resistor divider. The LTC3822-1 regulates the VFB voltage to the smaller of 0.6V or the voltage on the TRACK/SS pin. An internal 1µA pull-up current source is connected to this pin. Tying this pin to VIN allows VOUT start-up with the internal 1ms soft-start clamp. An external soft-start can be programmed by connecting a capacitor between this pin and ground. Do not leave this pin floating. VFB (Pin 4/Pin 6): Feedback Pin. This pin receives the remotely sensed feedback voltage for the controller from an external resistor divider across the output. ITH (Pin 5/Pin 7): Current Threshold and Error Amplifier Compensation Point. Nominal operating range on this pin is from 0.7V to 2V. The voltage on this pin determines the threshold of the main current comparator. RUN (Pin 6/Pin 8): Run Control Input. Forcing this pin below 1.1V shuts down the chip. Driving this pin to VIN or releasing this pin enables the chip to start-up. IPRG (Pin 7/Pin 10): Three-State Pin to Select the Maximum Peak Sense Voltage Threshold. This pin selects the maximum allowed voltage drop between the VIN and SW pins (i.e., the maximum allowed drop across the external topside MOSFET). Tie to VIN, GND or float to select 200mV, 82mV or 125mV respectively. 38221f 6 LTC3822-1 PIN FUNCTIONS (DD/GN) BG (Pin 8/Pin 11): Bottom Gate Driver Output. This pin drives the gate of the external bottom-side MOSFET. This pin has an output swing from GND to BOOST. TG (Pin 9/Pin 12): Top Gate Driver Output. This pin drives the gate of the external topside MOSFET. This pin has an output swing from GND to BOOST. BOOST (Pin 10/Pin 13): Positive Supply Pin for the Gate Driver Circuitry. A bootstrapped capacitor, charged with an external Schottky diode and a boost voltage source, is connected between the BOOST and SW pins. Voltage swing at the BOOST pin is from boost source voltage (typically VIN) to this boost source voltage + VIN. VIN (Pin 11/Pin 14): This pin powers the control circuitry and serves as the positive input to the differential current comparator. SW (Pin 12/Pin 16): Switch Node Connection to Inductor. This pin is also the negative input to the differential current comparator(DFN only) and an input to the reverse current comparator. Normally this pin is connected to the source of the external topside MOSFET, the drain of the external bottom-side MOSFET, and the inductor. Exposed Pad (Pin 13, DD Only): Ground. The Exposed Pad is ground and must be soldered to the PCB ground for electrical contact and optimal thermal performance. GND (Pins 1, 9 GN Only): Ground. PGOOD (Pin 4, GN Only): Power Good Output Voltage Monitor Open-Drain Logic Output. This pin is pulled to ground when the voltage on the feedback pin VFB is not within ±13.3% of its nominal set point. SENSE– (Pin 15, GN Only): Negative Input to the Differential Current Comparator. Normally this pin is connected to the source of the external topside MOSFET. 38221f 7 LTC3822-1 FUNCTIONAL DIAGRAM DB VIN VIN CB CIN SENSE – VOLTAGE REFERENCE BOOST IPRG VREF 0.6V TG SLOPE CLK + UNDERVOLTAGE LOCKOUT Q GND R ICMP SENSE+ M1 S SWITCHING LOGIC AND BLANKING CIRCUIT – VIN L VOUT COUT BOOST VIN BG M2 UVSD 0.7µA RUN GND BG t = 1ms INTERNAL SOFT-START BOOST REFRESH TIMEOUT CLK FCB IREV TRK/SS MUX TRACK/SS + SW – GND RICMP + 1µA SW ANTI-SHOOTTHROUGH SLEEP VIN 0.15V + – + OV BURSTDIS SYNC/MODE BURST DEFEAT – BURSTDIS FCB PHASE DETECTOR CLOCK DETECT + RB 0.3V PLLLPF + CLK PGOOD GND 0.54V – VFB ITH – EAMP OV UV UVSD + UV VCO VIN 0.68V RC + + – VREF 0.6V TRK/ V FB SS CC RA 38221 FD 38221f 8 LTC3822-1 OPERATION (Refer to Functional Diagram) Main Control Loop The LTC3822-1 uses a constant frequency, current mode architecture. During normal operation, the top external N-channel power MOSFET is turned on when the clock sets the RS latch, and is turned off when the current comparator (ICMP) resets the latch. The peak inductor current at which ICMP resets the RS latch is determined by the voltage on the ITH pin, which is driven by the output of the error amplifier (EAMP). The VFB pin receives the output voltage feedback signal from an external resistor divider. This feedback signal is compared to the internal 0.6V reference voltage by the EAMP. When the load current increases, it causes a slight decrease in VFB relative to the 0.6V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. While the top N-channel MOSFET is off, the bottom N-channel MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator RICMP, or the beginning of the next cycle. Shutdown, Soft-Start and Tracking Start-Up (RUN and TRACK/SS Pins) The LTC3822-1 is shut down by pulling the RUN pin low. In shutdown, all controller functions are disabled and the chip draws only 7.5µA. The TG and BG outputs are held low (off) in shutdown. Releasing the RUN pin allows an internal 0.7µA current source to pull up the RUN pin to VIN. The controller is enabled when the RUN pin reaches 1.1V. The start-up of VOUT is based on the three different connections on the TRACK/SS pin. The start-up of VOUT is controlled by the LTC3822-1’s internal soft-start when TRACK/SS is connected to VIN. During soft-start, the error amplifier EAMP compares the feedback signal VFB to the internal soft-start ramp (instead of the 0.6V reference), which rises linearly from 0V to 0.6V in about 1ms. This allows the output voltage to rise smoothly from 0V to its final value while maintaining control of the inductor current. The 1ms soft-start time can be changed by connecting the optional external soft-start capacitor CSS between the TRACK/SS and GND pins. When the controller is enabled by releasing the RUN pin, the TRACK/SS pin is charged up by an internal 1µA current source and rises linearly from 0V to above 0.6V. The error amplifier EAMP compares the feedback signal VFB to this ramp instead, and regulates VFB linearly from 0V to 0.6V. When the voltage on the TRACK/SS pin is less than the 0.6V internal reference, the LTC3822-1 regulates the VFB voltage to the TRACK/SS pin instead of the 0.6V reference. Therefore VOUT of the LTC3822-1 can track an external voltage VX during start-up. Typically, a resistor divider on VX is connected to the TRACK/SS pin to allow the start-up of VOUT to “track” that of VX. For coincident tracking during start-up, the regulated final value of VX should be larger than that of VOUT, and the resistor divider on VX should have the same ratio as the divider on VOUT that is connected to VFB. See detailed discussions in the Run and Soft-Start/ Tracking Functions in the Applications Information section. Light Load Operation (Burst Mode Operation, Continuous Conduction or Pulse Skipping Mode) (SYNC/MODE Pin) The LTC3822-1 can be programmed for either high efficiency Burst Mode operation, forced continuous conduction mode or pulse skipping mode at low load currents. To select Burst Mode operation, tie the SYNC/MODE pin to VIN. To select forced continuous operation, tie the SYNC/ MODE pin to a DC voltage below 0.4V (e.g., GND). Tying the SYNC/MODE to a DC voltage above 0.4V and below 1.2V (e.g., VFB) enables pulse skipping mode. When the LTC3822-1 is in Burst Mode operation, the peak current in the inductor is set to approximate one-fourth of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the load current, the EAMP will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.85V, the internal SLEEP signal goes high and the external MOSFETs are turned off. In sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the LTC3822-1 draws. The load current is supplied by the output capacitor. As the output voltage decreases, the EAMP increases the ITH voltage. When the ITH voltage reaches 0.925V, the SLEEP 38221f 9 LTC3822-1 OPERATION (Refer to Functional Diagram) signal goes low and the controller resumes normal operation by turning on the top N-channel MOSFET on the next cycle of the internal oscillator. When the controller is enabled for Burst Mode or pulse skipping operation, the inductor current is not allowed to reverse. Hence, the controller operates discontinuously. The reverse current comparator RICMP senses the drainto-source voltage of the bottom N-channel MOSFET. This MOSFET is turned off just before the inductor current reaches zero, preventing it from going negative. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin. The top MOSFET is turned on every cycle (constant frequency) regardless of the ITH pin voltage. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and no noise at audio frequencies. When the SYNC/MODE pin is clocked by an external clock source to use the phase-locked loop (see Frequency Selection and Phase-Locked Loop), or is set to a DC voltage between 0.4V and several hundred mV below VIN, the LTC3822-1 operates in PWM pulse skipping mode at light loads. In this mode, the current comparator ICMP may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles. The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. However, it provides low current efficiency higher than forced continuous mode, but not nearly as high as Burst Mode operation. During start-up or an undervoltage condition (VFB ≤ 0.54V), the LTC3822-1 operates in pulse skipping mode (no current reversal allowed), regardless of the state of the SYNC/MODE pin. Short-Circuit Protection The LTC3822-1 monitors VFB to detect a short-circuit on VOUT. When VFB is near ground, switching frequency is reduced to prevent the inductor current from running away. The oscillator frequency will progressively return to normal when VFB rises above ground. This feature is disabled during start-up. Output Overvoltage Protection As further protection, the overvoltage comparator (OVP) guards against transient overshoots, as well as other more serious conditions that may overvoltage the output. When the feedback voltage on the VFB pin has risen 13.33% above the reference voltage of 0.6V, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage is cleared. Frequency Selection and Phase-Locked Loop (PLLLPF and SYNC/MODE Pins) The selection of switching frequency is a tradeoff between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3822-1’s controllers can be selected using the PLLLPF pin. If the SYNC/MODE is not being driven by an external clock source, the PLLLPF can be floated, tied to VIN or tied to GND to select 550kHz, 750kHz or 300kHz, respectively. A phase-locked loop (PLL) is available on the LTC3822-1 to synchronize the internal oscillator to an external clock source that connects to the SYNC/MODE pin. In this case, a series RC should be connected between the PLLLPF pin and GND to serve as the PLL’s loop filter. The LTC3822-1 phase detector adjusts the voltage on the PLLLPF pin to align the turn-on of the top MOSFET to the rising edge of the synchronizing signal. The typical capture range of the LTC3822-1’s phase-locked loop is from approximately 200kHz to 1MHz. Boost Capacitor Refresh Timeout In order to maintain sufficient charge on CB, the converter will briefly turn off the top MOSFET and turn on the bottom MOSFET if at any time the bottom MOSFET has remained off for 10 cycles. This most commonly occurs in a dropout situation where VIN is close to VOUT. 38221f 10 LTC3822-1 OPERATION (Refer to Functional Diagram) Undervoltage Lockout To prevent operation of the MOSFETs below safe input voltage levels, an undervoltage lockout is incorporated in the LTC3822-1. When the input supply voltage (VIN) drops below 2.25V, the external MOSFETs and all internal circuits are turned off except for the undervoltage block, which draws only a few microamperes. Peak Current Sense Voltage Selection and Slope Compensation (IPRG Pin) When the LTC3822-1 controller is operating below 20% duty cycle, the peak current sense voltage (between the VIN and SENSE–/SW pins) allowed across the external top MOSFET is determined by: ∆VSENSE(MAX ) ≈ A • VITH – 0.7 V 10 However, once the controller’s duty cycle exceeds 20%, slope compensation begins and effectively reduces the peak sense voltage by a scale factor (SF) given by the curve in Figure 1. The peak inductor current is determined by the peak sense voltage and the on-resistance of the main MOSFET: IPK = RDS(ON) If a sense resistor is used, ΔVSENSE(MAX) is the peak current sense voltage (between the VIN and SENSE–/SW pins) across the sense resistor. The peak inductor is determined by the peak sense voltage and the resistance of the sense resistor: IPK = where A is a constant determined by the state of the IPRG pin. Floating the IPRG pin selects A = 1; tying IPRG to VIN selects A = 5/3; tying IPRG to GND selects A = 2/3. The maximum value of VITH is typically about 1.98V, so the maximum sense voltage allowed across the external main MOSFET is 125mV, 200mV or 82mV for the three respective states of the IPRG pin. ∆VSENSE(MAX ) ∆VSENSE(MAX ) RSENSE Power Good (PGOOD) Pin (GN Only) A window comparator monitors the feedback voltage and pulls the open-drain PGOOD output pin low when the feedback voltage is not within ±10% of the 0.6V reference voltage. PGOOD is low when the LTC3822-1 is shut down or in undervoltage lockout. 110 100 90 SF = I/IMAX (%) 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 38221 F01 Figure 1. Maximum Peak Current vs Duty Cycle 38221f 11 LTC3822-1 APPLICATIONS INFORMATION The typical LTC3822-1 application circuit is shown on the front page of this data sheet. External component selection for the controller is driven by the load requirement and begins with the selection of the inductor and the power MOSFETs. Power MOSFET Selection The LTC3822-1’s controller requires external N-channel power MOSFETs for the topside (main) and bottom (synchronous) switches. The main selection criteria for the power MOSFETs are the breakdown voltage VBR(DSS), threshold voltage VGS(TH), on-resistance RDS(ON), reverse transfer capacitance CRSS, turn-off delay tD(OFF) and the total gate charge QG. The gate drive voltage is usually the input supply voltage. Since the LTC3822-1 is designed for operation at low input voltages, a sublogic level MOSFET (RDS(ON) guaranteed at VGS = 2.5V) is required. A reasonable starting point is setting ripple current IRIPPLE to be 40% of IOUT(MAX). Rearranging the above equation yields: RDS(ON)MAX = 5 ∆VSENSE(MAX ) • for Dutyy Cycle < 20% 6 IOUT(MAX ) However, for operation above 20% duty cycle, slope compensation has to be taken into consideration to select the appropriate value of RDS(ON) to provide the required amount of load current: RDS(ON)MAX = ∆VSENSE(MAX ) 5 • SF • 6 IOUT(MAX ) where SF is a scale factor whose value is obtained from the curve in Figure 1. These must be further derated to take into account the significant variation in on-resistance with temperature. The following equation is a good guide for determining the required RDS(ON)MAX at 25°C (manufacturer’s specification), allowing some margin for variations in the LTC3822-1 and external component values: The topside MOSFET’s on-resistance is chosen based on the required load current. The maximum average load current IOUT(MAX) is equal to the peak inductor current minus half the peak-to-peak ripple current IRIPPLE. The LTC3822-1’s current comparator monitors the drain-tosource voltage VDS of the top MOSFET, which is sensed between the VIN and SW pins. The peak inductor current is limited by the current threshold, set by the voltage on the ITH pin, of the current comparator. The voltage on the ITH pin is internally clamped, which limits the maximum current sense threshold ΔVSENSE(MAX) to approximately 125mV when IPRG is floating (82mV when IPRG is tied low; 200mV when IPRG is tied high). The ρT is a normalizing term accounting for the temperature variation in on-resistance, which is typically about 0.4%/°C, as shown in Figure 2. Junction-to-case temperature ΔTJC is about 10°C in most applications. For a maximum ambient temperature of 70°C, using ρ80°C ≈ 1.3 in the above equation is a reasonable choice. The output current that the LTC3822-1 can provide is given by: ∆VSENSE(MAX ) IRIPPLE IOUT(MAX ) = – RDS(ON) 2 The power dissipated in the MOSFETs strongly depends on their respective duty cycles and load current. When the LTC3822-1 is operating in continuous mode, the duty cycles for the MOSFETs are: where IRIPPLE is the inductor peak-to-peak ripple current (see Inductor Value Calculation). RDS(ON)MAX = ∆VSENSE(MAX ) 5 • 0.9 • SF • 6 IOUT(MAX ) • ρT Top MOSFET Duty Cycle = VOUT VIN Bottom MOSFET Duty Cycle = VIN – VOUT VIN 38221f 12 LTC3822-1 APPLICATIONS INFORMATION gate drive (VIN) voltage, the MOSFETs ultimately should be evaluated in the actual LTC3822-1 application circuit to ensure proper operation. ρT NORMALIZED ON RESISTANCE 2.0 1.5 Shoot-through between the MOSFETs can most easily be spotted by monitoring the input supply current. As the input supply voltage increases, if the input supply current increases dramatically, then the likely cause is shoot-through. 1.0 0.5 0 – 50 Run and Soft-Start/Tracking Functions 50 100 0 JUNCTION TEMPERATURE (°C) 150 38221 F02 Figure 2. RDS(ON) vs Temperature The MOSFET power dissipations at maximum output current are: PTOP = VOUT 2 •I • ρT • RDS(ON) + 2 • VIN2 VIN OUT(MAX ) The LTC3822-1 has a low power shutdown mode which is controlled by the RUN pin. Pulling the RUN pin below 1.1V puts the LTC3822-1 into a low quiescent current shutdown mode (IQ = 7.2µA). Releasing the RUN pin, an internal 0.7µA (at VIN = 3.3V) current source will pull the RUN pin up to VIN, which enables the controller. The RUN pin can be driven directly from logic as showed in Figure 3. 3.3V LTC3822-1 RUN • IOUT(MAX ) • CRSS • f PBOT = VIN – VOUT • IOUT(MAX )2 • ρT • RDS(ON) VIN Both MOSFETs have I2R losses and the PTOP equation includes an additional term for transition losses, which are largest at high input voltages. The bottom MOSFET losses are greatest at high input voltage or during a short-circuit when the bottom duty cycle is 100%. The LTC3822-1 utilizes a non-overlapping, anti-shootthrough gate drive control scheme to ensure that the MOSFETs are not turned on at the same time. To function properly, the control scheme requires that the MOSFETs used are intended for DC/DC switching applications. Many power MOSFETs are intended to be used as static switches and therefore are slow to turn on or off. Reasonable starting criteria for selecting the MOSFETs are that they must typically have a gate charge (QG) less than 30nC (at 2.5VGS) and a turn-off delay (tD(OFF)) of less than approximately 140ns. However, due to differences in test and specification methods of various MOSFET manufacturers, and in the variations in QG and tD(OFF) with LTC3822-1 RUN 38221 F03 Figure 3. RUN Pin Interfacing Once the controller is enabled, the start-up of VOUT is controlled by the state of the TRACK/SS pin. If the TRACK/SS pin is connected to VIN, the start-up of VOUT is controlled by internal soft-start, which slowly ramps the positive reference to the error amplifier from 0V to 0.6V, allowing VOUT to rise smoothly from 0V to its final value. The default internal soft-start time is around 1ms. The soft-start time can be changed by placing a capacitor between the TRACK/SS pin and GND. In this case, the soft-start time will be approximately: tSS = CSS • 600mV 1µA where 1µA is an internal current source which is always on. When the voltage on the TRACK/SS pin is less than the internal 0.6V reference, the LTC3822-1 regulates the VFB voltage to the TRACK/SS pin voltage instead of 0.6V. Therefore the start-up of VOUT can ratiometrically track 38221f 13 LTC3822-1 APPLICATIONS INFORMATION an external voltage VX, according to a ratio set by a resistor divider at TRACK/SS pin (Figure 4a). The ratiometric relation between VOUT and VX is (Figure 4c): VOUT RTA RA + RB = • VX RA RTA + RTB For coincident tracking (VOUT = VX during start-up), RTA = RA, RTB = RB Table 1. The States of the TRACK/SS Pin TRACK/SS Pin FREQUENCY Capacitor CSS External Soft-Start VIN Internal Soft-Start Resistor Divider VOUT Tracking an External Voltage VX Phase-Locked Loop and Frequency Synchronization VX should always be greater than VOUT when using the tracking function of TRACK/SS pin. The internal current source (1µA), which is for external soft-start, will cause a tracking error at VOUT. For example, if a 59k resistor is chosen for RTA, the RTA current will be about 10µA (600mV/59k). In this case, the 1µA internal current source will cause about 10% (1µA/10µA • 100%) tracking error, which is about 60mV (600mV • 10%) referred to VFB. This is acceptable for most applications. If a better tracking accuracy is required, the value of RTA should be reduced. VOUT VX LTC3822-1 RTB Table 1 summarizes the different states in which TRACK/SS can be used. RB VFB RA TRACK/SS RTA 38221 F05a Figure 4a. Using the TRACK/SS Pin to Track VX The LTC3822-1 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the external top MOSFET to be locked to the rising edge of an external clock signal applied to the SYNC/MODE pin. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the external filter network connected to the PLLLPF pin. The relationship between the voltage on the PLLLPF pin and operating frequency, when there is a clock signal applied to SYNC/MODE, is shown in Figure 5 and specified in the electrical characteristics table. Note that the LTC3822-1 can only be synchronized to an external clock whose frequency is within range of the LTC3822-1’s internal VCO, which is nominally 200kHz to 1MHz. This is guaranteed, VOUT VX OUTPUT VOLTAGE OUTPUT VOLTAGE VX VOUT 38221 F04b,c TIME TIME (4b) Coincident Tracking (4c) Ratiometric Tracking Figure 4b and 4c. Two Different Modes of Output Voltage Tracking 38221f 14 LTC3822-1 APPLICATIONS INFORMATION over temperature and process variations, to be between 250kHz and 750kHz. A simplified block diagram is shown in Figure 6. If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the PLLLPF pin. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the PLLLPF pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the PLLLPF pin is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor CLP holds the voltage. The loop filter components, CLP and RLP, smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. These filter components determine how fast the loop acquires lock. Typically RLP = 10k and CLP is 2200pF to 0.01µF. Typically, the external clock (on SYNC/MODE pin) input high level is 1.6V, while the input low level is 1.2V. Table 2 summarizes the different states in which the PLLLPF pin can be used. Table 2. The States of the PLLLPF Pin PLLLPF PIN SYNC/MODE PIN FREQUENCY 0V DC Voltage 300kHz Floating DC Voltage 550kHz VIN DC Voltage 750kHz RC Loop Filter Clock Signal Phase-Locked to External Clock 1200 Using a Sense Resistor (GN Only) FREQUENCY (kHz) 1000 A sense resistor RSENSE can be connected between VIN and SENSE– to sense the output load current. In this case, the drain of the topside N-channel MOSFET is connected to SENSE– pin and the source is connected to the SW pin of the LTC3822-1. Therefore the current comparator monitors the voltage developed across RSENSE, not the VDS of the top MOSFET. The output current that the LTC3822-1 can provide in this case is given by: 800 600 400 200 0 0.2 0.7 1.2 1.7 PLLLPF PIN VOLTAGE (V) 2.2 IOUT(MAX ) = 38221 F05 Figure 5. Relationship Between Oscillator Frequency and Voltage at the PLLLPF Pin When Synchronizing to an External Clock RSENSE = CLP SYNC/ MODE EXTERNAL OSCILLATOR PLLLPF DIGITAL PHASE/ FREQUENCY DETECTOR OSCILLATOR 38221 F06 RSENSE – IRIPPLE 2 Setting ripple current as 40% of IOUT(MAX) and using Figure 1 to choose SF, the value of RSENSE is: 2.4V RLP ∆VSENSE(MAX ) ∆VSENSE(MAX ) 5 • SF • 6 IOUT(MAX ) Variation in the resistance of a sense resistor is much smaller than the variation in on-resistance of an external MOSFET. Therefore the load current is well controlled with a sense resistor. However the sense resistor causes I2R losses in addition to those of the MOSFET. Therefore, using a sense resistor lowers the efficiency of LTC3822-1, especially at high load current. Figure 6. Phase-Locked Loop Block Diagram 38221f 15 LTC3822-1 APPLICATIONS INFORMATION Burst Mode Operation Considerations The choice of RDS(ON) and inductor value also determines the load current at which the LTC3822-1 enters Burst Mode operation. When bursting, the controller clamps the peak inductor current to approximately: IBURST(PEAK ) = 1 ∆VSENSE(MAX ) • 4 RDS(ON) Inductor Value Calculation Given the desired input and output voltages, the inductor value and operating frequency fOSC directly determine the inductor’s peak-to-peak ripple current: IRIPPLE = VOUT ⎛ VIN – VOUT ⎞ VIN ⎜⎝ fOSC • L ⎟⎠ Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however, requires a large inductor. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: L≥ VIN – VOUT VOUT • fOSC • IRIPPLE VIN Inductor Core Selection Once the inductance value is determined, the type of inductor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Schottky Diode Selection (Optional) The Schottky diode D in Figure 10 conducts current during the dead time between the conduction of the power MOSFETs. This prevents the body diode of the bottom N-channel MOSFET from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency. A 1A Schottky diode is generally a good size for most applications, since it conducts a relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. This diode may be omitted if the efficiency loss can be tolerated. CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (VOUT/VIN). To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: VOUT • (VIN – VOUT ) 1/ 2 CIN Re quired IRMS ≈ IMAX • VIN This formula has a maximum value at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet the size or height requirements in the design. Due to the high operating frequency of the LTC3822-1, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can 38221f 16 LTC3822-1 APPLICATIONS INFORMATION The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (ΔVOUT) is approximated by: VOUT ⎛ 1 ≈ IRIPPLE • ⎜ESR + 8• f •C ⎝ OUT VOUT LTC3822-1 RB CFF VFB RA ⎞ ⎟⎠ 38221 F07 Figure 7. Setting the Output Voltage Topside MOSFET Drive Supply (CB, DB) In the Functional Diagram, external bootstrap capacitor CB is charged from a boost power source (usually VIN) through diode DB when the SW node is low. When a MOSFET is to be turned on, the CB voltage is applied across the gate source of the desired device. When the topside MOSFET is on, the BOOST pin voltage is above the input supply. VBOOST = 2VIN. CB must be 100 times the total input capacitance of the topside MOSFET. The reverse breakdown of DB must be greater than VIN(MAX). Note that in applications where the supply voltage to CB exceeds VIN, the boost pin will draw approximately 500µA in shutdown mode. Setting Output Voltage The LTC3822-1 output voltage is set by an external feedback resistor divider carefully placed across the output, as shown in Figure 7. The regulated output voltage is determined by: ⎛ R ⎞ VOUT = 0.6 V • ⎜1+ B ⎟ ⎝ RA ⎠ For most applications, a 59k resistor is suggested for RA. In applications where minimizing the quiescent current is critical, RA should be made bigger to limit the feedback divider current. If RB then results in very high impedance, it may be beneficial to bypass RB with a 10pF to 100pF capacitor CFF. Low Input Supply Voltage Although the LTC3822-1 can function down to below 2.4V, the maximum allowable output current is reduced as VIN decreases below 3V. Figure 8 shows the amount of change as the supply is reduced down to 2.4V. Also shown is the effect on VREF. 105 NORMALIZED VOLTAGE OR CURRENT (%) where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increase with input voltage. VREF 100 95 MAXIMUM SENSE VOLTAGE 90 85 80 75 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 INPUT VOLTAGE (V) 38221 F08 Figure 8. Line Regulation of VREF and Maximum Sense Voltage Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest amount of time that the LTC3822-1 is capable of turning the top MOSFET on. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle and high frequency applications may approach the minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT fOSC • VIN 38221f 17 LTC3822-1 APPLICATIONS INFORMATION If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC3822-1 will begin to skip cycles. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. The minimum on-time for the LTC3822-1 is typically about 170ns. However, as the peak sense voltage (IL(PEAK) • RDS(ON)) decreases, the minimum on-time gradually increases up to about 260ns. Other losses, including CIN and COUT ESR dissipative losses and inductor core losses, generally account for less than 2% total additional loss. Efficiency Considerations Checking Transient Response The efficiency of a switching regulator is equal to the output power divided by the input power. It is often useful to analyze individual losses to determine what is limiting efficiency and which change would produce the most improvement. Efficiency can be expressed as: The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ΔILOAD) • (ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. Efficiency = 100% – (L1 + L2 + L3 + …) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3822-1 circuits: 1) LTC3822-1 DC bias current, 2) MOSFET gate charge current, 3) I2R losses and 4) transition losses. 1) The VIN (pin) current is the DC supply current, given in the Electrical Characteristics, which excludes MOSFET driver currents. VIN current results in a small loss that increases with VIN. 2) MOSFET gate charge current results from switching the gate capacitance of the power MOSFET. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from BOOST to ground. The resulting dQ/dt is a current out of BOOST, which is typically much larger than the VIN supply current. In continuous mode, IGATECHG = f • QP. 3) I2R losses are calculated from the DC resistances of the MOSFETs, inductor and/or sense resistor. In continuous mode, the average output current flows through L but is “chopped” between the top MOSFET and the bottom MOSFET. Each MOSFET’s RDS(ON) can be multiplied by its respective duty cycle and summed together with the DCR of the inductor to obtain I2R losses. 4) Transition losses apply to the external MOSFET and increase with higher operating frequencies and input voltages. Transition losses can be estimated from: Transition Loss = 2 • VIN2 • IO(MAX) • CRSS • f The ITH series RC-CC filter (see the Functional Diagram) sets the dominant pole-zero loop compensation. The ITH external components showed in the figure on the first page of this data sheet will provide adequate compensation for most applications. The values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitor needs to be decided upon because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation 38221f 18 LTC3822-1 APPLICATIONS INFORMATION components, including a review of control loop theory, refer to Application Note 76. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25) • (CLOAD). Thus a 10µF capacitor would be require a 250µs rise time, limiting the charging current to about 200mA. Design Example For a design example, VIN will be a 3.3V power supply. Output voltage is 1.8V with a load current requirement of 8A. The IPRG pin will be tied to VIN and PLLLPF will be left floating, so the maximum current sense threshold ΔVSENSE(MAX) will be approximately 200mV and the switching frequency will be 550kHz. Duty Cycle = VOUT = 54.5% VIN From Figure 1, SF = 88%. RDS(ON)MAX = ∆VSENSE(MAX ) 5 • 0.9 • SF • = 0.013Ω 6 IOUT(MAX ) • ρT The Si4466DY has an RDS(ON) of 0.013Ω. To prevent inductor saturation during a short circuit, the inductor current rating should be higher than 16A. For 3.2A IRIPPLE, the required minimum inductor value is: LMIN = 1.8 V ⎛ 1.8 V ⎞ • ⎜1 – = 0.47µH 550kHz • 4A ⎝ 3.3V ⎟⎠ A Vishay IHLP2525CZ-01 (0.47µH, 17.5A) inductor works well for this application. CIN will require an RMS current rating of at least 5A at temperature. A low ESR ceramic COUT will allow approximately 15mV output ripple. Figure 10 shows an 8A, 3.3VIN/1.8VOUT application. PC Board Layout Checklist When laying out the printed circuit board, use the following checklist to ensure proper operation of the LTC3822-1. Figure 9 shows a suggested PCB floorplan. • The power loop (input capacitor, MOSFET, inductor, output capacitor) and high di/dt loop (VIN, through both MOSFETs to power GND and back through CIN to VIN) should be as small as possible and located on one layer. Excess inductance here can cause increased stress on the MOSFETs and increased high frequency ringing on the output. • Put the feedback resistors close to the VFB pins. The ITH compensation components should also be very close to the LTC3822-1. All small-signal circuitry should be isolated from the main switching loop with ground Kelvin connected to the output capacitor ground. • The current sense traces (VIN and SW) should be Kelvin connected right at the topside MOSFET source and drain. The positive current sense pin is shared with the VIN pin. This must not be locally decoupled with a capacitor. • Keep the switch node (SW) and the gate driver nodes (TG, BG) away from the small-signal components, especially the feedback resistors, and ITH compensation components. • Place CB as close as possible to the SW and BOOST pins. This capacitor carries high di/dt MOSFET gate drive currents. The charging current to the boost diode should be provided from a separate VIN trace than that to the VIN pin. • Beware of ground loops in multiple layer PC boards. Try to maintain one central signal ground node on the board. If the ground plane must be used for high DC currents, keep that path away from small-signal components. 38221f 19 LTC3822-1 APPLICATIONS INFORMATION VIN CIN M1 GND L1 SW M2 VOUT COUT GND U1 AND OTHER SMALL-SIGNAL COMPONENTS GND SENSE TRACE 38221 F09 Figure 9. LTC3822-1 Suggested PCB Floorplan 10.2k TRACK/SS IPRG VIN SYNC/MODE RUN TG PLLLPF LTC3822EDD-1 SW ITH BOOST 27pF 1000pF GND 59k 1% BG 22µF ×2 FDS6898A 0.22µF IHLP-2525CZ-01 0.47µH VIN 2.75V TO 4.5V VOUT 1.8V 47µF* 8A ×2 D OPTIONAL VFB 118k 1% 38221 F10 *TDK C3216X5R0JL176M 27pF Figure 10. 3.3VIN 1.8V/8A High Efficiency 550kHz Step-Down Converter 38221f 20 LTC3822-1 APPLICATIONS INFORMATION 1M TRACK/SS IPRG VIN SYNC/MODE RUN TG PGOOD – SENSE PLLLPF SW LTC3822EGN-1 ITH BOOST 33pF Si7882DP 47µF ×2 0.56µH** VOUT 1.8V 100µF* 12A ×2 0.22µF 13.7k 680pF GND 59k 1% BG VIN 3.3V Si7882DP VFB 118k 1% 38221 F07 *TAIYO YUDEN JMK325BJ107MM **TOKO FDU0650 68pF Figure 11. 3.3VIN 1.8V/12A High Efficiency High Current 300kHz Step-Down Converter Efficiency Load Step 95 90 EFFICIENCY (%) VOUT 200mV/DIV AC COUPLED Burst Mode OPERATION 85 80 75 PULSE SKIPPING CONTINUOUS MODE 70 INDUCTOR CURRENT 5A/DIV 65 60 55 50 10 100 1000 10000 LOAD CURRENT (mA) 100000 38221 F11c 50µs/DIV VIN = 3.3V VOUT = 1.8V FORCED CONTINUOUS MODE 1A TO 6A 38221 F11b 38221f 21 LTC3822-1 APPLICATIONS INFORMATION EXTERNAL OSCILLATOR 700kHz 10nF 10k 64.9k TRACK/SS IPRG VIN SYNC/MODE RUN TG PLLLPF LTC3822EDD-1 SW ITH BOOST 22µF ×2 Si7940DP VIN 3.3V 0.20µH** 0.20µF 10µF X5R 33pF VOUT 1.1V 220µF* 8A 470pF GND 59k 1% BG Si7940DP VFB 49.9k 1% 38221 F12a *SANYO 2R5TPE220M9 **TOKO FDV0630 82pF Figure 12. Externally Synchronized 700kHz, 3.3VIN, 1.1V/8A Step-Down Converter Efficiency Load Step 90 80 VOUT 50mV/DIV AC COUPLED EFFICIENCY (%) 70 60 50 INDUCTOR CURRENT 2A/DIV 40 30 20 10 0 10 100 1000 LOAD CURRENT (mA) 10000 50µs/DIV VIN = 3.3V VOUT = 1.1V LOAD STEP 300mA TO 3.3A 38221 F12c 38221 F12b 38221f 22 LTC3822-1 PACKAGE DESCRIPTION DD Package 12-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1725 Rev A) R = 0.115 TYP 7 0.40 ± 0.10 12 0.70 ±0.05 3.50 ±0.05 2.10 ±0.05 2.38 ±0.05 1.65 ±0.05 2.38 ±0.10 3.00 ±0.10 (4 SIDES) 1.65 ± 0.10 PIN 1 NOTCH R = 0.20 OR 0.25 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) PACKAGE OUTLINE 6 0.25 ± 0.05 1 0.23 ± 0.05 0.45 BSC 0.75 ±0.05 0.200 REF 0.45 BSC 2.25 REF 2.25 REF (DD12) DFN 0106 REV A 0.00 – 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) .0532 – .0688 (1.35 – 1.75) 2 3 4 5 6 7 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 38221f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC3822-1 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1628/LTC3728 Dual High Efficiency, 2-Phase Synchronous Step Down Controllers Constant Frequency, Standby, 5V and 3.3V LDOs, VIN to 36V, 28-Lead SSOP LTC1735 High Efficiency Synchronous Step-Down Controller Burst Mode Operation, 16-Pin Narrow SSOP, Fault Protection, 3.5V ≤ VIN ≤ 36V LTC1778 No RSENSE, Synchronous Step-Down Controller Current Mode Operation Without Sense Resistor, Fast Transient Response, 4V ≤ VIN ≤ 36V LTC3411 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT ≥ 0.8V, IQ = 60µA, ISD = <1µA, MS Package LTC3412 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT ≥ 0.8V, IQ = 60µA, ISD = <1µA, TSSOP-16E Package LTC3416 4A, 4MHz, Monolithic Synchronous Step-Down Regulator Tracking Input to Provide Easy Supply Sequencing, 2.25V ≤ VIN ≤ 5.5V, 20-Lead TSSOP Package LTC3418 8A, 4MHz, Synchronous Step-Down Regulator Tracking Input to Provide Easy Supply Sequencing, 2.25V ≤ VIN ≤ 5.5V, QFN Package LTC3708 2-Phase, No RSENSE, Dual Synchronous Controller with Output Tracking Constant On-Time Dual Controller, VIN Up to 36V, Very Low Duty Cycle Operation, 5mm × 5mm QFN Package LTC3736/LTC3736-2 2-Phase, No RSENSE, Dual Synchronous Controller with Output Tracking 2.75V ≤ VIN ≤ 9.8V, 0.6V ≤ VOUT ≤ VIN, 4mm × 4mm QFN LTC3736-1 Low EMI 2-Phase, Dual Synchronous Controller with Output Tracking Integrated Spread Spectrum for 20dB Lower “Noise,” 2.75V ≤ VIN ≤ 9.8V LTC3737 2-Phase, No RSENSE, Dual DC/DC Controller with Output Tracking 2.75V ≤ VIN ≤ 9.8V, 0.6V ≤ VOUT ≤ VIN, 4mm × 4mm QFN LTC3772/LTC3772B Micropower No RSENSE Step-Down DC/DC Controller 2.75V ≤ VIN ≤ 9.8V, 3mm × 2mm DFN or 8-Lead SOT-23, LTC3776 Dual, 2-Phase, No RSENSE Synchronous Controller for DDR/ Provides VDDQ and VTT with One IC, 2.75V ≤ VIN ≤ 9.8V, Adjustable QDR Memory Termination Constant Frequency with PLL Up to 850kHz, Spread Spectrum Operation, 4mm × 4mm QFN and 24-Lead SSOP Packages LTC3808 Low EMI, Synchronous Controller with Output Tracking LTC3809/LTC3809-1 No RSENSE Synchronous Controller with Output Tracking 2.75V ≤ VIN ≤ 9.8V, 4mm × 3mm DFN, Spread Spectrum for 20dB Lower Peak Noise 2.75V ≤ VIN ≤ 9.8V, 3mm × 3mm DFN and 10-Lead MSOPE Packages LTC3822 No RSENSE Low Input Voltage, All N-Channel MOSFET, Synchronous Step-Down DC/DC Controller 2.75V ≤ VIN ≤ 4.5V, 0.6V ≤ VOUT ≤ VIN, 10-Lead MS and 3mm × 3mm DFN Packages LTC3830 High Power Synchronous Step-Down Controller for Low Voltages (3V to 8V) 3V ≤ VIN ≤ 8V, 500kHz, S8, S16 and SSOP-16 Packages LTC3836 Dual No RSENSE Low Input Voltage, All N-Channel MOSFET, 2.75V ≤ VIN ≤ 4.5V, 0.6V ≤ VOUT ≤ VIN, 4mm × 5mm QFN and Synchronous Step-Down DC/DC Controller 28-Lead SSOP Packages 38221f 24 Linear Technology Corporation LT 1006 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006