SLA7060M Datasheet

SLA7060M THRU
SLA7062M
Data Sheet
28210.10B
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UNIPOLAR STEPPER-MOTOR
TRANSLATOR/DRIVERS
ABSOLUTE MAXIMUM RATINGS
Driver Supply Voltage, VBB ................ 46 V
Load Supply Voltage, VM .................. 46 V
Output Current, IO
SLA7060M ................................. 1.0 A*
SLA7061M ................................. 2.0 A*
SLA7062M ................................. 3.0 A*
Logic Supply Voltage, VDD ............... 7.0 V
Logic Input Voltage Range,
VI .......................... -0.3 V to VDD+ 0.3 V
Sense Voltage, VS ........................ ±2.0 V†
Reference Input Voltage Range,
VREF ............................... -0.3 V to VDD+ 0.3 V
Package Power Dissipation,
PD ....................................... See Graph
Junction Temperature, TJ ............ +150°C
Operating Temperature Range,
TA ................................. -20°C to +85°C
Storage Temperature Range,
TS ............................... -30°C to +150°C
* Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any set of
conditions, do not exceed the specified current rating or
junction temperature.
† Internal filtering provides protection against transients
during the first 1 μs of the current-sense pulse.
Combining low-power CMOS logic with high-current, high-voltage
power FET outputs, the Series SLA7060M translator/drivers provide
complete control and drive for a two-phase unipolar stepper motor with
internal fixed off time and pulse-width modulation (PWM) control of
the output current in a power multi-chip module (PMCM™). There are
no phase-sequence tables, high-frequency control lines, or complex
interfaces to program.
The CMOS logic section provides the sequencing logic, direction,
control, synchronous/asynchronous PWM operation, and a “sleep”
function. The minimum CLOCK input is an ideal fit for applications
where a complex μP is unavailable or overburdened. TTL or LSTTL
may require the use of appropriate pull-up resistors to ensure a proper
input-logic high. For PWM current control, the maximum output
current is determined by the user’s selection of a reference voltage and
sensing resistor. The NMOS outputs are capable of sinking up to 1, 2,
or 3 A (depending on device) and withstanding 46 V in the off state.
Clamp diodes provide protection against inductive transients. Special
power-up sequencing is not required.
Half-, quarter-, eighth-, and sixteenth-step operation are externally
selectable for the SLA7060/61/62M. Half-step excitation alternates
between the one-phase and two-phase modes (AB-B-AB-A-AB-B-ABA), providing an eight-step sequence.
The Series SLA7060M is supplied in a 21-pin single in-line powertab package with leads formed for vertical mounting (suffix LF2102).
The tab is at ground potential and needs no insulation. For high-current
or high-frequency applications, external heat sinking may be required.
This device is rated for continuous operation between -20°C and
+85°C.
FEATURES
 To 3 A Output Rating
 Internal Sequencer for Microstepping Operation
 PWM Constant-Current Motor Drive
 Cost-Effective, Multi-Chip Solution
 100 V, Avalanche-Rated NMOS
 Low rDS(on) NMOS Outputs
 Advanced, Improved Body Diodes
 Inputs Compatible with 3.3 V or 5 V Control Signals
 Sleep Mode
 Internal Clamp Diodes
Always order by complete part number, e.g., SLA7060MLF2102 .
SANKEN ELECTRIC CO., LTD.
http://www.sanken-ele.co.jp/en/
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SLA7060M THRU SLA7062M
UNIPOLAR STEPPER-MOTOR
TRANSLATOR/DRIVERS
Functional block diagram
Recommended operating conditions
Load Supply Voltage, VBB ......................... 10 to 44 V
Logic Supply Voltage, VDD ................... 3.0 V to 5.5 V
Reference Input Voltage, VREF ............. 0.1 V to 1.0 V
Tab Temperature (no heat sink), TT ................. <90°C
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Electrical characteristics: unless otherwise noted at TA = +25°C, VBB = 24 V, VDD = 5.0 V.
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Operating
10
—
44
V
Output drivers
Driver Supply Volt. Range
VBB
Drain-Source Breakdown
V(BR)DS
VBB = 44 V, ID = 1 mA
100
—
—
V
Output On Resistance
rDS(on)
SLA7060M, IO = 1.0 A
—
700
850
mΩ
SLA7061M, IO = 2.0 A
—
250
400
mΩ
SLA7062M, IO = 3.0 A
—
180
240
mΩ
SLA7060M, IF = 1.0 A
—
0.85
1.1
V
SLA7061M, IF = 2.0 A
—
0.95
1.2
V
SLA7062M, IF = 3.0 A
—
0.95
2.1
V
—
—
15
mA
VREF > 2.0 V (sleep mode)
—
—
100
μA
Operating
3.0
5.0
5.5
V
Body Diode Forward Volt.
Driver Supply Current
VF
IBB
Control logic
Logic Supply Volt. Range
VDD
Logic Input Voltage
VIH
0.75VDD
—
—
V
VIL
—
—
0.25VDD
V
IIH
—
±1.0
—
μA
CLOCK, RESET, CW/CCW, and SYNC.
—
±1.0
—
μA
M1 and M2
-25
-50
-75
μA
Logic Input Current
IIL
Max. Clock Frequency
fclk
PWM Off Time
toff
PWM Min. On Time
ton(min)
Ref. Input Voltage Range
VREF
250*
—
—
kHz
70 to 100%Itripmax
—
12
—
μs
38 to 64%Itripmax
—
9.0
—
μs
9 to 30%Itripmax
—
7.0
—
μs
—
1.8
—
μs
0
—
1.5
V
2.0
—
VDD
V
Operating
Sleep mode
Ref. Input Current
IREF
—
±10
—
μA
Monitor Output Voltage
VMoH
VDD - 1.25
—
—
V
VMoL
—
—
1.25
V
IMo
—
—
±3.0
mA
0.95VREF
VREF
1.05VREF
V
—
±10
—
μA
Monitor Output Current
Sense Voltage
Sense Input Current
Propagation Delay Time
Logic Supply Current
VS
Trip point at 100% IO
ISENSE
tPLH
Clock rising edge to output on
—
2.0
—
μs
tPHL
Clock rising edge to output off
—
1.5
—
μs
—
—
4.0
mA
IDD
Typical values are given for circuit design information only.
*Operation at a clock frequency greater than the specified minimum value is possible but not warranted.
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Logic input timing
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Typical MOSFET characteristics
SLA7060M
TL [°C]
SLA7061M
TL [°C]
SLA7062M
TL [°C]
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SLA7060M THRU SLA7062M
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TRANSLATOR/DRIVERS
Typical body diode characteristics
SLA7060M
TL [°C]
SLA7061M
TL [°C]
SLA7062M
TL [°C]
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TRANSLATOR/DRIVERS
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Functional description
Device operation. These devices are complete
microstepping motor drivers with built in translator for
easy operation with minimal control lines. They are
designed to operate unipolar stepper motors in half-,
quarter-, eighth-, and sixteenth-step modes. The current in
each of the four outputs, all n-channel DMOS, is regulated
with fixed off time pulse-width modulated (PWM) control
circuitry. The current at each step is set by the value of an
external current-sense resistor (RS), a reference voltage
(VREF), and the DAC’s output voltage controlled by the
output of the translator.
At VDD power up, or reset, the translator sets the
DACs to the home state (see figures for reset conditions).
When a step command signal occurs on the CLOCK input
the translator automatically sequences the DACs to the
next level (see table 2 for the current level sequence). The
microstep resolution is set by inputs M1 and M2 as shown
in table 1.
RESET input. The RESET input sets the translator to a
predefined home state (see table 2); this is not the same as
the sleep mode. The monitor output (MO) goes low and
all STEP inputs are ignored until the RESET input goes
low. A low-pass filter is integrated into the reset circuit;
therefore a 5 μs delay is required between the falling edge
of the RESET input and the rising edge of the CLOCK
input.
Monitor output (MO). A logic output indicator of the
initial/home state of the translator (45°). At power up the
translator is reset to the home state (phase A and phase B
output currents are both at the half-step position or
70.7%). This output is also high at the 135°, 225°, and
315° positions.
CLOCK (step) input. A low-to-high transition on the
clock input sequences the translator, which controls the
input to the DACs and advances the motor one increment.
The size of the increment is determined by the state of
inputs M1 and M2 (see table 1). The hold state is done by
stopping the CLOCK input regardless of the input level.
Microstep select (M1 and M2). These logic-level
inputs set the translator step mode per table 1. Changes to
these inputs do not take effect until the rising edge of the
clock input.
Direction (CW/CCW) input. This logic-level input sets
the translator step direction. Changes to this input do not
take effect until the rising edge of the clock input.
Internal PWM current control. Each pair of outputs is
controlled by a fixed off-time (7 to 12 μs, depending on
step) PWM current-control circuit that limits the load
current to a desired value (ITRIP). Initially, an output is
enabled and current flows through the motor winding and
RS. When the voltage across the current-sense resistor
equals the DAC output voltage, the current-sense comparator resets the PWM latch, which turns off the driver for the
fixed off time during which the load inductance causes the
current to recirculate for the off time period. The driver is
then re-enabled and the cycle repeats.
Synchronous operation mode. This function prevents occasional motor noise during a “hold” state, which
normally results from asynchronous PWM operation of
both motor phases. A logic high at the SYNC input is
synchronous operation; a logic low is asynchronous
operation. The use of synchronous operation during
normal stepping is not recommended because it produces
less motor torque and can cause motor vibration due to
staircase current.
Sleep mode. Applying a voltage greater than 2 V to the
REF pin disables the outputs and puts the motor in a free
state (coast). This function is used to minimize power
consumption when not in use. Although it disables much
of the internal circuitry including the output MOSFETs
and regulator, the sequencer/translator circuit is active and
therefore a microcontroller can set the step starting point
for the next operation during the sleep mode. When
coming out of sleep mode, wait 100 μs before issuing a
step command to allow the internal circuitry to stabilize.
Table 1. Step Modes
Input
M1
H
H
L
L
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Input
M2
H
L
H
L
Step Mode
Half Step
Quarter Step
Eighth Step
Sixteenth Step
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TRANSLATOR/DRIVERS
Table 2. Step Sequencing
(CW/CCW = L)
Half
Step #
Quarter
Step #
Eighth
Step #
Sixteenth
Step #
Phase A or A\
Current
[%Itripmax]
Phase B or B\
Current
[%Itripmax]
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
70.7
77.3
83.1
88.2
92.4
95.7
98.1
100
100
100
98.1
95.7
92.4
88.2
83.1
77.3
70.7
63.4
55.5
47.1
38.2
29.0
19.5
9.8
0
-9.8
-19.5
-29.0
-38.2
-47.1
-55.5
-63.4
-70.7
-77.3
-83.1
-88.2
-92.4
-95.7
-98.1
-100
-100
-100
-98.1
-95.7
-92.4
-88.2
-83.1
-77.3
-70.7
-63.4
-55.5
-47.1
-38.2
-29.0
-19.5
-9.8
0
9.8
19.5
29.0
38.2
47.1
55.5
63.4
70.7
70.7
63.4
55.5
47.1
38.2
29.0
19.5
9.8
0
-9.8
-19.5
-29.0
-38.2
-47.1
-55.5
-63.4
-70.7
-77.3
-83.1
-88.2
-92.4
-95.7
-98.1
-100
-100
-100
-98.1
-95.7
-92.4
-88.2
-83.1
-77.3
-70.7
-63.4
-55.5
-47.1
-38.2
-29.0
-19.5
-9.8
0
9.8
19.5
29.0
38.2
47.1
55.5
63.4
70.7
77.3
83.1
88.2
92.4
95.7
98.1
100
100
100
98.1
95.7
92.4
88.2
83.1
77.3
70.7
1
1
2
3
1
2
4
5
3
6
7
2
4
8
9
5
10
11
3
6
12
13
7
14
15
4
8
16
17
9
18
19
5
10
20
21
11
22
23
6
12
24
25
13
26
27
7
14
28
29
15
30
31
8
* Home state; MO output high.
16
32
Step
Angle
45*
67.5
90
102.5
135†
157.5
180
202.5
225†
247.5
270
292.5
315†
337.5
360
22.5
45*
† MO output high.
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TRANSLATOR/DRIVERS
Half-step output current waveshapes. For illustrative purposes, phase A\ or B\ current (unipolar
drive) is shown as negative current.
Quarter-step output current waveshapes. For
illustrative purposes, phase A\ or B\ current
(unipolar drive) is shown as negative current.
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SLA7060M THRU SLA7062M
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TRANSLATOR/DRIVERS
Eighth-step output current waveshapes. For
illustrative purposes, phase A\ or B\ current
(unipolar drive) is shown as negative current.
Sixteenth-step output current waveshapes. For
illustrative purposes, phase A\ or B\ current
(unipolar drive) is shown as negative current.
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Applications information
Layout.
The printed wirting board should use a heavy ground
plane.
For optimum electrical and thermal performance, the
driver should be soldered directly into the board.
The driver supply terminal, VBB, should be decoupled
with an electrolytic capacitor (>47 μF is recommended)
placed as close to the device as possible.
To avoid problems due to capacitive coupling of the
high dv/dt switching transients, route the high-level, output
traces away from the sensitive, low-level logic traces.
Always drive the logic inputs with a low source impedance
to increase noise immunity.
Grounding. A star ground system located close to the
driver is recommended. The logic supply return and the
driver supply return should be connected together at only a
single point — the star ground.
Logic supply voltage, VDD. Transients at this terminal
should be held to less than 0.5 V to avoid malfunctioning
operation. Both VBB and VDD may be turned on or off
separately.
Logic inputs. Unused logic inputs (CW/CCW, M1, M2,
RESET, or SYNC) must be connected to either ground or
the logic supply voltage.
Current sensing. To minimize inaccuracies caused by
ground-trace IR drops in sensing the output current level,
the current-sense resistors, RS, should have an independent
ground return to the star ground of the device. This path
should be as short as possible. For low-value sense
resistors, the IR drops in the printed wiring board sense
resistor’s traces can be significant and should be taken into
account. The use of sockets should be avoided as they can
introduce variation in RS due to their contact resistance.
PWM current control. The maximum value of current
limiting (ITRIP) is set by the selection of RS and the voltage
at the REF input with a transconductance function approximated by:
ITRIP = VREF/RS
The required VREF should not be less than 0.1 V. If it is,
RS should be increased for a proportionate increase in
VREF.
RS = 0.1 Ω to 2 Ω
R1 = 10 kΩ
R2 = 5.1 kΩ
R3 = 10 kΩ
CA = 100 μF, 50 V
CB = 10 μF, 10 V
C1 = 0.1 μF
Typical application
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TRANSLATOR/DRIVERS
Applications Information (cont’d)
Continuous
mode
Discontinuous
mode
Sync. signal generator
1.6
Io=1.0A
1.4
1.2
Vds(on) (V)
Reference voltage. In the Typical Application shown,
resistors R1 and R2 set the reference voltage as:
VREF = (VDD x R2)/(R1 + R2)
The trimming of R2 allows for the resistor tolerances
and REF input current. The sum of R1+R2 should be less
than 50 kΩ to minimize the effect of IREF. Raising VREF
above 2 V by activating Q1 causes the sleep mode.
Minimum output current. The Series SLA7060M uses
fixed off-time PWM current control. Due to internal logic
and switching delays, the actual load current peak will be
slightly higher than the calculated ITRIP value (especially
for low-inductance loads). These delays, plus the minimum recommended VREF, limit the minimum value the
current-control circuitry can regulate. An application with
this device should maintain continuous PWM control in
order to obtain optimum torque out of the motor. The
boundary of the load current (IO(min)) between continuous
and discontinuous operation is:
IO(min) = [(VM + VSD)/Rm] x [(1/etoff/[Rm x Lm]) - 1]
where VM = load supply voltage
VF = body diode forward voltage
Rm = motor winding resistance
toff = PWM off time
Lm = motor winding inductance
To produce zero current in a motor, the REF input
should be pulled above 2 V, turning off all drivers.
Synchronous operation mode. If an external signal
is not available to control the synchronous operation
mode, a simple circuit can keep the SYNC input low while
the CLOCK input is active; the SYNC input will go high
(synchronous operation) when the CLOCK input stays low
(“hold”). The RC time constant determines the sync
transition timing.
NOTE –The use of this function except at 0, 70.7, or
100%Itripmax (half-step positions 0 through 8) is not
recommended.
Temperature effects on FET outputs. Analyzing
safe, reliable operation includes a concern for the relationship of NMOS on resistance to junction temperature.
Device package power calculations must include the
increase in on resistance (producing higher on voltages)
1
Io=0.7A
0.8
Io=0.5A
0.6
0.4
0.2
0
-50
-25
0
25
50
75
100
125
150
Junction temperature in C
Normalized FET on resistance
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Applications Information (cont’d)
caused by increased operating junction temperatures. The
figure provides a normalized on-resistance curve, and all
thermal calculations should consider increases from the
given +25°C limits, which may be caused by internal
heating during normal operation.
These power MOSFET outputs feature an excellent
combination of fast switching, ruggedized device design,
low on resistance, and cost effectiveness.
Avalanche energy capability. There is a surge voltage
expected when the output MOSFET turns off, and this
voltage may exceed the MOSFET breakdown voltage
(V(BR)DS). However, the MOSFETs are avalanche type
and as long as the energy (E(AV)), which is imposed on the
MOSFET by the surge voltage, is less than the maximum
allowable value, it is considered to be within its safe
operating area. Note that the maximum allowable avalanche energy is reduced as a function of temperature.
In application, the avalanche energy (E(AV)) dissipated
by the MOSFET is approximated as
E(AV) = VDS(AV) x 0.5 x ID x t
Output circuit for avalanche energy
calculations
SLA7062M
SLA7061M
SLA7060M
Lead temperature TL [°C) at GND pin (#11) close to the package
Allowable avalanche energy
Waveforms during avalanche breakdown
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Terminal list
Pin
Terminal
Name
1, 2
OUTA
Driver outputs for phase A
3, 4
OUTA\
Driver outputs for phase A\
5
SENSEA
6
VDD
Logic power supply, VDD
7
REF
Current set & “sleep” control
8
RESET
9
CW/CCW
10
CLOCK
11
GND
12
M2
Step mode logic control input
13
M1
Step mode logic control input
14
MO
Monitor logic output
15
SYNC
16
VBB
17
SENSEB
18, 19
OUTB\
Driver outputs for phase B\
20, 21
OUTB
Driver outputs for phase B
Terminal Description
Phase A current sense
Logic control input
Forward/reverse logic control input
Step clock input
Supply negative return
Synchronous PWM control input
Driver power supply, VBB
Phase B current sense
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TRANSLATOR/DRIVERS
SLA706xMLF2102
Dimensions in millimeters
NOTES: 1.
2.
3.
4.
Exact body and lead configuration at vendor’s option within limits shown.
Lead spacing tolerance is non-cumulative.
Recommended mounting hardware torque: 0.490 - 0.822 Nm.
Recommended use of metal-oxide-filled, alkyl-degenerated oil-base silicone grease: G746, Shin-Etsu Chemical Co., Ltd.
YG6260, Momentive Performance Materials Inc.; SC102, Dow Corning Toray Co., Ltd..
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• The contents in this document are subject to changes, for improvement and other purposes, without notice. Make sure that this is
the latest revision of the document before use.
• Application and operation examples described in this document are quoted for the sole purpose of reference for the use of the
products herein and Sanken can assume no responsibility for any infringement of industrial property rights, intellectual property
rights or any other rights of Sanken or any third party which may result from its use.
• Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products at a certain rate is inevitable. Users of Sanken products are requested to take, at their own risk, preventative
measures including safety design of the equipment or systems against any possible injury, death, fires or damages to the society
due to device failure or malfunction.
• Sanken products listed in this document are designed and intended for the use as components in general purpose electronic
equipment or apparatus (home appliances, office equipment, telecommunication equipment, measuring equipment, etc.).
When considering the use of Sanken products in the applications where higher reliability is required (transportation equipment and
its control systems, traffic signal control systems or equipment, fire/crime alarm systems, various safety devices, etc.), and whenever
long life expectancy is required even in general purpose electronic equipment or apparatus, please contact your nearest Sanken
sales representative to discuss, prior to the use of the products herein.
The use of Sanken products without the written consent of Sanken in the applications where extremely high reliability is required
(aerospace equipment, nuclear power control systems, life support systems, etc.) is strictly prohibited.
• In the case that you use Sanken products or design your products by using Sanken products, the reliability largely depends on the
degree of derating to be made to the rated values. Derating may be interpreted as a case that an operation range is set by derating
the load from each rated value or surge voltage or noise is considered for derating in order to assure or improve the reliability. In
general, derating factors include electric stresses such as electric voltage, electric current, electric power etc., environmental stresses
such as ambient temperature, humidity etc. and thermal stress caused due to self-heating of semiconductor products. For these
stresses, instantaneous values, maximum values and minimum values must be taken into consideration.
In addition, it should be noted that since power devices or IC’s including power devices have large self-heating value, the degree of
derating of junction temperature affects the reliability significantly.
• When using the products specified herein by either (i) combining other products or materials therewith or (ii) physically, chemically
or otherwise processing or treating the products, please duly consider all possible risks that may result from all such uses in
advance and proceed therewith at your own responsibility.
• Anti radioactive ray design is not considered for the products listed herein.
• Sanken assumes no responsibility for any troubles, such as dropping products caused during transportation out of Sanken’s
distribution network.
• The contents in this document must not be transcribed or copied without Sanken’s written consent.
SANKEN ELECTRIC CO., LTD.
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