™ R ™ iCE65 mobileFPGA as an LVDS, FPD-Link Display Driver SiliconBlue December 1, 2010 (1.2) Application Note AN014 Introduction Traditionally, color graphic displays employ a TTL or LVCMOS signaling interface. Three separate binary-weighted values represent the red, green, and blue constituent colors of a pixel. Such an interface requires between 21 and 28 signal wires for data and control. By contrast, many modern high-resolution, large-format graphic displays use an FPD-Link (Flat Panel Display Link) interface, based around the Low-Voltage Differential Swing (LVDS) I/O standard or an LVDS Display Interface (LDI). Both interfaces reduce the number of signal wires required, which is critical for the compact packaging of today’s electronics, as shown in Figure 1. The display is typically separated from the main body containing most of the electronics. The main body and the display are mechanically connected by some sort of hinge mechanism. Sending a wide, LVCMOS signal cable bundle across the hinge to the display is simply impractical. Likewise, a custom, wide, flex-cable is prohibitively expensive. Figure 1: LVDS-based Display Interfaces Are Critical for Today's Compact Electronics Display Hinge Main body of electronics Laptop Netbook Mobile Internet Device (MID) Mobile Phone Smart Phone FPD-Link Display Basics Figure 2 shows an example RGB-to-FPD-Link interface. The LVDS outputs from the interface connect directly to an FPD-Link or LDI color graphics display. Figure 2 depicts an 18-bit color interface where three separate 6-bit values represent the balance of red, green, and blue. This interface is sometime represented as (6:6:6), representing three 6bit values for red, green, and blue. A 24-bit color interface, (8:8:8), adds another LVDS output pair and recodes the output data. Both interfaces have identical timing and electrical requirements, but use a different number of LVDS output pairs and have different data encoding, as described in “18-bit Color (6:6:6) Encoding” and “24-bit Color (8:8:8) Encoding” starting on page 2. For a given resolution, the data bandwidth at each LVDS output put is identical between 18-bit and 24-bit color modes. © 2010 by SiliconBlue Technologies Corporation. All rights reserved. www.SiliconBlueTech.com (1.2, 1-DEC-2010) 1 iCE65 mobileFPGA as an LVDS, FPD-Link Display Driver Figure 2: 18-bit (6:6:6) FPD-Link Interface to Color Graphics Display 21 lines at 1X clock rate = 3 differential channels at 7X clock rate, 21:3 compression ratio 21 data/control lines Three differential data channels (6 traces) at 7X the clock rate RED[5:0] GREEN[5:0] BLUE[5:0] HSYNC VSYNC FPD-Link Graphics Display Interface DATA ENABLE 18-bit (6:6:6) FPD-Link Color Graphics Display Regenerated clock, same frequency, different duty cycle CLOCK Low-voltage, differential swing (LVDS) channel In an 18-bit (6:6:6) design, the 21 data and control signals from the RGB interface are re-encoded onto three LVDS output pairs plus a regenerated clock output. As described later, the output clock has specific duty-cycle and data alignment requirements. 18-bit Color (6:6:6) Encoding Figure 3 shows the data encoding for the 21 signals in an 18-bit (6:6:6) RGB interface onto three LVDS output data pairs. Each pixel is recoded into seven data transfers across three LVDS pairs. The regenerated clock output has the same frequency as the input clock, but has specific duty-cycle requirements. The rising and falling edges of the associated regenerated output clock signal also provide data alignment information to the receiver. Figure 3: 18-bit Color (6:6:6) FPD-Link Data Encoding CLOCK Previous pixel Current pixel PAIR2 BLU3 BLU2 DEN PAIR1 GRN2 GRN1 BLU1 PAIR0 RED1 RED0 GRN0 Next pixel VSYNC HSYNC BLU5 BLU4 BLU3 BLU2 DEN VSYNC BLU0 GRN5 GRN4 GRN3 GRN2 GRN1 BLU1 BLU0 RED5 RED4 RED3 RED2 RED1 RED0 GRN0 RED5 24-bit Color (8:8:8) Encoding Figure 4 shows the data encoding for the 27 or 28 signals in a 24-bit (8:8:8) RGB interface onto four LVDS output data pairs. Each pixel is recoded into seven data transfers across four LVDS pairs. Again, the regenerated clock output has the same frequency as the input clock, but has specific duty-cycle requirements. The rising and falling edges of the associated regenerated output clock signal also provide data alignment information to the receiver. Figure 4: 24-bit Color (8:8:8) FPD-Link Data Encoding CLOCK Previous pixel Current pixel Next pixel PAIR3 RED1 RED0 CTRL BLU1 BLU0 GRN1 GRN0 RED1 RED0 CTRL BLU1 PAIR2 BLU5 BLU4 DEN VSYNC HSYNC BLU7 BLU6 BLU5 BLU4 DEN VSYNC PAIR1 GRN4 GRN3 BLU3 BLU2 GRN7 GRN6 GRN5 GRN4 GRN3 BLU3 BLU2 PAIR0 RED3 RED2 GRN2 RED7 RED6 RED5 RED4 RED3 RED2 GRN2 RED7 (1.2, 1-DEC-2010) 2 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Data/Clock Rates by Screen Resolution The iCE65P mobileFPGA family supports LVDS output data rates up to the maximum data shown in Table 1. Table 1: Maximum Data Rates for SubLVDS and LVDS on iCE65 mobileFPGAs SubLVDS LVDS Units 1.8 2.5 Volts 210 350 Million bits/sec (Mbps) VCCO_# Voltage Maximum Data Rate (MAX_RATE) Equation 1 shows the relationship between the maximum data rate and supported FPD-Link screen resolutions, based on the product of the number of pixels in a video line (including blanking), the number of lines in a vide frame (including blanking), the number of frames per second, and the number of color bits per pixel. This product is then divided by the number of data channels, which is three (3) for 18-bit color and four (4) for 24-bit color. Equation 1 Pixels Video Lines Frames Color Bits � × × × � bits Frame Video Line Second Pixel ≤MAX_RATE Data Channels second ×channel Table 2 lists a few of the supported FPD-Link screen resolutions for iCE65 mobileFPGAs. For higher-resolution displays, there are two competing limits. The iCE65 LVDS I/O pins support data rates up to 350 Mbps, meaning that the display’s input clock rate must be 50 MHz or less. Many high-resolution displays support a 50 MHz input clock rate but some require an ever higher clock rate, depending on vendor. Table 2: Popular FPD-Link LCD Screen Resolutions Supported by iCE65 mobileFPGAs Pixel Clock (MHz) Data Rate per Channel (Mbps) LCD Screen Format Line Width Number of Lines Pixel per Line Lines per Frame Frames per Second VGA SDTV, 480p PAL SVGA WSVGA WXGA (HD-ready) HD (720p) 640 704 768 800 1,024 480 480 576 600 600 800 858 960 1,056 1,240 525 525 625 632 638 60 59.94 50 60 65 25.20 27.00 30.00 40.04 45.00 176 189 210 280 315 1,280 800 1,300 821 55 49.21 345 1,366 768 1,494 803 48 50.00 350 SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.2, 1-DEC-2010) 3 iCE65 mobileFPGA as an LVDS, FPD-Link Display Driver iCE65 mobileFPGA Solution Figure 5 provides a block diagram for an RGB-to-FPD-Link solution implemented in an iCE65 mobileFPGA. The design essentially supports both 18-bit (6:6:6) and 24-bit (8:8:8) color interfaces with slight modification. A 24-bit interface requires an additional serializer and DDR LVDS output, as shown by comparing Figure 4 to Figure 3. RGB data is first formatted into multiple seven-bit bundles for the 7-to-1 (7:1) serializers. The data encoding is different between 18-bit and 24-bit applications, again as shown in Figure 3 and Figure 4. Figure 5: iCE65 mobileFPGA RGB-to-FPD-Link Solution RED n 7 RGB Interface, Data Formatter BLUE n HSYNC 7:1 Serializer 7 7:1 Serializer 7 7 DATA_ENABLE TXOUT1 TXOUT2 DDR LVDS Output 7:1 Serializer VSYNC TXOUT0 TXOUT3 7X bits/ second 3.5X Clock Domain 1X Phase-Locked 3.5X Loop (PLL) DDR LVDS Output Output Clock Generator 24-bit interface GREEN CLOCK DDR LVDS Output DDR LVDS Output DDR LVDS Output 7:1 Serializer 18-bit interface n TXCLKOUT 1X Clock The output data rate is seven times (7X) the input clock frequency. Because of the potentially high output data rates, the design uses Double Data Rate (DDR) flip-flops located in each iCE65 PIO pin. Each serializer produces two outputs for the DDR LVDS output stage. Each DDR LVDS output, shown in Figure 6, consists of two PIO pins and an external resistor compensation network to generate LVDS signals. The external resistors shown define LVDS output voltage levels; SubLVDS requires different values. One output from the serializer (DATA_0) is clocked out on the rising edge of the 3.5X clock while the other output (DATA_180) is clocked out on the falling edge. The two PIO pins form a complementary LVDS pair. One PIO pin (TXOUT_P) is non-inverting while the other (TXOUT_N) inverts the input data into the DDR output flip-flop. Figure 6: DDR LVDS Output Pair Requires Two PIO Pins Clocked on rising edge DATA_0 Non-inverted data D Data from serializer DATA_180 Clocked on falling edge Q DDR MUX PAD DDR D External resistor network generates LVDS electrical signals RS = 150 Ω Q LVDS pair DDR RP = 140 Ω PIO D Q DDR MUX Inverted data PAD DDR D Clock from PLL, multiplied by 3.5X CLOCK_3P5X TXOUT_P RS = 150 Ω TXOUT_N Q DDR PIO The DDR flip-flops essentially multiply the output data rate by a factor of two. Consequently, most of the internal mobileFPGA logic is clocked at 3.5 times (3.5X) the input clock rate instead of 7 times the clock rate, which has the following effects on the design. 1. Clocking internal logic at half the output rate effective doubles the available timing margin for most of the design. (1.2, 1-DEC-2010) 4 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue 2. Clocking internal logic at half the output rate also requires that data is alternatively clocked on rising and falling clock edges. The 3.5X internal clock is generated by the iCE65P’s internal phase-locked loop (PLL). The output from the PLL is phase aligned to the input clock. Based on available characterization data, keep the LVDS output data rate below 350 million bits per second (350 Mbps), which equates to an input clock rate 50 MHz (350 Mbps divided by 7) or slower. Faster performance may be possible pending further characterization. Clocking Generating Serializer Clock FPD-Link applications require a data rate that is seven times (7X) faster than the basic pixel clock rate. Instead of using a 7X clock within the application, many FPD-Link solutions employ an internal clock that is 3.5 times (3.5X) faster than the pixel clock. The 3.5X clock then drives double-data-rate (DDR) output flip-flops that generate a 7X output data rate (3.5X times 2). There are several advantages to using a 3.5X clock instead of a 7X clock. Because the 3.5X clock operates at half the frequency of a 7X clock, it doubles the clock period which allows more levels of logic between clock edges and simplifies timing requirements. Because the 3.5X clock operates at half the frequency, it also cuts the power consumption in half for the design. Generating a 3.5X generally requires a Phase-Locked Loop (PLL). Fortunately, the iCE65 P-Series mobileFPGAs include an on-chip PLL. The two possible solutions appear below. Generating 3.5X from Pixel Clock Input If the pixel clock is already available in the application, then the PLL in the iCE65P mobileFPGA multiplies the input clock by 3.5 to generate a 3.5X pixel clock, as shown in Figure 7. Figure 7: Generating 3.5X Pixel Clock using PLL Multiply by 3.5 PLL 3.5X Pixel Clock 1X Pixel Clock 1X Pixel Clock Generating 1X and 3.5X Pixel Clock from General Clock Frequency In many applications, the system clock is not a desirable pixel clock. In these applications, use the PLL to generate a frequency that is seven times (7X) faster than the desired pixel clock frequency. Using PLB logic, divide the 7X clock by 7 to generate the desired pixel clock and divide by 2 to generate the 3.5X pixel clock, as shown in Figure 8. Figure 8: Generating 1X and 3.5X Pixel Clock from General Clock Frequency Source Clock PLL 7X PLB Pixel logic Clock ÷2 ÷7 3.5X Pixel Clock 1X Pixel Clock Due to the very high frequency of the 7X clock, the divide-by-7 circuitry requires careful design and placement. See “Placing Logic using a Logic Region” on page 11 for detailed step-by-step instructions. The divide-by-2 circuit is a simple toggle flip-flop. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.2, 1-DEC-2010) 5 iCE65 mobileFPGA as an LVDS, FPD-Link Display Driver FPD-Link Clock and Data Timing Figure 9 shows the clock timing that drives most of the decisions in the design. The Phase-Locked Loop (PLL) and all logic driving the FPD-Link interface are clocked by the rising edge of the input clock. The PLL generates an internal clock that is 3.5 times faster than the input clock. Figure 9: Clock and Data Timing Because of 3.5X clock, output data and regenerated clock are clocked on opposite clock edges ever other clock cycle. Input clock period Pixel Clock (1X) 3.5X Pixel Clock (3.5X) Serialized DDR Output Data 0 1 2 3 4 5 6 0 1 2 3 4 5 6 Generated FPD-Link Clock Regenerated clock edges are aligned with data. Placement of rising and falling edges mark data alignment for receiver. 4 bit periods 3 bit periods Input clock period New graphic data is clocked on every rising edge of the input clock. The Output Clock Generator detects the rising clock edge and generates all the load controls for the serializers, as described in “Serializer Design” on page 6. The outputs from the 7-to-1 serializers are clocked into the DDR LVDS outputs on both the rising and falling edges of the 3.5X clock form the PLL. One of the tricks of the serializer design is that data is clocked on the rising edge during one input clock cycle and clocked on the falling edge during the next cycle. The generated LVDS clock has the same frequency as the input clock signal. However, the output clock has a different duty-cycle and phase relationship. The rising or falling edge of the output clock defines the data alignment for the display’s receiver. The falling clock edge always coincides with the start of data output bit 2 and the rising edge always coincides with the start of data output bit 5. Similarly, the generated output clock is synchronized with the data output. Serializer Design The serializer design is perhaps the most difficult challenge in the application because of the 3.5X clock. Data is clocked on both edges of the 3.5X so that the final output data is seven times the input data rate. Various solutions are possible but the challenges are as follows. Serialized data is clocked on both edges of the 3.5X clock. At various points in the design, there is a critical timing path that crosses from one 3.5X clock edge to the other. Essentially, there are paths that operate at 7X the input clock rate. Ideally, for maximum performance, these crossings are few and have a single load or connection to other logic. Various design trade-offs are possible that use additional logic to improve performance. Figure 10 provides an overview of the solution used in the demonstration design. Two bits of serialized data are sent to the DDR LVDS output during every 3.5X clock cycle—one bit for the rising edge, one bit for the falling edge. (1.2, 1-DEC-2010) 6 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue The seven bits of parallel data are loaded into two four-bit shift registers. One register is clocked on the rising edge of the 3.5X clock, the other on the falling edge. Because seven bits are clocked out every 3.5X clock cycle, the shift registers load even-numbered bits during one serialization period and the odd-numbered bits during the next, as shown in Figure 11. Figure 10: Serializer Design Block Diagram Even Odd Load Even/ Odd Data Load_0 4-bit Parallel Load/Serial Shift Register Serial_Data_0 Odd Even Load Even/ Odd Data Data to DDR LVDS Outputs CROSSING Pre-Load_180 3.5X Clock from PLL 4-bit Parallel Load/Serial Shift Register Serial_Data_180 All of the control logic is generated by the Output Clock Generator, shown in Figure 5 and clocked by the rising edge of the 3.5X clock to simplify timing closure. Additionally, all timing paths are as relaxed as possible. Parallel input data and all controls are stable at least a full 3.5X clock cycle before they are used. The controller synchronizes to the rising edge of the input clock, when new pixel data is available. The controller detects a New Cycle and resynchronizes every two incoming pixels. A Johnson counter tracks the serializer bit position between synchronizations. The Johnson counter reduces overall power consumption and to simplify timing. The counter tracks data for two input clock cycles or two pixels. The Johnson counter also simplifies the decoding for all control outputs. The control logic indicates when new parallel data is loaded into the serializer’s shift registers and whether to load even or odd data. The load control for the falling-edge clocked shift register, Pre-Load_180, is sent to the serializers one cycle early, on the rising edge of the 3.5X clock. The load control is then re-clocked in each serializer onto the falling edge as Load_180, making the load control stable for a full 3.5X clock cycle before it is used. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.2, 1-DEC-2010) 7 iCE65 mobileFPGA as an LVDS, FPD-Link Display Driver Figure 11: Serializer Control Timing 1X Pixel Clock Pixel Clock/2 Pixel Clock/2+1 New Cycle Position Counter 1000 0001 0011 0111 1111 1110 1100 1000 3.5X Clock from PLL Load_0 Pre-Load_180 Load_180 2 3 4 5 6 4 5 6 Serializer Shift Register SHIFT 5 SHIFT 4 SHIFT SHIFT 3 SHIFT SHIFT 2 SHIFT SHIFT 1 LOAD_180 SHIFT 0 LOAD_0 LOAD_180 Serial Data Output SHIFT Operation LOAD_0 Load Even/ Odd Data 6 0 1 2 3 4 5 6 2 3 4 5 6 4 5 6 6 6 Generated FPD-Link Clock Serialized pixel data Serialized pixel data iCEman65P Demonstration Application The design was validated in hardware by connecting a SiliconBlue iCEman65P evaluation kit to a HannStar 10-inch, 1024x600 WSVGA color display. The HannStar display supports an 18-bit (6:6:6) FPD-Link style interface. As shown in Figure 12, the demonstration design consists of the RGB-to-FPD-Link interface described above. A timing control block generates the proper timing for a 1024x600 WSVGA display. A pattern generator provides the red, green, and blue output data. Figure 12: FPD-Link Demonstration Application for iCEman65P RED Pattern Generator LCD Display Timing Controller (48.214 MHz) CLOCK 27 MHz Crystal Oscillator (1.2, 1-DEC-2010) 8 GREEN 6 BLUE 6 HSYNC 6 7:1 Serializer 7 7:1 Serializer RGB Interface, Data Formatter 7 7:1 Serializer 7 VSYNC DDR LVDS Output DDR LVDS Output DDR LVDS Output TXOUT0 TXOUT1 TXOUT2 7X bits/ second (337.5 Mbps) DATA_ENABLE 3.5X Clock Domain 1X Phase-Locked 7X Loop (PLL) (multiply by 12.5) (337.5 MHz) ÷7 ÷2 1X 3.5X (168.75 MHz) Output Clock Generator DDR LVDS Output TXCLKOUT Regenerated 1X Clock SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Clocking for Application Example The iCEman65P board includes a 27 MHz crystal oscillator. Using the mobileFPGA’s PLL, the 27 MHz clock is multiplied by 12.5 to generate a 337.5 MHz clock, which is 7 times faster than the desired pixel clock. The 7X clock is then divided by 7 to generate the 48.214 MHz pixel clock and the 168.75 MHz clock for the serializer (3.5X clock). The 48.214 MHz pixel clock generates a rate slightly faster than 60 frames per second, for demonstration purposes. Figure 13 shows the Synplicity clock constraints. Figure 13: Synplicity Clock Constraints Connector to LCD Display The LCD panel connects to I/O Bank 1 on the iCEman65P board, which already includes the external LVDS output compensation resistors on selected pairs. Table 3 provides a detailed connection list. The connection to the iCEman65P board is via Header J18, a 40-pin stake-pin header with 0.1” (2.54 mm) pin spacing. The connection to the HannStar display is via a FI-XB30SSRL-HF16 (JAE or equivalent) connector. Table 3: iCEman65P Connection to HannStar Display HannStar Display iCEman65P04 FI-XB30SSRL-HF16 (JAE or equiv) Header J18 Example Display Signal Pin Signal Application Pin3: Pin4: Pin5: Pin8: Pin9: Pin10: Pin11: Pin12: Pin13: Pin14: Pin15: Pin16: Pin17: Pin18: Pin26: VDD(+3.3V DC) VDD(+3.3V DC) Backlight ADJ Data0Data0+ GND Data1Data1+ GND Data2Data2+ GND CLKCLK+ VDD_LED_Backlight(+5V DC) SiliconBlue Technologies Corporation www.SiliconBlueTech.com 29 29 1 22 21 12 18 17 12 16 15 30 14 13 11 VCCIO_1 VCCIO_1 B1-IO00 B1-DP04_N B1-DP04_P GND B1-DP02_N B1-DP02_P GND B1-DP01_N B1-DP01_P GND B1-DP00_N B1-DP00_P +5 VDC VCCIO_1 VCCIO_1 — TXOUT_N[0] TXOUT_P[0] GND TXOUT_N[1] TXOUT_P[1] GND TXOUT_N[2] TXOUT_P[2] GND TXCLKOUT_N TXCLKOUT_P — FPGA Ball VCCIO_1 VCCIO_1 D20 P16 R18 GND P18 P15 GND N15 N16 GND E20 F20 — (1.2, 1-DEC-2010) 9 iCE65 mobileFPGA as an LVDS, FPD-Link Display Driver Color Bar Application Example Figure 14 is a photograph showing the HannStar display panel, driven by the iCEman65P evaluation kit board, with a simple color-bar test pattern. The HannStar display panel connects to the 40-pin header connected to the mobileFPGA’s I/O Bank 1 (note the orientation of the board in the figure). The display panel also requires a 3.3V supply, which is provided from the iCEman65P board by setting VCCIO_1 to 3.3V. Figure 14: HannStar 10-inch LCD Display with FPD-Link Interface Driven by iCEman65P Evaluation Kit Figure 15 shows an example oscilloscope output of the FPD-Link interface. The top trace is the generated output clock signal and the bottom trace is one of the LVDS data outputs. Figure 15: Example FPD-Link Transmitter on iCEman65P Evaluation Board Application Example Design Files The application design files are available from your local SiliconBlue sales representative. (1.2, 1-DEC-2010) 10 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue Appendix Placing Logic using a Logic Region The following steps describe how to create a logic region, how to create a logic group, and how to assign logic to a group. Creating a Logic R egion Follow these steps to create a logic region. 1. After synthesizing the design in Synplicty, import the design into iCEcube by double-clicking Import P&R Input Files. 2. Open the Floor Planner by clicking on the Floor Planner icon in the iCEcube tool bar. 3. 4. 5. 6. Click the Region tab. Right-click in the pane. Click Create Region. Click Create Inclusive Region. 7. Locate the Programmable Logic Block (PLB) immediately above the PLL at the center of the bottom edge of the iCE65P04 floor plan. Click and drag to select the entire PLB. 8. Type a name for the region, RGN_CLK_7. 9. Click OK. The region is now defined. SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.2, 1-DEC-2010) 11 iCE65 mobileFPGA as an LVDS, FPD-Link Display Driver Creating a Logic Group 1. Click the Group tab. 2. Right-click in the pane. 3. Select Create Logic Group. 4. Type a name for the logic group, GRP_CLK_7. 5. Assign the logic group to a region from the drop list. 6. Click OK. The logic group is defined and is assigned to a region. Assigning Logic to a Group 1. Click the Logic tab. 2. While holding either the Shift or the Ctrl key, select the desired logic to be added the group. In this example, it is all the logic in the PIXEL_CLOCK_GENERATOR module. 3. Right-click on the selection. 4. Select Add to logic group. (1.2, 1-DEC-2010) 12 SiliconBlue Technologies Corporation www.SiliconBlueTech.com SiliconBlue 5. Assign the selected logic to a previously defined logic group name using the drop list. 6. Click OK. The selected logic is now assigned to a logic group and the logic group was previously assigned to a region. Save the Floor P lan 1. From the iCEcube menu bar, select File Save Floor Planner. 3. Generally, use the default name. Otherwise, specify a name for the constraints file. 4. Check Add the constraint file option 5. Click OK to save the constraints file and add it to the current project. Process Design The design must be processed using the iCEcube software. Related Documents HannStar, HSD100IFW1 10” Color TFT-LCD Module www.siliconbluetech.com/media/downloads/Hannstar10inchHSD100IFW1-A00.pdf SiliconBlue, AN008: Using Differential I/O (LVDS, SubLVDS, LVPECL) in iCE65 mobileFPGAs www.siliconbluetech.com/media/downloads/SiliconBlue_AN008_LVDS.pdf National Semiconductor, AN-1032: An Introduction to FPD-Link www.national.com/an/AN/AN-1032.pdf National Semiconductor, AN-1127: LVDS Display Interface (LDI) TFT Data Mapping for Interoperability with FPD-Link www.national.com/an/AN/AN-1127.pdf SiliconBlue Technologies Corporation www.SiliconBlueTech.com (1.2, 1-DEC-2010) 13 iCE65 mobileFPGA as an LVDS, FPD-Link Display Driver Revision History Version 1.2 Date 1-DEC-2010 1.1 19-NOV-2010 1.0 5-OCT-2010 Description Corrected I/O bank and voltage settings in Figure 14. Updated Figure 3 and Figure 4. Added support for 1280x800 (WXGA, HD-ready) and 1366x768 (HD, 720p) displays in “Data/Clock Rates by Screen Resolution” section on page 3. Initial release. Copyright © 2010 by SiliconBlue Technologies LTD. All rights reserved. SiliconBlue is a registered trademark of SiliconBlue Technologies LTD in the United States. Specific device designations, and all other words and logos that are identified as trademarks are, unless noted otherwise, the trademarks of SiliconBlue Technologies LTD. All other product or service names are the property of their respective holders. SiliconBlue products are protected under numerous United States and foreign patents and pending applications, maskwork rights, and copyrights. SiliconBlue warrants performance of its semiconductor products to current specifications in accordance with SiliconBlue's standard warranty, but reserves the right to make changes to any products and services at any time without notice. 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