1A Ultra Low Dropout Linear Regulator with Programmable Current Limiting ISL80121-5 Features The ISL80121-5 is a low dropout voltage, single output LDO with programmable current limiting. This LDO operates from input voltages of 2.2V to 6V. The ISL80121-5 has a nominal output voltage of 5V. Other custom voltage options are available upon request. • ±1.8% VOUT Accuracy Guaranteed Over Line, Load and TJ = -40°C to +125°C • Very Low 130mV Dropout Voltage at VIN = 5.0V • High Accuracy Current Limit Programmable up to 1.75A • Very Fast Transient Response A sub-micron BiCMOS process is utilized for this product family to deliver the best in class analog performance and overall value. The programmable current limiting improves system reliability of end applications. An external capacitor on the soft-start pin provides an adjustable soft-starting ramp. The ENABLE feature allows the part to be placed into a low quiescent current shutdown mode. • 210µVRMS Output Noise • Power-Good Output • Programmable Soft-Start • Over-Temperature Protection • Small 10 Ld DFN Package This CMOS LDO will consume significantly lower quiescent current as a function of load compared to bipolar LDOs, which translates into higher efficiency and packages with smaller footprints. Quiescent current is modestly compromised to achieve a very fast load transient response. Applications • USB devices • Telecommunications and Networking • Medical Equipment TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS PART NUMBER ILIMIT (DEFAULT) PROGRAMMABLE ISET ISL80101 1.75A No ISL80101A 1.62A Yes ISL80121-5 0.75A Yes • Instrumentation Systems • Routers and Switchers • Gaming Typical Applications 5.4V ±10% VIN CIN ISL80121-5 10 9 10µF 8 ON 7 OFF 6 VIN VOUT VOUT VIN SENSE ISET 2 3 5.4V ±10% VIN COUT CIN 10µF 10µF ISL80121-5 10 9 8 RPG 100kΩ VIN VOUT VIN VOUT SENSE ISET ENABLE SS PG 2 6 LIMIT = 0.75A (default) 1 CSS COUT 10µF RPG 100kΩ 7 OFF RSENSE 10Ω 3 RSET 10kΩ GND 5 I 4 5.0V ±1.8% VOUT 1 ON CSS April 22, 2011 FN7713.3 1 5.0V ±1.8% VOUT ENABLE SS PG 4 GND 5 2.9 I LIMIT = 0.75 + ------------------------------------R SET ( kΩ ) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010, 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners ISL80121-5 Block Diagram SS THERMAL SHUTDOWN V IN CURRENT LIMITER V OUT I SET VOLTAGE REFERENCE PGOOD POWER GOOD SENSE ENABLE GND Ordering Information PART NUMBER (Notes 1, 2, 4) ISL80121IR50Z PART MARKING DZAD VOUT VOLTAGE (Note 3) TEMP. RANGE (°C) 5.0V -40 to +125 PACKAGE (Pb-Free) 10 Ld 3x3 DFN PKG DWG. # L10.3x3 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. The 1.5V, 3.3V and 5V fixed output voltages will be released in the future. Please contact Intersil Marketing for more details. 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL80121-5. For more information on MSL, please see Technical Brief TB363. 2 FN7713.3 April 22, 2011 ISL80121-5 Pin Configuration ISL80121-5 (10 LD 3x3 DFN) TOP VIEW VOUT 1 VOUT 2 SENSE 3 PG 4 7 ENABLE 5 6 SS GND 10 VIN 9 VIN PAD 8 ISET Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1, 2 VOUT 3 SENSE 4 PG 5 GND 6 SS 7 ENABLE 8 ISET Current limit setting. Current limit is 0.75A when this pin is left floating. This default value can be increased by tying RSET to GND, or decreased by tying RSET to VIN. See “Programmable Current Limit” on page 7 in the “Functional Description” for more details. Do not short this pin to ground. 9, 10 VIN Input supply. A minimum of 10µF X5R/X7R input capacitor is required for stability. See “External Capacitor Requirements” on page 8 in “Functional Description” for more details. - EPAD Output voltage. A minimum 10µF X5R/X7R output capacitor is required for stability. See “External Capacitor Requirements” on page 8 in the “Functional Description” for more details. Remote voltage sense for internally fixed VOUT options. Parasitic resistance between the VOUT pin and the load causes small voltage drops which degrade VOUT accuracy. For applications that require a stiff VOUT, connect the sense pin to the load. VOUT in regulation signal. Logic low indicates VOUT is not in regulation, and must be grounded if not used. Ground. External capacitor adjusts in-rush current. VIN-independent chip enable. TTL and CMOS compatible. EPAD at ground potential. Soldering it directly to GND plane is required for thermal considerations. See “Power Dissipation and Thermals” on page 9 for more details. 3 FN7713.3 April 22, 2011 ISL80121-5 Absolute Maximum Ratings Thermal Information (Note 7) VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V VOUT Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V PG, ENABLE, SENSE, SS, ISET Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V ESD Rating Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . .2.5kV Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . 250V Latch Up (Tested per JESD78). . . . . . . . . . . . . . . . . . . . . . .±100mA @ 85°C Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Ld 3x3 DFN Package (Notes 5, 6). . . . . 48 7 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions (Note 8) Junction Temperature Range (TJ) . . . . . . . . . . . . . . . . . . .-40°C to +125°C VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V PG, ENABLE, SENSE, SS, ISET Relative to GND . . . . . . . . . . . . . . . . 0V to 6V PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 7. Absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%. 8. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current = lifetime average current. Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions: VIN = VOUT + 0.4V, VOUT = 5.0V, CIN = COUT = 10µF, TJ = +25°C, ILOAD = 0A. Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to “Functional Description” on page 7 and Tech Brief TB379. Boldface limits apply over the operating temperature range, -40°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA defines established limits. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNITS 1.8 % 1 % DC CHARACTERISTICS DC Output Voltage Accuracy VOUT ΔVOUT/ΔVIN DC Input Line Regulation ΔVOUT DC Output Load Regulation Ground Pin Current IQ Ground Pin Current in Shutdown ISHDN Dropout Voltage (Note 10) VDO Output Current Limit ILIMIT VOUT + 0.4V < VIN < 6V; 0A < ILOAD < 1A -1.8 VOUT + 0.4V < VIN < 6.0V, VOUT = 5.0V 0A < ILOAD < 1A -1 % ILOAD = 0A, 2.2V < VIN < 6V 3 5 mA ILOAD = 1A, 2.2V < VIN < 6V 5 7 mA ENABLE = 0.2V, VIN = 6V 0.2 12 µA ILOAD = 1A, VIN = 5.0V, VSENSE = 0V 90 130 mV 0.75 0.84 A VOUT = 4.75V, VOUT + 0.4V < VIN < 6V, ISET is floating 0.66 VOUT = 4.75V, VOUT + 0.4V < VIN < 6V, RSET = 19.33kΩ 0.9 A Thermal Shutdown Temperature TSD VOUT + 0.4V < VIN < 6V 160 °C Thermal Shutdown Hysteresis (Rising Threshold) TSDn VOUT + 0.4V < VIN < 6V 30 °C PSRR f = 1kHz, ILOAD = 1A 40 dB f = 1kHz, ILOAD = 100mA 40 dB ILOAD = 10mA, BW = 10Hz < f < 100kHz 210 µVRMS AC CHARACTERISTICS Input Supply Ripple Rejection Output Noise Voltage ENABLE PIN CHARACTERISTICS Turn-on Threshold VEN(HIGH) 2.2V < VIN < 6V 0.3 0.8 1.0 V Hysteresis (Rising Threshold) VEN(HYS) 2.2V < VIN < 6V 10 80 200 mV 4 FN7713.3 April 22, 2011 ISL80121-5 Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions: VIN = VOUT + 0.4V, VOUT = 5.0V, CIN = COUT = 10µF, TJ = +25°C, ILOAD = 0A. Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to “Functional Description” on page 7 and Tech Brief TB379. Boldface limits apply over the operating temperature range, -40°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA defines established limits. (Continued) PARAMETER SYMBOL ENABLE Pin Turn-on Delay tEN ENABLE Pin Leakage Current TEST CONDITIONS MIN (Note 9) COUT = 10µF, ILOAD = 1A TYP MAX (Note 9) 100 VIN = 6V, ENABLE = 3V UNITS µs 1 µA SOFT-START CHARACTERISTICS Reset Pull-Down Current IPD Soft-Start Charge Current ICHG ENABLE = 0V, SS = 1V 0.5 1 1.3 mA -3.3 -2 -0.8 µA 75 84 92 %VOUT PG PIN CHARACTERISTICS VOUT PG Flag Threshold VOUT PG Flag Hysteresis 4 PG Flag Low Voltage ISINK = 500µA PG Flag Leakage Current VIN = 6V, PG = 6V % 47 100 mV 0.05 1 µA NOTES: 9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 10. Dropout is defined by the difference in supply VIN and VOUT when the output is below its nominal regulation. 5 FN7713.3 April 22, 2011 ISL80121-5 Typical Operating Performance Unless otherwise noted: VIN = 5.4V, VOUT = 5.0V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. 1.8 150 1.2 0.6 +125°C 90 DVOUT (%) DROPOUT (mV) 120 +25°C 60 0 -0.6 -40°C 30 0 -1.2 0 0.2 0.4 0.6 LOAD CURRENT (A) 0.8 -1.8 -50 1.0 0 25 50 75 3.30 GROUND CURRENT (mA) +25°C 0 -40°C +125°C 150 +25°C 3.25 1.2 -0.6 125 FIGURE 2. OUTPUT VOLTAGE vs TEMPERATURE 1.8 0.6 100 JUNCTION TEMPERATURE (°C) FIGURE 1. DROPOUT VOLTAGE vs LOAD DVOUT (%) -25 -1.2 +125°C 3.20 3.15 -40°C 3.10 3.05 3.00 2.95 2.90 -1.8 0.25 0 0.50 0.75 1.00 2.85 0 0.2 0.4 0.6 0.8 1 LOAD CURRENT (A) OUTPUT CURRENT (A) FIGURE 3. OUTPUT VOLTAGE vs OUTPUT CURRENT FIGURE 4. GROUND CURRENT vs LOAD CURRENT 5.0 4.5 GROUND CURRENT (µA) 4.0 ENABLE (2V/DIV) 3.5 3.0 VIN = 6V 2.5 SS (2V/DIV) 2.0 1.5 VOUT (5V/DIV) 1.0 0.5 0 -40 PG (5V/DIV) -25 -10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 FIGURE 5. SHUTDOWN CURRENT vs TEMPERATURE 6 TIME (2ms/DIV) FIGURE 6. ENABLE START-UP FN7713.3 April 22, 2011 ISL80121-5 Typical Operating Performance 1.0 Unless otherwise noted: VIN = 5.4V, VOUT = 5.0V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued) RSET = 20kΩ 0.9 CURRENT LIMIT (A) 0.8 RSET = OPEN 0.7 0.6 VOUT (50mV/DIV) 0.5 0.4 0.3 IOUT = 500mA 0.2 IOUT = 10mA 0.1 0 -40 10 60 110 TEMPERATURE (°C) TIME (50µs/DIV) FIGURE 7. CURRENT LIMIT vs TEMPERATURE FIGURE 8. LOAD TRANSIENT RESPONSE 60 100mA LOAD 40 LOAD = 100mA COUT = 100µF 50 MAGNITUDE (dB) MAGNITUDE (dB) 1A LOAD 30 20 30 20 COUT = 22µF 10 0 10 COUT = 47µF 40 10 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 9. PSRR vs LOAD Functional Description Input Voltage Requirements The ISL80121-5 is optimized for 5V output, and can operate from input voltages of 2.2V to 6V. Due to the nature of an LDO, VIN must be some margin higher than VOUT plus dropout at the maximum rated current of the application if active filtering (PSRR) is expected from VIN to VOUT. The generous dropout specification of this family of LDOs allows applications to design for a level of efficiency that can accommodate profiles smaller than the TO220/263. Programmable Current Limit 0 10 COUT = 10µF 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 10. PSRR vs C OUT The current limit is set at 0.75A by default when the ISET pin is left floating. This limit can be increased by tying a resistor RSET from the ISET pin to ground. The current limit is determined by RSET as shown in Equation 1: 2.9 I LIMIT = 0.75 + -------------------------R SET ( kΩ ) (EQ. 1) Figure 11 shows the relationship between RSET and the current limit when the RSET is tied from ISET pin to GND. Do not short this pin to ground. Increasing the current limit past 1.75A may cause damage to the part and is highly discouraged. The ISL80121-5 protects against overcurrent due to short-circuit and overload conditions applied to the output. When this happens, the LDO performs as a constant current source. If the short-circuit or overload condition is removed, the output returns to normal voltage regulation operation. 7 FN7713.3 April 22, 2011 ISL80121-5 VIN. PG goes low when the output voltage drops below 84% of the nominal output voltage, the current limit faults, or the input voltage is too low. PG functions during shutdown, but not during thermal shutdown. For applications not using this feature, connect this pin to ground. CURRENT LIMIT (A) 1.7 1.5 Soft-Start Operation 1.3 1.1 0.9 0.7 2 20 RSET (kΩ) 200 FIGURE 11. INCREASING ILIMIT (R SET TO GND) The soft-start circuit controls the rate at which the output voltage rises up to regulation at power-up or LDO enable. This start-up ramp time can be set by adding an external capacitor from the SS pin to ground. An internal 2µA current source charges up this CSS and the feedback reference voltage is clamped to the voltage across it. The start-up time is set by Equation 3: ( C SS x0.5 ) T start = --------------------------2μA (EQ. 3) The current limit can be decreased from the 0.75A default by tying RSET from the ISET pin to VIN. The current limit is then determined by both RSET and VIN following Equation 2: Equation 4 determines the CSS required for a specific start-up in-rush current, where VOUT is the output voltage, COUT is the total capacitance on the output and IINRUSH is the desired in-rush current. 2.9 × ( 2 × V IN – 1 ) I LIMIT = 0.75 – ----------------------------------------------R SET ( kΩ ) ( V OUT xC OUT x2μA ) C SS = -------------------------------------------------I INRUSH x0.5V (EQ. 2) Figure 12 shows the relationship between RSET and the current limit when RSET is tied from the ISET pin to VIN for VIN = 5.4V. The external capacitor is always discharged to ground at the beginning of start-up or enabling. External Capacitor Requirements 0.75 External capacitors are required for proper operation. Careful attention must be paid to the layout guidelines and selection of capacitor type and value to ensure optimal performance. 0.65 0.55 CURRENT LIMIT (A) (EQ. 4) OUTPUT CAPACITOR 0.45 0.35 0.25 0.15 0.05 -0.05 40 RSET (kΩ) 400 FIGURE 12. DECREASING I SET (RSET TO V IN) Enable Operation The ENABLE turn-on threshold is typically 800mV with 80mV of hysteresis. An internal pull-up or pull-down resistor to change these values is available upon request. As a result, this pin must not be left floating, and should be tied to VIN if not used. A 1kΩ to 10kΩ pull-up resistor is required for applications that use open collector or open drain outputs to control the ENABLE pin. The ENABLE pin may be connected directly to VIN for applications with outputs that are always on. The ISL80121-5 applies state-of-the-art internal compensation to keep the selection of the output capacitor simple for the customer. Stable operation over full temperature, VIN range, VOUT range and load extremes are guaranteed for all capacitor types and values assuming a minimum of 10µF X5R/X7R is used for local bypass on VOUT. This output capacitor must be connected to the VOUT and GND pins of the LDO with PCB traces no longer than 0.5cm. There is a growing trend to use very-low ESR multilayer ceramic capacitors (MLCC) because they can support fast load transients and also bypass very high frequency noise from other sources. However, the effective capacitance of MLCCs drops with applied voltage, age, and temperature. X7R and X5R dieletric ceramic capacitors are strongly recommended as they typically maintain a capacitance range within ±20% of nominal voltage over full operating ratings of temperature and voltage. Additional capacitors of any value in ceramic, POSCAP, alum/tantalum electrolytic types may be placed in parallel to improve PSRR at higher frequencies and/or load transient AC output voltage tolerances. Power-Good Operation INPUT CAPACITOR PG is a logic output that indicates the status of VOUT, current limit tripping, and VIN. The PG flag is an open-drain NMOS that can sink up to 10mA during a fault condition. The PG pin requires an external pull-up resistor typically connected to the VOUT pin. The PG pin should not be pulled up to a voltage source greater than For proper operation, a minimum capacitance of 10µF X5R/X7R is required at the input. This ceramic input capacitor must be connected to the VIN and GND pins of the LDO with PCB traces no longer than 0.5cm. 8 FN7713.3 April 22, 2011 ISL80121-5 Power Dissipation and Thermals Thermal Fault Protection The junction temperature must not exceed the range specified in the “Recommended Operating Conditions” on page 4. The power dissipation can be calculated by using Equation 5: The power level and the thermal impedance of the package (+48°C/W for DFN) determine when the junction temperature exceeds the thermal shutdown temperature. In the event that the die temperature exceeds around +160°C, the output of the LDO will shut down until the die temperature cools down to about +130°C. (EQ. 5) P D = ( V IN – V OUT ) × I OUT + V IN × I GND The maximum allowable junction temperature, TJ(MAX) and the maximum expected ambient temperature, TA(MAX) determine the maximum allowable power dissipation, as shown in Equation 6: General PowerPAD Design Considerations (EQ. 6) P D ( MAX ) = ( T J ( MAX ) – T A ) ⁄ θ JA θJA is the junction-to-ambient thermal resistance. For safe operation, ensure that the power dissipation PD, calculated from Equation 5, is less than the maximum allowable power dissipation PD(MAX). The DFN package uses the copper area on the PCB as a heat-sink. The EPAD of this package must be soldered to the copper plane (GND plane). Figure 13 shows a curve for the θJA of the DFN package for different copper area sizes. Figure 14 shows the recommended use of vias on the thermal pad to remove heat from the IC. This typical array populates the thermal pad footprint with vias spaced three times the radius distance from the center of each via. Small via size is advisable, but not to the extent that solder reflow becomes difficult. All vias should be connected to the pad potential, with low thermal resistance for efficient heat transfer. Complete connection of the plated-through hole to each plane is important. It is not recommended to use “thermal relief” patterns to connect the vias. 46 θJA (°C/W) 44 42 40 38 FIGURE 14. PCB VIA PATTERN 36 34 2 4 6 8 10 12 14 16 18 20 22 24 EPAD-MOUNT COPPER LAND AREA ON PCB, mm2 FIGURE 13. 3mmx3mm 10 LD DFN ON 4-LAYER PCB WITH THERMAL VIAS θJA vs EPAD-MOUNT COPPER LAND AREA ON PCB For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN7713.3 April 22, 2011 ISL80121-5 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION 4/22/11 FN7713.3 2/1/11 FN7713.2 CHANGE In Figure 8 on page 7, corrected label from “VOUT (50V/DIV)." to “VOUT (50mV/DIV)." In “DC Output Voltage Accuracy” on page 4, corrected the MAX value from -1.8 to +1.8. 1. page 1, paragraph 2, "The programmable current limiting improves system reliability of applications" changed to "The programmable current limiting improves system reliability of end applications." 2. page 1, Features, "Programmable Soft-starting" changed to "Programmable Soft-Start" 3. Made subbing consistent throughout document. 4. page 3, EPAD Description “directly to GND plane is optional." Changed to "directly to GND plane is required for thermal considerations. See "Power Dissipation and Thermals" on page 9 for more details." 5. page 5, Removed Notes in Electrical Spec Table, which read :"Minimum capacitor of 10µF X5R/X7R on VIN and VOUT required for stability." and "If the current limit for in-rush current is acceptable in application, do not use this feature. Used only when large bulk capacitance required on VOUT for application." 6. page 5, Electrical Specifications, PG Pin Characteristics, Vout PG Flag Threshold a.Typical "85" changed to "84" %Vout 7. page 9, after Thermal Fault Protection section a.Added "General PowerPAD Design Considerations" section with Figure 14. 8. All PGOOD changed to PG throughout. 1/28/11 Changed Theta Ja from 51C/W to 48C/W. 1/25/11 1.page 1, Features a."200µVrms Output Noise" changed to "210 µVrms Output Noise" 2.page 1, Typical Applications, right side figure a.Resize "VOUT" (pin2) and "SENSE" (pin3) 3.page 8, Equation 4 a.Extra parenthesis ")" removed 1/21/11 page 1 Before Features added Table of Key Differences. page 2 Block Dagram - Removed “ADJ Voltage Version” and left the “Sense” Connection. page 3 Pin Number 8, description, 2nd sentence: “Current limit is 0.75mA...” changed to "Current limit is 0.75A…" page 4 Electrical Specifications, AC Characteristics, Input Supply Ripple Rejection Test conditions and Typical values changed from “f = 1kHz, ILOAD = 1A, f = 120Hz, ILOAD = 1A” TO “f = 1kHz, ILOAD = 1A, f = 1kHz, ILOAD = 100mA” page 6, Figure 3 - X-axis label changed from "Output Current (mA)" to "Output Current (A) page 8, Figure 12 - a.Figure label change. "IN" in "VIN" was subscripted. 12/6/10 FN7713.1 1. In “Block Diagram” on page 2: a. Added "ADJ adjustable voltage version" Pin. Added "fixed voltage version" to "SENSE" pin 2. On page 4: “Ground Pin Current” Test Conditions a. Replaced "VOUT+0.4V" with "2.2V" on both lines 12/2/10 FN7713.0 Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL80121-5 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/sear 10 FN7713.3 April 22, 2011 ISL80121-5 Package Outline Drawing L10.3x3 10 LEAD DUAL FLAT PACKAGE (DFN) Rev 6, 09/09 3.00 6 PIN #1 INDEX AREA A B 1 6 PIN 1 INDEX AREA (4X) 3.00 2.00 8x 0.50 2 10 x 0.23 4 0.10 1.60 TOP VIEW 10x 0.35 BOTTOM VIEW 4 (4X) 0.10 M C A B 0.415 PACKAGE OUTLINE 0.200 0.23 0.35 (10 x 0.55) SEE DETAIL "X" (10x 0.23) 1.00 MAX 0.10 C BASE PLANE 2.00 0.20 C SEATING PLANE 0.08 C SIDE VIEW (8x 0.50) C 0.20 REF 5 1.60 0.05 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Lead width applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 11 FN7713.3 April 22, 2011