TI TPS78330DDCT

TPS783xx
www.ti.com
SBVS133 – FEBRUARY 2010
500nA IQ, 150mA, Ultra-Low Quiescent Current
Low-Dropout Linear Regulator
FEATURES
DESCRIPTION
•
•
•
•
•
•
The TPS783 family of low-dropout regulators (LDOs)
offers the benefits of ultra-low power (IQ = 500nA),
and miniaturized packaging.
1
2
•
•
•
•
Low IQ: 500nA
150mA, Low-Dropout Regulator
Low-Dropout at +25°C, 130mV at 150mA
Low-Dropout at +85°C, 175mV at 150mA
3% Accuracy Over Load/Line/Temperature
Available in Fixed Voltage Options Using
Innovative Factory EEPROM Programming
Stable with a 1.0mF Ceramic Capacitor
Thermal Shutdown and Overcurrent Protection
CMOS Logic Level-Compatible Enable Pin
DDC (TSOT23-5) Package
APPLICATIONS
•
•
•
TI MSP430 Attach Applications
Power Rails with Programming Mode
Wireless Handsets, Smartphones, PDAs, MP3
Players, and Other Battery-Operated Handheld
Products
TPS783xxDDC
TSOT23-5
(TOP VIEW)
IN
1
GND
2
EN
3
5
OUT
4
GND
This LDO is designed specifically for battery-powered
applications where ultra-low quiescent current is a
critical parameter. The TPS783, with ultra-low IQ
(500nA),
is
ideal
for
microprocessors,
microcontrollers,
and
other
battery-powered
applications.
The absence of pulldown circuitry at the output of the
TPS783 LDO gives an application the flexibility to use
the regulator output capacitor as a temporary backup
power supply for a short period of time without the
presence of the battery when the LDO is disabled
(during battery replacement).
The ultra-low power and miniaturized packaging allow
designers to customize power consumption for
specific applications. Consult with your local factory
representative for exact voltage options and ordering
information; minimum order quantities may apply.
The TPS783 family is designed to be compatible with
the TI MSP430 and other similar products. The
enable pin (EN) is compatible with standard CMOS
logic. This LDO is stable with any output capacitor
greater than 1.0mF. Therefore, this device requires
minimal board space because of miniaturized
packaging and a potentially small output capacitor.
The TPS783 series also features thermal shutdown
and current limit to protect the device during fault
conditions. All packages have an operating
temperature range of TJ = –40°C to +105°C.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS783xx
SBVS133 – FEBRUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS (1)
Output
Voltage (V)
Output
Voltage (V)
(1)
TPS78315
TPS78318
TPS78319
TPS78320
TPS78322
TPS78323
TPS78325
TPS78326
1.5
1.8
1.9
2.0
2.2
2.3
2.5
2.6
TPS78328
TPS78329
TPS78330
TPS78332
TPS78333
TPS78336
TPS78342
2.8
2.9
3.0
3.2
3.3
3.6
4.2
Additional output voltage options are available on a quick-turn basis using innovative, factory EEPROM programming. Minimum-order
quantities may apply; contact your sales representative for details and availability
ORDERING INFORMATION (1)
PRODUCT
VOUT
TPS783xxyyyz
(1)
XX is the nominal output voltage
YYY is the package designator.
Z is the tape and reel quantity (R = 3000, T = 250).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
At TJ = –40°C to +105°C, unless otherwise noted. All voltages are with respect to GND.
PARAMETER
Input voltage range, VIN
TPS783xx
UNIT
–0.3 to +6.0
V
Enable
–0.3 to VIN + 0.3V
V
Output voltage range, VOUT
–0.3 to VIN + 0.3V
V
Maximum output current, IOUT
Internally limited
Output short-circuit duration
Indefinite
Total continuous power dissipation, PDISS
ESD rating
See Dissipation Ratings Table
Human body model (HBM)
2
500
V
Operating junction temperature range, TJ
–40 to +105
°C
Storage temperature range, TSTG
–55 to +150
°C
(1)
Charged device model (CDM)
kV
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
DISSIPATION RATINGS
BOARD
High-K
(1)
2
(1)
PACKAGE
RqJC
RqJA
DERATING FACTOR
ABOVE TA = +25°C
TA < +25°C
TA = +70°C
TA = +85°C
DDC
90°C/W
200°C/W
5.0mW/°C
500mW
275mW
200mW
The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on top and bottom of the board.
Copyright © 2010, Texas Instruments Incorporated
TPS783xx
www.ti.com
SBVS133 – FEBRUARY 2010
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +105°C), VIN = VOUT(NOM) + 0.5V or 2.2V, whichever is greater;
IOUT = 100mA, VEN = VIN, COUT = 1.0mF, fixed VOUT test conditions, unless otherwise noted. Typical values at TJ = +25°C.
TPS783xx
PARAMETER
VIN
TEST CONDITIONS
Input voltage range
ΔVOUT/ΔVIN
DC output accuracy
Line regulation
(1)
%
–3.0
±2.0
+3.0
%
VOUT(NOM) + 0.5V ≤ VIN ≤ 5.5V
±1.0
%
100mA ≤ IOUT ≤ 150mA
±1.0
%
VIN = 95% VOUT(NOM), IOUT = 150mA
130
86
ICL
Output current limit
VOUT = 0.90 × VOUT(NOM)
IGND
Ground pin current
ISHDN
Shutdown current (IGND)
VEN ≤ 0.4V, VIN(MIN) ≤ VIN < 5.5V
IOUT-SHDN
Output leakage current at
shutdown (2)
VIN = Open, VEN = 0.4V,
VOUT = VOUT(NOM)
VENHI
Enable high-level voltage
VIN = 5.5V
1.2
VENLO
Enable low-level voltage
VIN = 5.5V
0
EN pin current
VIN = VEN = 5.5V
Power-supply rejection ratio
VIN = 4.3V,
VOUT = 3.3V,
IOUT = 150mA
tSTR
Startup time
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
V
+2
Output noise voltage
(3)
UNIT
5.5
±1
VN
PSRR
MAX
–2
BW = 100Hz to 100kHz, VIN = 2.2V,
VOUT = 1.2V, IOUT = 1mA
IEN
(1)
(2)
(3)
Dropout voltage
TJ = +25°C
Over VIN, IOUT, VOUT + 0.5V ≤ VIN ≤ 5.5V,
temperature
100mA ≤ IOUT ≤ 150mA
ΔVOUT/ΔIOUT Load regulation
VDO
TYP
2.2
Nominal
VOUT
MIN
150
IOUT = 0mA
IOUT = 150mA
250
mV
mVRMS
230
400
420
800
8
mA
nA
mA
18
150
nA
170
500
nA
VIN
V
3
0.4
V
40
nA
f = 10Hz
40
dB
f = 100Hz
20
dB
f = 1kHz
15
dB
500
ms
Shutdown, temperature increasing
+160
°C
Reset, temperature decreasing
+140
COUT = 1.0mF, VOUT = 10% VOUT(NOM) to
VOUT = 90% VOUT(NOM)
–40
°C
+105
°C
VDO is not measured for devices with VOUT(NOM) ≤ 2.3V because minimum VIN = 2.2V.
See Shutdown in the Application Information section for more details.
Time from VEN = 1.2V to VOUT = 90% (VOUT(NOM)).
Copyright © 2010, Texas Instruments Incorporated
3
TPS783xx
SBVS133 – FEBRUARY 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
IN
OUT
Current
Limit
Mux
Thermal
Shutdown
EEPROM
EN
Bandgap
Logic
GND
PIN CONFIGURATIONS
DDC PACKAGE
TSOT23-5
(TOP VIEW)
IN
GND
(1)
EN
(1)
1
5
OUT
4
GND
2
3
(1)
All ground pins must be connected to ground for proper operation.
Table 1. PIN DESCRIPTIONS
PIN
NAME
4
DDC
DESCRIPTION
OUT
5
Regulated output voltage pin. A small (1mF) ceramic capacitor is needed from this pin to ground to
assure stability. See the Input and Output Capacitor Requirements in the Application Information
section for more details.
N/C
—
Not connected.
EN
3
Driving the enable pin (EN) over 1.2V turns ON the regulator. Driving this pin below 0.4V puts the
regulator into shutdown mode, reducing operating current to 18nA typical.
GND
2, 4
IN
1
Input pin. A small capacitor is needed from this pin to ground to assure stability. Typical input capacitor
= 1.0mF. Both input and output capacitor grounds should be tied back to the IC ground with no
significant impedance between them.
Thermal pad
—
It is recommended that the thermal pad on the SON-6 package be connected to ground.
ALL ground pins must be tied to ground for proper operation.
Copyright © 2010, Texas Instruments Incorporated
TPS783xx
www.ti.com
SBVS133 – FEBRUARY 2010
TYPICAL CHARACTERISTICS
Over the operating temperature range of TJ = –40°C to +105°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100mA, VEN = VIN, COUT = 1mF, and CIN = 1mF, unless otherwise noted.
TPS78330 LINE REGULATION
IOUT = 5mA, VOUT(NOM) = 3.0V
TPS78330 LINE REGULATION
IOUT = 150mA, VOUT(NOM) = 3.0V
3
1.0
0.8
-40°C
0.6
2
1
+85°C
+25°C
0.2
VOUT (%)
VOUT (%)
0.4
0
+105°C
-0.2
0
+105°C
-1
-0.4
-0.6
-40°C
+25°C
+85°C
-2
-0.8
-3
-1.0
3.5
3.7
3.9
4.1
4.3
4.5
4.7
4.9
5.1
5.5
5.3
3.5
3.7
3.9
4.1
4.3
VIN (V)
4.5
4.7
4.9
5.1
5.5
Figure 1.
Figure 2.
TPS78330 LOAD REGULATION
VIN = 3.5V, VOUT(NOM) = 3.0V
TPS78330 DROPOUT VOLTAGE vs OUTPUT CURRENT
VOUT(NOM) = 3.0V, VIN = 0.95 × VOUT(NOM)
3
200
+85°C
1
-40°C
VDO (VIN - VOUT) (mV)
2
VOUT (%)
5.3
VIN (V)
+25°C
0
+105°C
+85°C
-1
150
+105°C
100
+25°C
50
-40°C
-2
-3
0
0
25
50
75
100
125
150
0
25
50
IOUT (mA)
75
100
125
150
IOUT (mA)
Figure 3.
Figure 4.
TPS78330 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE
VOUT(NOM) = 3.0V, VIN = 0.95 × VOUT(NOM)
VDO (VIN - VOUT) (mV)
250
200
150
100mA
150mA
100
50mA
50
10mA
0
-40 -25 -10
5
20
35
50
65
80
95
110 125
TJ (°C)
Figure 5.
Copyright © 2010, Texas Instruments Incorporated
5
TPS783xx
SBVS133 – FEBRUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ = –40°C to +105°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100mA, VEN = VIN, COUT = 1mF, and CIN = 1mF, unless otherwise noted.
TPS78330 GROUND PIN CURRENT vs INPUT VOLTAGE
IOUT = 0mA, VOUT(NOM) = 3.0V
TPS78330 CURRENT LIMIT vs INPUT VOLTAGE
VOUT = 95% VOUT(NOM), VOUT(NOM) = 3.0V
900
300
800
290
280
700
270
ICL (mA)
IGND (nA)
600
+85°C
500
400
300
240
+25°C
220
+25°C
100
-40°C
250
230
-40°C
200
260
+85°C
210
0
+105°C
200
3.8
4.0
4.4
4.2
4.6
4.8
5.0
5.4 5.5
5.2
3.5
3.7
3.9
4.1
4.5
4.3
VIN (V)
4.7
4.9
5.1
5.3
5.5
VIN (V)
Figure 6.
Figure 7.
TPS78330 ENABLE PIN CURRENT vs INPUT VOLTAGE
IOUT = 100mA, VOUT(NOM) = 3.0V
TPS78330 ENABLE PIN HYSTERESIS vs
JUNCTION TEMPERATURE, IOUT = 1mA, VOUT(NOM) = 3.0V
1.2
3.0
2.7
1.1
+105°C
2.4
1.0
VEN On
0.9
1.8
VEN (V)
IEN (nA)
2.1
1.5
1.2
0.7
+85°C
0.9
0.8
VEN Off
0.6
0.6
0.5
0.3
+25°C
-40°C
0
3.5
3.7
3.9
4.1
4.3
4.5
4.7
4.9
5.1
0.4
5.3
5.5
-40 -25 -10
5
20
35
50
65
80
95
110 125
TJ (°C)
VIN (V)
Figure 8.
Figure 9.
TPS78330 OUTPUT CURRENT LEAKAGE AT SHUTDOWN
VOUT = VOUT(NOM) = 3.0V, VEN = 0.4V
250
ILKG (nA)
200
150
+105°C
100
+85°C
+25°C
50
-40°C
0
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
VOUT (V)
Figure 10.
6
Copyright © 2010, Texas Instruments Incorporated
TPS783xx
www.ti.com
SBVS133 – FEBRUARY 2010
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ = –40°C to +105°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100mA, VEN = VIN, COUT = 1mF, and CIN = 1mF, unless otherwise noted.
TPS78330
%ΔVOUT vs JUNCTION TEMPERATURE
VIN = 3.5V, VOUT(NOM) = 3.0V
TPS78330 OUTPUT SPECTRAL NOISE DENSITY
CIN = 1mF, COUT = 2.2mF, VIN = 3.5V, VOUT(NOM) = 3.0V
3
Output Spectral Noise Density (mV/ÖHz)
100
2
10
150mA
0.1
100mA
10mA
0
150mA
5mA
-1
50mA
1mA = 130mVRMS
50mA = 134mVRMS
150mA = 138.0mVRMS
0.01
DVOUT(NOM) (%)
1
1
-2
1mA
-3
0.001
10
100
1k
10k
100k
5
-40 -25 -10
20
50
65
80
95
Figure 11.
Figure 12.
TPS78330 RIPPLE REJECTION vs FREQUENCY
VIN = 3.5V, VOUT(NOM = 3.0V, COUT = 2.2mF
TPS78330 INPUT VOLTAGE RAMP vs
OUTPUT VOLTAGE
80
110 125
VIN = 0.0V to 5.0V
VOUT = 3.0V
IOUT = 150mA
COUT = 10mF
VIN
70
Voltage (1V/div)
1mA
60
50
50mA
40
Enable
VOUT
Load Current
30
0V
20
Current (50mA/div)
Power-Supply Rejection Ratio (dB)
35
TJ (°C)
Frequency (Hz)
150mA
10
0
10
100
1k
10k
100k
Time (20ms/div)
1M
Frequency (Hz)
Figure 13.
Figure 14.
TPS78330 OUTPUT VOLTAGE vs
ENABLE (SLOW RAMP)
TPS78330 INPUT VOLTAGE vs
DELAY TO OUTPUT
VOUT
Load Current
VIN = 5.5V
VOUT = 3.0V
IOUT = 150mA
COUT = 10mF
Voltage (1V/div)
Enable
Current (50mA/div)
Voltage (1V/div)
VIN
VIN = 5.5V
VOUT = 3.0V
IOUT = 150mA
COUT = 10mF
VIN
VENABLE
VOUT
0V
Time (20ms/div)
Figure 15.
Copyright © 2010, Texas Instruments Incorporated
Time (500ms/div)
Figure 16.
7
TPS783xx
SBVS133 – FEBRUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ = –40°C to +105°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100mA, VEN = VIN, COUT = 1mF, and CIN = 1mF, unless otherwise noted.
Voltage
(100mV/div)
TPS78330
LOAD TRANSIENT RESPONSE
VIN
Enable
VOUT
Load
Current
Current
(10mA/div)
VIN = 5.5V
VOUT = 3.0V
IOUT = 0mA to 10mA
COUT = 10mF
0A
Time (5ms/div)
Figure 17.
8
Copyright © 2010, Texas Instruments Incorporated
TPS783xx
www.ti.com
SBVS133 – FEBRUARY 2010
APPLICATION INFORMATION
APPLICATION EXAMPLES
The TPS783 family of LDOs is factory-programmable
to have a fixed output. Note that during startup or
steady-state conditions, it is important that the EN pin
voltage never exceed VIN + 0.3V.
4.2V to 5.5V
VIN
2.7V
IN
VOUT
OUT
1mF
1mF
TPS78327
EXTENDING BATTERY LIFE IN KEEP-ALIVE
CIRCUITRY APPLICATIONS FOR MSP430
AND OTHER LOW-POWER
MICROCONTROLLERS
One of the primary advantages of a low quiescent
current LDO is its extremely low energy requirement.
Counter-intuitively, this requirement enables a longer
battery life compared to using only the battery as an
unregulated
voltage
supply
for
low-power
microcontrollers such as the MSP430. Figure 19
illustrates the characteristic performance of an
unregulated (3.0V) battery supply versus a regulated
TPS783 supply for a typical MSP430 application.
On
EN
Off
X5R- and X7R-type capacitors are best because they
have minimal variation in value and ESR over
temperature. Maximum ESR should be less than
1.0Ω. With tolerance and dc bias effects, the
minimum capacitance to ensure stability is 1mF.
GND
Figure 18. Typical Application Circuit
90
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
Battery, VCC = 3.0V
TPS783, VCC = 2.2V
80
The TPS783 series are designed to be stable with
standard ceramic capacitors with values of 1.0mF or
larger at the output.
Battery Life (Days)
70
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1mF to 1.0mF low equivalent series resistance
(ESR) capacitor across the input supply near the
regulator. This capacitor counteracts reactive input
sources and improves transient response, noise
rejection, and ripple rejection. A higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated, or if the device is not
located near the power source. If source impedance
is not sufficiently low, a 0.1mF input capacitor may be
necessary to ensure stability.
60
50
40
30
20
10
0
5 10
20
30
40
50
60
70
80
90
100
Duty Cycle (Time in Active Mode) (%)
Calculated with an MSP430F model, operating at 6MHz.
Figure 19. Battery Life Comparison vs Duty Cycle
for MSP430 Application
Table 2 summarizes this comparison.
Table 2. Battery Life Comparison vs Active Mode Time for MSP430 Application
CONDITION/PERFORMANCE
DUTY CYCLE
(%)
TPS783xx
(NO. OF DAYS)
BATTERY
(NO. OF DAYS)
1mA LDO
(NO. OF DAYS)
73%
Efficiency with VBAT = 3.0V and VCC = 2.2V (VO/VI)
—
73%
100%
LDO quiescent current (IQ)
—
0.5mA
0
1mA
MSP430 active current
—
2.19mA
3.09mA
2.19mA
MSP430 low-power current
—
0.5mA
0.6mA
0.5mA
Active mode, 1 sec/hour
0.028
5742
6286
4373
Active mode, 10 sec/hour
0.28
1320
998
1085
Active mode, 100 sec/hour
2.8
151
106
148
Active mode, 1000 sec/hour
28
15.4
10.7
15.4
Active mode, 100% duty cycle (on all the time)
100
4.2
3.0
4.2
Copyright © 2010, Texas Instruments Incorporated
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TPS783xx
SBVS133 – FEBRUARY 2010
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SUPERCAPACITOR-BASED BACKUP
POWER
The very low leakage current at the LDO output gives
a system the flexibility to use the device output
capacitor as a temporary backup power supply for a
short period of time, without the presence of the
battery when the LDO is disabled (during battery
replacement). The leakage current going into the
regulator output from the output capacitor, when the
LDO is disabled, is typically 170nA, see Figure 10.
ILP
IN
OUT
No Battery
COUT
MSP430
10% Duty Cycle
TPS783xx
EN = Low
EN
SVS
GND
150nA = ILKG
Battery Low
Low-Power Mode
SYSTEM EXAMPLE
When the system is active, a voltage supervisor
enables the regulator and puts the MSP430 into
active mode when there is a battery installed and its
voltage is above a certain threshold, as shown in
Figure 20. (The dashed red line indicates the ground
current.)
ImC
IN
OUT
Battery
TPS783xx
MSP430
10% Duty Cycle
EN = High
EN
SVS
GND
Battery OK
500nA
Figure 20. MSP430 Application in Active Mode
When the battery is depleted, the voltage supervisor
signals the user to replace the system battery. Once
the battery is removed, the voltage supervisor
disables the regulator and signals the MSP430 to go
into low-power mode. At this moment, the output
capacitor acts as a power supply for the MSP430
during the absence of the battery while it is being
replaced, as Figure 21 illustrates. (The dashed red
line indicates the ground current.)
Figure 21. MSP430 Application While Battery is
Replaced
The time that the capacitor can provide an
appropriate voltage level to the MSP430 (that is, the
maximum time it should take to replace a depleted
battery with a new battery), or tMAX, can vary from a
few seconds to a few minutes, depending on several
factors, as Equation 1 shows:
• the nominal output of the regulator, VOUT(Nom)
(equivalent to the initial voltage of the capacitor
when the regulator is disabled);
• the minimum voltage required by the MSP430,
VMIN;
• the leakage current into the regulator output, or
ILKG;
• the current demand from the MSP430 in
low-power mode, or ILP; and
• the size of the output capacitor COUT
tMAX
COUT =
VOUT(Nom) - VMIN
ILKG + ILP
(1)
The PMOS pass element in the TPS783 series has a
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
operation is anticipated, external limiting up to the
maximum rated current for the device may be
appropriate.
BOARD LAYOUT RECOMMENDATIONS TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance (such as PSRR, output
noise, and transient response), it is recommended
that the printed circuit board (PCB) be designed with
separate ground planes for VIN and VOUT, with each
ground plane connected only at the GND pin of the
device. In addition, the output capacitor must be as
near to the ground pin of the device as possible to
ensure a common reference for regulation purposes.
High ESR capacitors may degrade PSRR.
10
Copyright © 2010, Texas Instruments Incorporated
TPS783xx
www.ti.com
SBVS133 – FEBRUARY 2010
INTERNAL CURRENT LIMIT
TRANSIENT RESPONSE
The TPS783 is internally current-limited to protect the
regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is
largely independent of output voltage. For reliable
operation, the device should not be operated in a
current limit state for extended periods of time.
As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response. For
more information, see Figure 17.
SHUTDOWN
The TPS783 series are stable with no output load.
Traditional PMOS LDO regulators suffer from lower
loop gain at very light output loads. The TPS783
employs an innovative, low-current circuit under very
light or no-load conditions, resulting in improved
output voltage regulation performance down to zero
output current. See Figure 17 for the load transient
response.
The enable pin (EN) is active high and is compatible
with standard and low-voltage CMOS levels. When
shutdown capability is not required, EN should be
connected to the IN pin, as shown in Figure 22.
4.2V to 5.5V
VIN
2.7V
IN
VOUT
OUT
1mF
1mF
MINIMUM LOAD
THERMAL INFORMATION
TPS78327
THERMAL PROTECTION
EN
GND
Figure 22. Circuit Showing EN Tied High when
Shutdown Capability is Not Required
DROPOUT VOLTAGE
The TPS783 series use a PMOS pass transistor to
achieve low dropout. When (VIN – VOUT) is less than
the dropout voltage (VDO), the PMOS pass device is
the linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass element.
VDO approximately scales with output current
because the PMOS device behaves like a resistor in
dropout. As with any linear regulator, PSRR and
transient response are degraded as (VIN – VOUT)
approaches dropout. This effect is shown in the
Typical Characteristics section. Refer to application
report SLVA207, Understanding LDO Dropout,
available for download from www.ti.com.
Copyright © 2010, Texas Instruments Incorporated
Thermal protection disables the device output when
the junction temperature rises to approximately
+160°C, allowing the device to cool. Once the
junction temperature cools to approximately +140°C,
the output circuitry is enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off again. This cycling limits the dissipation of
the regulator, protecting it from damage as a result of
overheating.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +105°C maximum.
To estimate the margin of safety in a complete design
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions.
The internal protection circuitry of the TPS783 series
has been designed to protect against overload
conditions. However, it is not intended to replace
proper heatsinking. Continuously running the TPS783
series into thermal shutdown degrades device
reliability.
11
TPS783xx
SBVS133 – FEBRUARY 2010
POWER DISSIPATION
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards
are given in the Dissipation Ratings table. Using
heavier copper increases the effectiveness in
removing heat from the device. The addition of plated
through-holes to heat-dissipating layers also
improves the heatsink effectiveness. Power
12
www.ti.com
dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT), as
shown in Equation 2:
PD = (VIN - VOUT) ´ IOUT
(2)
PACKAGE MOUNTING
Solder pad footprint recommendations for the
TPS783 series are available from the Texas
Instruments web site at www.ti.com through the
TPS783 series product folders.
Copyright © 2010, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS78330DDCR
ACTIVE
SOT
DDC
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS78330DDCT
ACTIVE
SOT
DDC
5
250
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS78330DDCR
SOT
DDC
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS78330DDCT
SOT
DDC
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS78330DDCR
SOT
DDC
5
3000
195.0
200.0
45.0
TPS78330DDCT
SOT
DDC
5
250
195.0
200.0
45.0
Pack Materials-Page 2
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