User Guide 008 ISL8002BDEMO1Z Demonstration Board User Guide Description Key Features The ISL8002BDEMO1Z kit is intended for use by individuals with requirements for point-of-load applications sourcing from 2.7V to 5.5V. The ISL8002BDEMO1Z board is used to demonstrate the performance of the ISL8002B low quiescent current mode converter. • Small, compact design • VIN range of 2.7V to 5.5V • VOUT adjustable from 0.6V up to 80% of VIN • IOUT maximum is 2A The ISL8002B is offered in a 8 pin 2mmx2mm TDFN package with 1mm maximum height. The complete converter occupies less than 64mm2 area. • External soft-start programmable Specifications • Over-temperature/thermal protection This board has been configured and optimized for the following operating conditions: References • Output tracking and sequencing • Overcurrent and short-circuit protection ISL8002B Datasheet • VIN = 2.7V to 5.5V Ordering Information • VOUT = 1.8V • VTRACK = 1.8V PART NUMBER • IOUT maximum is 2A • Switching frequency is 2MHz ISL8002BDEMO1Z DESCRIPTION 2A Demonstration Board • Up to 95% peak efficiency • Selectable PFM or PWM operation option FIGURE 1. ISL8002BDEMO1Z TOP SIDE January 22, 2015 UG008.0 1 FIGURE 2. ISL8002BDEMO1Z BOTTOM SIDE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. User Guide 008 What’s Inside PCB Layout Guidelines The demonstration kit contains the following: The PCB layout is a very important converter design step to make sure the designed converter works well. The power loop is composed of the output inductor L’s, the output capacitor COUT, the PHASE’s pins, and the PGND pin. It is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide. The switching node of the converter, the PHASE pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. The input capacitor should be placed as closely as possible to the VIN pin and the ground of the input and output capacitors should be connected as closely as possible. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for better EMI performance. It is recommended to add at least 4 vias ground connection within the pad for the best thermal relief. • The ISL80O2BDEMO1Z • ISL8002B Datasheet Test Steps If tracking feature is not used, connect SS/TR to VIN for 1ms internal soft-start and follow the test steps below: 1. Ensure that the circuit is correctly connected to the supply and loads prior to applying any power. 2. Connect the bias supply to VIN. Plus terminal to VIN (TP1) and negative return to PGND (TP2). 3. Connect the output load to VO (TP3), and the negative return to PGND (TP4). 4. Turn on the power supply. 5. Verify the output voltage is 1.8V for VOUT. Functional Description The ISL8002BDEMO1Z provides a simple platform to evaluate performance of the ISL8002B. The ISL8002B is a highly efficient, monolithic, synchronous step-down DC/DC converter that can deliver up to 2A of continuous output current from a 2.7V to 5.5V input supply. It uses peak current mode control architecture to allow very low duty cycle operation. The ISL8002B operates at a 2MHz switching frequency, thereby providing superior transient response and allowing for the use of small inductor. The ISL8002B can be configured for either PFM (discontinuous conduction) or PWM (continuous conduction) operation at light load. PFM provides high efficiency by reducing switching losses at light loads and PWM reduces noise susceptibility and RF interference. Tied MODE pin to high for PWM or to Ground for PFM. The ISL8002B can be programmable for external soft-start or output tracking and sequencing. Adding a resistor divider from VIN to SS/TR (R5; R4) and a capacitor (C6) from the SS/TR pin to ground determines the output ramp rate, maximum soft-start cap value is 1μF. Adding a resistor divider across SS/TR can be use for outputs tracking. Populate R3 and R4 if Tracking feature is used. Ratio between R1/R2 should equal R3/R4. Otherwise connect SS/TR to VIN for 1ms internal soft-start. Submit Document Feedback 2 UG008.0 January 22, 2015 User Guide 008 ISL8002BDEMO1Z Schematic U1 L1 VIN 1 TP1 EN 2 MODE 3 2 EN C2 22UF PGND 7 3 MODE 4 C1 22UF PHASE 8 1 VIN 4 PG 9 FB 6 TRACK/SS 5 8 1 VO 2 TP3 1.2UH 7 6 C5 22PF A 5 R1 200K C3 22UF C4 22UF EP A L8.2X2B VIN ISL8002B R2 100K R5 TP4 DNP TP2 A A A C6 TRACK OPEN R4 100K 200K R3 TP5 A VIN VIN R7 100K R6 100K ON PWM MODE EN R8 OFF OPEN A Submit Document Feedback 3 R9 OPEN PFM A UG008.0 January 22, 2015 User Guide 008 Bill of Materials MANUFACTURER PART QTY UNITS C2012X5R0J226M 4 EA C1-C4 CAP, SMD, 0805, 22µF, 6.3V, 20%, TDK X5R, ROHS GRM36COG220J050AQ 1 EA C5 CAP, SMD, 0402, 22pF, 50V, 5%, NP0, ROHS 0 EA C6 CAP, SMD, 0402, DNP-PLACE HOLDER, ROHS VLCF4028T-1R2N2R7-2 1 EA L1 COIL-PWR INDUCTOR, WW, SMD, 4mm, 1.2µH, 30%, 2.7A, ROHS TDK 5000 2 EA TP1, TP3 CONN-MINI TEST PT, VERTICAL, RED, ROHS KEYSTONE 5001 3 EA TP2, TP4, TP5 CONN-MINI TEST PT, VERTICAL, BLK, ROHS KEYSTONE ISL8002BIRZ 1 EA U1 IC-2A BUCK REGULATOR, 8P, TDFN, 2X2, ROHS INTERSIL ERJ2RKF1003 2 EA R2, R4 RES, SMD, 0402, 100k, 1/16W, 1%, TF, ROHS PANASONIC MCR01MZPF2003 2 EA R1, R3 RES, SMD, 0402, 200k, 1/16W, 1%, TF, ROHS ROHM 0 EA R5 RES, SMD, 0402, DNP, DNP, DNP, TF, ROHS 2 EA R6, R7 RES, SMD, 0603, 100k, 1/10W, 1%, TF, ROHS 0 EA R8, R9 RES, SMD, 0603, DNP-PLACE HOLDER, ROHS CR0603-10W-1003FT Submit Document Feedback 4 REFERENCE DESIGNATOR DESCRIPTION MANUFACTURER MURATA VENKEL UG008.0 January 22, 2015 User Guide 008 Board Layout FIGURE 3. SILKSCREEN TOP FIGURE 4. LAYER 1 FIGURE 5. LAYER 2 FIGURE 6. LAYER 3 Submit Document Feedback 5 UG008.0 January 22, 2015 User Guide 008 Board Layout (Continued) FIGURE 7. LAYER 4 FIGURE 8. SILKSCREEN BOTTOM Typical Performance Curves EXTERNAL SS PROGRAMMING CSS = 0.1µF VEN 5V/DIV EXTERNAL SS PROGRAMMING CSS = 0.1µF VEN 5V/DIV VOUT 1V/DIV VSS 1V/DIV VOUT 1V/DIV VSS 1V/DIV PG 5V/DIV PG 5V/DIV 500µs/DIV FIGURE 9. START-UP AT 2A LOAD fSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C 100µs/DIV FIGURE 10. SHUTDOWN AT 2A LOAD fSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 6 UG008.0 January 22, 2015 User Guide 008 Typical Performance Curves (Continued) VEN 5V/DIV VEN 5V/DIV VOUT1 1V/DIV VOUT2 1V/DIV VOUT1 1V/DIV PG 2V/DIV VOUT2 1V/DIV PG 2V/DIV 500µs/DIV 100µs/DIV FIGURE 11. COINCIDENTAL VOLTAGE TRACKING START-UP AT FULL LOAD, VIN = 5V, MODE = PWM, TA = +25°C FIGURE 12. COINCIDENTAL VOLTAGE TRACKING SHUTDOWN AT FULL LOAD, VIN = 5V, MODE = PWM, TA = +25°C VEN 5V/DIV VEN 5V/DIV PG1 EN2 5V/DIV PG1 EN2 5V/DIV VOUT 1V/DIV VOUT2 1V/DIV VOUT 1V/DIV VOUT2 1V/DIV 500µs/DIV 100µs/DIV FIGURE 13. SEQUENTIAL START-UP USING EN AND PG AT FULL LOAD, VIN = 5V, MODE = PWM, TA = +25°C FIGURE 14. SEQUENTIAL SHUTDOWN USING EN AND PG AT FULL LOAD, VIN = 5V, MODE = PWM, TA = +25°C VEN1 5V/DIV VEN1 5V/DIV SS1 2V/DIV SS1 2V/DIV VOUT1 1V/DIV VOUT2 1V/DIV VOUT1 1V/DIV VOUT2 1V/DIV 1ms/DIV FIGURE 15. RATIOMETRIC START-UP WITH VOUT1 LEADING VOUT2 AT FULL LOAD, VIN = 5V, MODE = PWM, TA = +25°C Submit Document Feedback 7 1ms/DIV FIGURE 16. RATIOMETRIC SHUTDOWN WITH VOUT1 LEADING VOUT2 AT FULL LOAD, VIN = 5V, MODE = PWM, TA = +25°C UG008.0 January 22, 2015