74AHC157-Q100; 74AHCT157-Q100 Quad 2-input multiplexer Rev. 1 — 4 July 2013 Product data sheet 1. General description The 74AHC157-Q100; 74AHCT157-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74AHC157-Q100; 74AHCT157-Q100 is a quad 2-input multiplexer which selects 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74AHC157-Q100; 74AHCT157-Q100. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common. The 74AHC157-Q100; 74AHCT157-Q100 is logic implementation of a 4-pole, 2-position switch. The logic levels applied to S, determines the position of the switch. The logic equations are: 1Y = E (1I1 S + 1I0 S) 2Y = E (2I1 S + 2I0 S) 3Y = E (3I1 S + 3I0 S) 4Y = E (4I1 S + 4I0 S) This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accept voltages higher than VCC Multiple input enable for easy expansion Ideal for memory chip select decoding Input levels: For 74AHC157-Q100: CMOS level For 74AHCT157-Q100: TTL level 74AHC157-Q100; 74AHCT157-Q100 NXP Semiconductors Quad 2-input multiplexer ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Ordering information Table 1. Ordering information Type number 74AHC157D-Q100 Package Temperature range Name Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal SOT763-1 enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 3.5 0.85 mm 74AHCT157D-Q100 74AHC157PW-Q100 74AHCT157PW-Q100 74AHC157BQ-Q100 74AHCT157BQ-Q100 4. Functional diagram S E 1I1 1Y 1I0 2I1 2Y 2I0 2 3I1 3 5 6 11 10 14 13 3Y 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 3I0 1 S 15 E 4I1 1Y 2Y 3Y 4Y 4 7 9 12 4Y 4I0 Fig 1. Logic diagram 74AHC_AHCT157_Q100 Product data sheet mna484 mna481 Fig 2. logic symbol All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 © NXP B.V. 2013. All rights reserved. 2 of 17 74AHC157-Q100; 74AHCT157-Q100 NXP Semiconductors Quad 2-input multiplexer 1 2 G1 1I0 3 1I1 5 2I0 6 2I1 11 3I0 10 3I1 14 4I0 13 4I1 SELECTOR MULTIPLEXER OUTPUTS 1Y 4 15 2Y 7 2 EN 1 3 3Y MUX 4 1 5 9 7 6 11 4Y 12 9 10 14 S E 1 15 12 13 mna483 Fig 3. Logic symbol mna482 Fig 4. IEC logic symbol 5. Pinning information 5.1 Pinning 6 WHUPLQDO LQGH[DUHD $+&4 $+&74 9&& $+&4 $+&74 , ( , , 9&& ( < , , , , < < , , , < , , < < , *1' < , , *1' , < *1' 6 DDD 7UDQVSDUHQWWRSYLHZ DDD (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration SO16, TSSOP16 74AHC_AHCT157_Q100 Product data sheet Fig 6. Pin configuration DHVQFN16 All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 © NXP B.V. 2013. All rights reserved. 3 of 17 74AHC157-Q100; 74AHCT157-Q100 NXP Semiconductors Quad 2-input multiplexer 5.2 Pin description Table 2. Pin description Symbol Pin Description S 1 common data select input 1I0 to 4I0 2, 5, 11, 14 data inputs from source 0 1I1 to 4I1 3, 6, 10, 13 data inputs from source 1 1Y to 4Y 4, 7, 9, 12 multiplexer outputs GND 8 ground (0 V) E 15 enable input (active LOW) VCC 16 supply voltage 6. Functional description Table 3. Function table[1] Input Output E S nI0 nI1 nY H X X X L L L L X L L L H X H L H X L L L H X H H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 74AHC_AHCT157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 © NXP B.V. 2013. All rights reserved. 4 of 17 74AHC157-Q100; 74AHCT157-Q100 NXP Semiconductors Quad 2-input multiplexer 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +7.0 V VI input voltage IIK input clamping current VI < 0.5 V [1] 0.5 +7.0 V 20 - IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] mA - 20 mA IO output current VO = 0.5 V to (VCC + 0.5 V) - 25 mA ICC IGND supply current - 75 mA ground current 75 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation Tamb = 40 C to +125 C SO16 package [2] - 500 mW TSSOP16 package [3] - 500 mW DHVQFN16 package [4] - 500 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 8 mW/K above 70 C. [3] Ptot derates linearly with 5.5 mW/K above 60 C. [4] Ptot derates linearly with 4.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHC157-Q100 74AHCT157-Q100 Unit Min Typ Max Min Typ Max 2.0 5.0 5.5 4.5 5.0 5.5 V 5.5 0 - 5.5 V 0 - VCC supply voltage VI input voltage 0 - VO output voltage 0 - Tamb ambient temperature 40 +25 +125 40 +25 +125 t/V input transition rise and fall rate VCC = 3.3 V 0.3 V - - 100 - - - ns/V VCC = 5.0 V 0.5 V - - 20 - - 20 ns/V 74AHC_AHCT157_Q100 Product data sheet VCC All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 VCC V C © NXP B.V. 2013. All rights reserved. 5 of 17 74AHC157-Q100; 74AHCT157-Q100 NXP Semiconductors Quad 2-input multiplexer 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V For type 74AHC157-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V HIGH-level VI = VIH or VIL output voltage IO = 50 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 50 A; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = 50 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = 8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.70 - V LOW-level VI = VIH or VIL output voltage IO = 50 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 A; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 A II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 A CI input capacitance - 3.0 10 - 10 - 10 pF CO output capacitance - 4.0 - - - - - pF For type 74AHCT157-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 A 4.4 4.5 - 4.4 - 4.4 - V 3.94 - - 3.8 - 3.70 - V - 0 0.1 - 0.1 - 0.1 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 A IO = 8.0 mA 74AHC_AHCT157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 © NXP B.V. 2013. All rights reserved. 6 of 17 74AHC157-Q100; 74AHCT157-Q100 NXP Semiconductors Quad 2-input multiplexer Table 6. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions VI = 5.5 V or GND; VCC = 0 V to 5.5 V 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - - 0.1 - 1.0 - 2.0 A II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 A ICC additional per input pin; supply current VI = VCC 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 3 10 - 10 - 10 pF CO output capacitance - 4.0 - - - - - pF 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit, see Figure 9. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] CL = 15 pF - 4.4 9.7 CL = 50 pF - 6.3 13.2 - 3.2 6.4 - 4.6 CL = 15 pF - CL = 50 pF Max Min Max Min Max 1.0 11.5 1.0 12.5 ns 1.0 15.0 1.0 16.5 ns 1.0 7.5 1.0 8.0 ns 8.4 1.0 9.5 1.0 10.5 ns 4.8 13.6 1.0 16.0 1.0 17.0 ns - 6.8 17.1 1.0 19.5 1.0 21.5 ns - 3.6 8.6 1.0 10.0 1.0 11.0 ns - 5.2 10.6 1.0 12.0 1.0 13.5 ns CL = 15 pF - 5.9 13.2 1.0 15.5 1.0 16.5 ns CL = 50 pF - 8.4 16.7 1.0 19.0 1.0 21.0 ns CL = 15 pF - 4.2 8.1 1.0 9.5 1.0 10.5 ns CL = 50 pF - 6.0 10.1 1.0 11.5 1.0 13.0 ns For type 74AHC157-Q100 tpd propagation delay nI0, nI1 to nY; see Figure 7 [2] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF S to nY; see Figure 7 [2] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF E to nY; see Figure 8 [2] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 74AHC_AHCT157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 © NXP B.V. 2013. All rights reserved. 7 of 17 74AHC157-Q100; 74AHCT157-Q100 NXP Semiconductors Quad 2-input multiplexer Table 7. Dynamic characteristics …continued GND = 0 V; For test circuit, see Figure 9. Symbol Parameter CPD 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max - 31 - - - - - pF - 13 - - - - - pF CL = 15 pF - 3.2 6.4 1.0 7.5 1.0 8.0 ns CL = 50 pF - 4.6 8.7 1.0 9.8 1.0 11.0 ns - 3.7 8.6 1.0 10.0 1.0 11.0 ns - 5.2 10.4 1.0 12.0 1.0 13.0 ns - 4.7 8.1 1.0 9.5 1.0 10.5 ns - 6.7 10.6 1.0 12.0 1.0 13.5 ns - 41 - - - - - pF - 16 - - - - - pF power CL = 50 pF; fi = 1 MHz; dissipation VI = GND to VCC capacitance 4 outputs switching via S [3] 1 outputs switching via I For type 74AHCT157-Q100 tpd propagation delay nI0, nI1 to nY; see Figure 7 [2] VCC = 4.5 V to 5.5 V S to nY; see Figure 7 VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF E to nY; see Figure 8 [2] VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF CPD power CL = 50 pF; fi = 1 MHz; dissipation VI = GND to VCC capacitance 4 outputs switching via S 1 outputs switching via I [1] [3] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation PD (W). PD = CPD VCC2 fi + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. 74AHC_AHCT157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 © NXP B.V. 2013. All rights reserved. 8 of 17 74AHC157-Q100; 74AHCT157-Q100 NXP Semiconductors Quad 2-input multiplexer 11. Waveforms VI nI0, nI1, S VM input GND t PHL t PLH VOH VM nY output mna486 VOL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Propagation delay input (nI0, nI1, S) to output (nYn) VCC VM E input GND t PHL t PLH VOH VM nY output mna485 VOL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Table 8. Propagation delay input (E) to output (nY) Measurement points Type Input Output VM VM 74AHC157-Q100 0.5VCC 0.5VCC 74AHCT157-Q100 1.5 V 0.5VCC 74AHC_AHCT157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 © NXP B.V. 2013. All rights reserved. 9 of 17 74AHC157-Q100; 74AHCT157-Q100 NXP Semiconductors Quad 2-input multiplexer VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistor S1 = Test selection switch Fig 9. Load circuitry for switching times Table 9. Test data Type Input VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74AHC157-Q100 VCC 3.0 ns 15 pF, 50 pF 1 k open GND VCC 3.0 ns 15 pF, 50 pF 1 k open GND VCC 74AHCT157-Q100 3.0 V 74AHC_AHCT157_Q100 Product data sheet Load S1 position All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 © NXP B.V. 2013. All rights reserved. 10 of 17 74AHC157-Q100; 74AHCT157-Q100 NXP Semiconductors Quad 2-input multiplexer 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT109-1 (SO16) 74AHC_AHCT157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 © NXP B.V. 2013. All rights reserved. 11 of 17 74AHC157-Q100; 74AHCT157-Q100 NXP Semiconductors Quad 2-input multiplexer TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 11. Package outline SOT403-1 (TSSOP16) 74AHC_AHCT157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 © NXP B.V. 2013. All rights reserved. 12 of 17 74AHC157-Q100; 74AHCT157-Q100 NXP Semiconductors Quad 2-input multiplexer DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 0.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT763-1 (DHVQFN16) 74AHC_AHCT157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 © NXP B.V. 2013. All rights reserved. 13 of 17 74AHC157-Q100; 74AHCT157-Q100 NXP Semiconductors Quad 2-input multiplexer 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor LSTTL Low-power Schottky Transistor-Transistor Logic ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model MIL Military CDM Charged-Device Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74AHC_AHCT157_Q100 v.1 20130704 74AHC_AHCT157_Q100 Product data sheet Data sheet status Change notice Supersedes Product data sheet - - All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 © NXP B.V. 2013. All rights reserved. 14 of 17 74AHC157-Q100; 74AHCT157-Q100 NXP Semiconductors Quad 2-input multiplexer 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74AHC_AHCT157_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 © NXP B.V. 2013. All rights reserved. 15 of 17 NXP Semiconductors 74AHC157-Q100; 74AHCT157-Q100 Quad 2-input multiplexer No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74AHC_AHCT157_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 July 2013 © NXP B.V. 2013. All rights reserved. 16 of 17 NXP Semiconductors 74AHC157-Q100; 74AHCT157-Q100 Quad 2-input multiplexer 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 4 July 2013 Document identifier: 74AHC_AHCT157_Q100