[ /Title (CDP1 802AC /3) /Subject (HighReliability CMOS 8-Bit Microprocessor) /Autho r () /Keywords (Intersil Corporation, 8-bit microprocessors, 8 bit microprocessors, peripherals) /Creator () /DOCI NFO pdfmark CDP1802AC/3 High-Reliability CMOS 8-Bit Microprocessor March 1997 Features Description • For Use In Aerospace, Military, and Critical Industrial Equipment The CDP1802A/3 High-Reliability LSI CMOS 8-bit register oriented Central-Processing Unit (CPU) is designed for use as a general purpose computing or control element in a wide range of stored-program systems or products. • Minimum Instruction Fetch-Execute Time of 4.5µs (Maximum Clock Frequency of 3.6MHz) at VDD = 5V, TA = +25oC • Operation Over the Full Military Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC • Any Combination of Standard RAM and ROM Up to 65,536 Bytes • 8–Bit Parallel Organization With Bidirectional Data Bus and Multiplexed Address Bus • 16 x 16 Matrix of Registers for Use as Multiple Program Counters, Data Pointers, or Data Registers • On-Chip DMA, Interrupt, and Flag Inputs • High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of VDD Ordering Information PACKAGE SBDIP TEMP. RANGE (oC) 5V - 3.2MHz PKG NO. -55 to 125 CDP1802ACD3 D40.6 The CDP1802A/3 includes all of the circuits required for fetching, interpreting, and executing instructions which have been stored in standard types of memories. Extensive input/output (I/O) control features are also provided to facilitate system design. The 1800 Series Architecture is designed with emphasis on the total microcomputer system as an integral entity so that systems having maximum flexibility and minimum cost can be realized. The 1800 Series CPU also provides a synchronous interface to memories and external controllers for I/O devices, and minimizes the cost of interface controllers. Further, the I/O interface is capable of supporting devices operating in polled, interrupt-driven, or direct memory-access modes. The CDP1802AC/3 is functionally identical to its predecessor, the CDP1802. The “A” version includes some performance enhancements and can be used as a direct replacement in systems using the CDP1802. This type is supplied in 40 lead dual-in-line sidebrazed ceramic packages (D suffix). Pinout CDP1802AC/3 (SBDIP) TOP VIEW CLOCK 1 WAIT 2 40 VDD 39 XTAL CLEAR 3 38 DMA IN Q 4 37 DMA OUT SC1 5 36 INTERRUPT SC0 6 35 MWR MRD 7 34 TPA BUS 7 8 33 TPB BUS 6 9 32 MA7 BUS 5 10 31 MA6 BUS 4 11 30 MA5 BUS 3 12 29 MA4 BUS 2 13 28 MA3 BUS 1 14 27 MA2 BUS 0 15 26 MA1 VCC 16 25 MA0 N2 17 24 EF1 N1 18 23 EF2 N0 19 22 EF3 VSS 20 21 EF4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 3-30 File Number 1441.2 CDP1802AC/3 ADDRESS BUS CDP1852 INPUT PORT CS2 MA0–7 N0 MA0–4 MA0–7 CS1 MRD MRD CDP1802 8–BIT CPU MRD CDP1833 1K–ROM MWR DATA CS1 CS2 CDP1852 OUTPUT CLOCK PORT MWR N1 CEO TPB DATA TPA TPA DATA 8–BIT DATA BUS FIGURE 1. TYPICAL CDP1802A/3 SMALL MICROPROCESSOR SYSTEM 3-31 CDP1824 32 BYTE RAM CS DATA CDP1802AC/3 Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1802AC/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . .±10mA Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) SBDIP Package. . . . . . . . . . . . . . . . . . . . 55 15 Device Dissipation Per Output Transistor TA = Full Package Temperature Range. . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 ±1/32 In. (1.59 ±0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges PARAMETER MIN MAX UNITS 4 6.5 V VSS VDD V - 1 µs DC Operating Voltage Range Input Voltage Range Maximum Clock Input Rise or Fall Time Performance Specifications VDD (V) -55oC TO +25oC +125oC UNITS Minimum Instruction Time (Note 1) 5 4.5 5.9 µs Maximum DMA Transfer Rate 5 450 340 Kbytes/s Maximum Clock Input Frequency, Load Capacitance (CL) = 50pF, fCL 5 DC-3.6 DC-2.7 MHz PARAMETER NOTE: 1. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3 machine cycles - one Fetch and two Execute operations. Static Electrical Specifications All Limits are 100% Tested -55oC, +25oC CONDITIONS +125oC VOUT (V) VIN, (V) VCC, VDD (V) MIN MAX MIN MAX UNITS - - 5 - 100 - 250 µA 0.4 0, 5 5 1.20 - 0.90 - mA 0.4 5 5 185 - 140 - µA 4.6 0, 5 5 - -0.30 - -0.20 mA 4.6 0 5 - -135 - -100 µA Output Voltage Low-Level, VOL - 0, 5 5 - 0.1 - 0.2 V Output Voltage High-Level, VOH - 0, 5 5 4.9 - 4.8 - V PARAMETER Quiescent Device Current, IDD Output Low Drive (Sink) Current (Except XTAL), IOL XTAL Output High Drive (Source) Current (Except XTAL), IOH XTAL 3-32 CDP1802AC/3 Static Electrical Specifications All Limits are 100% Tested (Continued) -55oC, +25oC CONDITIONS +125oC VOUT (V) VIN, (V) VCC, VDD (V) MIN MAX MIN MAX UNITS Input Low Voltage, VIL 0.5, 4.5 - 5 - 1.5 - 1.5 V Input High Voltage, VIH 0.5, 4.5 - 5 3.5 - 3.5 - V Input Leakage Current, IIN Any Input 0, 5 5 - ±1 - ±5 µA Three-State Output Leakage Current, IOUT 0, 5 0, 5 5 - ±1 - ±5 µA PARAMETER NOTE: 2. 5V level characteristics apply to Part No. CDP1802AC/3, and 5V and 10V level characteristics apply to part No. CDP1802A/3. Timing Specifications As a Function of T (T = 1/fCLOCK), CL = 50 pF LIMITS (NOTE 3) VDD (V) -55oC, +25oC +125oC UNITS 5 2T-450 2T-580 ns High-Order Memory-Address Byte Hold After TPA Time, tH 5 T/2 +0 T/2 +0 ns Low-Order Memory-Address Byte Hold After WR Time, tH 5 T-30 T-40 ns CPU Data to Bus Hold After WR Time, tH 5 T-170 T-250 ns Required Memory Access Time Address to Data, tACC 5 5T-300 5T-400 ns PARAMETER High-Order Memory-Address Byte Setup to TPA Time, tSU NOTE: 3. These limits are not directly tested. Implicit Specifications (Note 4) TA = -55oC to +25oC SYMBOL VDD (V) TYPICAL VALUES UNITS f = 2MHz - 5 4 mW Effective Input Capacitance any Input - CIN - 5 pF Effective Three-State Terminal Capacitance Data Bus - - 7.5 pF Minimum Data Retention Voltage - VDR - 2.4 V Data Retention Current - IDR 2.4 10 µA PARAMETER Typical Total Power Dissipation Idle “00” at M(0000), CL = 50pF NOTE: 4. These specifications are not tested. Typical values are provided for guidance only. 3-33 CDP1802AC/3 Dynamic Electrical Specifications CL = 50pF, Timing Measurement at 0.5 VDD Point -55oC TO +25oC +125oC VDD (V) MIN MAX MIN MAX UNITS Clock to TPA, TPB 5 - 275 - 370 ns Clock-to-Memory High Address Byte, tPLH, tPHL 5 - 725 - 950 ns Clock-to-Memory Low Address Byte Valid, tPLH, tPHL 5 - 340 - 425 ns Clock to MRD, tPLH, tPHL 5 - 340 - 425 ns Clock to MWR, tPLH, tPHL 5 - 275 - 370 ns Clock to (CPU DATA to BUS) Valid, tPLH, tPHL 5 - 430 - 550 ns Clock to State Code, tPLH, tPHL 5 - 440 - 550 ns Clock to Q, tPLH, tPHL 5 - 375 - 475 ns Clock to N (0 - 2), tPLH, tPHL 5 - 400 - 525 ns Data Bus Input Setup, tSU 5 10 - 10 - ns Data Bus Input Hold, t H 5 175 - 230 - ns DMA Setup, tSU 5 10 - 10 - ns DMA Hold, t H 5 200 - 270 - ns Interrupt Setup, t SU 5 10 - 10 - ns Interrupt Hold, tH 5 175 - 230 - ns WAIT Setup, tSU 5 30 - 30 - ns EF1-4 Setup, tSU 5 20 - 20 - ns EF1-4 Hold, tH 5 100 - 135 - ns CLEAR Pulse Width, tWL 5 150 - 200 - ns CLOCK Pulse Width, tWL 5 140 - 185 - ns PARAMETERS Progagation Delay Times, tPLH, tPHL Interface Timing Requirements (Note 5) Required Pulse Width Times NOTE: 5. Minimum input setup and hold times required by Part CDP1802AC/3. 3-34 CDP1802AC/3 0 CLOCK 1 2 3 4 5 6 7 0 tW 00 01 10 11 20 tPLH 30 21 31 40 41 50 51 60 61 70 00 71 01 tPHL TPA tPLH tPHL TPB tSU MEMORY ADDRESS MRD (MEMORY READ CYCLE) tPLH, tPHL tH HIGH ORDER ADDRESS BYTE tPLH tPLH, tPHL LOW ORDER ADDRESS BYTE tPLH, tPHL tPLH tPHL MWR (MEMORY WRITE CYCLE) tPLH tPHL tPLH tPHL DATA FROM CPU TO BUS STATE CODES tPLH, tPHL tPLH tPHL tPLH tPHL tPLH, tPHL Q N0, N1, N2 (I/O EXECUTION CYCLE) tPLH tPHL DATA LATCHED IN CPU DMA DMA REQUEST INTERRUPT SAMPLED (S1, S2) INTERRUPT REQUEST EF 1-4 FLAG LINES SAMPLED (IN SI) tSU SAMPLED (S1, S2, S3) tSU tH tSU tH tH tSU WAIT CLEAR tH tSU DATA FROM BUS TO CPU ANY NEGATIVE TRANSITION tW NOTES: 6. This timing diagram is used to show signal relationships only, and does not represent any specific machine cycle. 7. All measurements are referenced to 50% point of the waveforms. 8. Shaded areas indicate “don’t care” or undefined state. Multiple transitions may occur during this period. FIGURE 2. TIMING WAVEFORMS 3-35 CDP1802AC/3 5 4 VDD = 5V 3 2 1 25 35 45 55 65 75 85 95 105 115 6 TA = 25oC 5 4 LA TE D 6 LOAD CAPACITANCE (CL) = 50pF 7 3 PO 7 0 8 TA = 125oC A LOAD CAPACITANCE (CL) = 50pF EX TR 8 SYSTEM MAXIMUM CLOCK FREQUENCY (fCL) (MHz) SYSTEM MAXIMUM CLOCK FREQUENCY (fCL) (MHz) Performance Curves 2 1 0 125 2 3 4 AMBIENT TEMPERATURE (TA) (oC) FIGURE 3. TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF TEMPERATURE 350 OUTPUT HIGH (SOURCE) CURRENT (IOH -mA) TRANSITION TIME (tTHL, t TLH) (ns) 7 8 9 10 11 12 0 AMBIENT TEMPERATURE (TA) = 25oC 300 250 200 150 tTLH 100 tTHL 50 0 25 50 75 100 125 150 LOAD CAPACITANCE (CL) (pF) 175 GATE TO SOURCE VOLTAGE (VGS) = -5V 1 2 3 4 AMBIENT TEMPERATURE = -40 TO +85oC 5 6 -10 200 -9 -8 -7 -6 -5 -4 -2 -3 -1 0 DRAIN TO SOURCE VOLTAGE (VDS) (V) FIGURE 5. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 35 1000 AMBIENT TEMPERATURE = -40oC TO +85oC TYPICAL POWER DISSIPATION (PD) (mW) OUTPUT LOW (SINK) CURRENT (IOL) (mA) 6 FIGURE 4. TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE 400 0 5 SUPPLY VOLTAGE (VDD) (V) 30 25 20 15 10 GATE TO SOURCE VOLTAGE (VGS) = 5V 5 AMBIENT TEMPERATURE (TA) = 25oC 100 10 V 1 V CC N RA “B ” CH D = VD V CC =5 5V D = VD =+ ” LE “ID 0.1 0.01 0 0 1 2 3 4 5 6 7 8 9 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 10 0.1 1 10 CLOCK INPUT FREQUENCY (f CL) (MHz) NOTES: 9. Idle = “00” at M (0000) 10. Branch = “3707” at M (8107) FIGURE 7. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY FOR BRANCH INSTRUCTION AND IDLE INSTRUCTION 3-36 CDP1802AC/3 Performance Curves (Continued) = V D D = 5V AMBIENT TEMPERATURE (TA) = 25oC 125 C C 100 V ∆ PROPAGATION DELAY TIME (∆tPLH, ∆tPHL) (ns) 150 75 50 H ∆ t PL = 5V L 25 0 V CC = V DD ∆ t PH 0 50 100 150 ∆ LOAD CAPACITANCE (∆ CL) (pF) 200 NOTE: Any output except XTAL. FIGURE 9. TYPICAL CHANGE IN PROPAGATION DELAY AS A FUNCTION OF A CHANGE IN LOAD CAPACITANCE Burn-In Circuit VDD VDD 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 NC VDD NC NC VDD ALL RESISTORS ARE 47kΩ ±20% TYPE CDP1802AC VDD TEMPERATURE TIME 7V +125oC 160 Hours FIGURE 10. BIAS/STATIC BURN-IN CIRCUIT All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3-37