INTERSIL CDP1872CE

CDP1872C,
CDP1874C, CDP1875C
High-Speed 8-Bit Input and Output Ports
March 1997
Features
Description
• Parallel 8-Bit Input/Output Register with Buffered Outputs
The CDP1872C, CDP1874C and CDP1875C devices are
high-speed 8-bit parallel input and output ports designed for
use in the CDP1800 microprocessor system and for general
use in other microprocessor systems. The CDP1872C and
CDP1874C are 8-bit input ports; the CDP1875C is an 8-bit
output port.
• High-Speed Data-In to Data-Out 85ns (Max) at VDD = 5V
• Flexible Applications In Microprocessor Systems as
Buffers and Latches
• High Order Address-Latch Capability in CDP1800Series Microprocessor Systems
• Output Sink Current = 5mA (Min) at VDD = 5V
• Three-State Output - CDP1872C and CDP1874C
Ordering Information
PART
NUMBER
TEMP. RANGE
PACKAGE
PKG.
NO.
CDP1872CE
-40oC to +85oC
PDIP
E22.4
CDP1874CE
-40oC to +85oC
PDIP
E22.4
CDP1875CE
-40oC to +85oC
PDIP
E22.4
These devices have flexible capabilities as buffers and data
latches and are reset by CLR input when the data strobe is
not active.
The CDP1872C and CDP1874C are functionally identical
except for device selects.The CDP1872C has one active low
and one active high select; the CDP1874C has two active
high device selects. These devices also feature Three-state
outputs when deselected. Data is strobed into the register on
the leading edge of the CLOCK and latched on the trailing
edge of the CLOCK.
The CDP1875C is an output port with data latched into the
registers when the device selects are active. There are two
active high and one active low selects. The output buffers
are enabled at all times.
Pinouts
CDP1874C INPUT PORT
(PDIP)
TOP VIEW
CDP1872C INPUT PORT
(PDIP)
TOP VIEW
CDP1875C OUTPUT PORT
(PDIP)
TOP VIEW
CS1
1
22
VDD
CS1
1
22
VDD
CS1
1
22
VDD
DI0
2
21
DI7
DI0
2
21
DI7
DI0
2
21
DI7
DO0
3
20
D07
DO0
3
20
D07
DO0
3
20
D07
DI1
4
19
DI6
DI1
4
19
DI6
DI1
4
19
DI6
D01
5
18
D06
D01
5
18
D06
D01
5
18
D06
DI2
6
17
DI5
DI2
6
17
DI5
DI2
6
17
DI5
D02
7
16
D05
D02
7
16
D05
D02
7
16
D05
DI3
8
15
DI4
DI3
8
15
DI4
DI3
8
15
DI4
D03
9
14
D04
D03
9
14
D04
D03
9
14
D04
CLOCK
10
13
CLR
CLOCK
10
13
CLR
CS3
10
13
CLR
VSS
11
12
CS2
VSS
11
12
CS2
VSS
11
12
CS2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-76
File Number
1255.2
CDP1872C, CDP1874C, CDP1875C
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . . -0.5V to +7V
(Voltage referenced to VSS Terminal)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Resistance (Typical)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Device Dissipation Per Output Transistor
TA = Full Package Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (TA)
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
At TA = -40 to +85oC. For maximum reliability, operating conditions should be selected
so that operation is always within the following ranges:
Recommended Operating Conditions
PARAMETER
LIMITS
ALL TYPES
UNITS
4 to 6.5
V
VSS to VDD
V
DC Operating-Voltage Range
Input Voltage Range
Static Electrical Specifications
At TA = -40 to +85oC, VDD ±5%, Unless Otherwise Specified.
LIMITS
ALL TYPES
TEST CONDITIONS
PARAMETER
VO
(V)
VIN
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
UNITS
Quiescent Device Current
IDD
-
0, 5
5
-
25
50
µA
Output Low Drive (Sink)
Current
IOL
0.4
0, 5
5
5
10
-
mA
Output High Drive (Source)
Current
IOH
4.6
0, 5
5
-4
-7
-
mA
Output Voltage Low-Level
(Note 2)
VOL
-
0, 5
5
-
0
0.1
V
Output Voltage High-Level
(Note 2)
VOH
-
0, 5
5
4.9
5
-
V
Input Low Voltage
VIL
0.5, 4.5
-
5
-
-
1.5
V
Input High Voltage
VIH
0.5, 4.5
-
5
3.5
-
-
V
Input Leakage Current
IIN
-
0, 5
5
-
-
±1
µA
Three-State Output Leakage
Current (Note 3)
IOUT
0, 5
0, 5
5
-
-
±5
µA
Input Capacitance
CIN
-
-
-
-
15
-
pF
COUT
-
-
-
-
15
-
pF
Output Capacitance (Note 3)
NOTES:
1. Typical values are for TA = +25oC and nominal VDD ±5%.
2. IOL = IOH = 1µA
3. For CDP1872C and CDP1874C only.
4-77
CDP1872C, CDP1874C, CDP1875C
Logic Diagrams
CS1
CS1
CS2
DI
CS2
DI
D
CLOCK
C
D
CLOCK
C
DO
Q
DO
Q
R
R
CLR
CLR
FIGURE 1. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES
SHOWN) FOR CDP1872C
DI
CS1
CS2
CS3
FIGURE 2. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES
SHOWN) for CDP1874C
D
C
DO
Q
R
CLR
FIGURE 3. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES SHOWN) FOR CDP1875C
Dynamic Electrical Specifications
At TA = 25oC, VDD 5V, tR, tF = 10ns, VIH = 0.7VDD, VIL = 0.3VDD, CL = 150pF
LIMITS
CDP1872C, CDP1874C
PARAMETER
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
UNITS
INPUT PORT (FIGURE 4)
Output Enable
tEN
-
45
90
ns
Output Disable
tDIS
-
45
90
ns
Clock to Data Out
tCLO
-
45
90
ns
Clear to Output
tCRO
-
80
160
ns
Data In to Data Out
tDIO
-
50
85
ns
Minimum Data Setup Time
tDSU
-
10
30
ns
Data Hold Time
tDH
-
10
30
ns
Minimum Clock Pulse Width
tCL
-
30
60
ns
Minimum Clear Pulse Width
tCR
-
30
60
ns
NOTES:
1. Typical values are for TA = +25oC and VDD ±5%.
2. Maximum values are for TA = +85oC and VDD ±5%
4-78
CDP1872C, CDP1874C, CDP1875C
CSI • CS2
(CDP1872C)
CSI • CS2
(CDP1874C)
tDSU
tDH
CLOCK
tCL
DATA IN
tEN
tCLO
tDIS
DATA BUS
(HIGH Z)
tDIO
tCRO
CLR
tCR
FIGURE 4. TIMING WAVEFORMS FOR CDP1872C AND CDP1874C (INPUT-PORT TYPES)
Dynamic Electrical Specifications
At TA = 25oC, VDD 5V, tR, tF = 10ns, VIH = 0.7VDD, VIL = 0.3VDD, CL = 150pF
LIMITS
CDP1875C
PARAMETER
MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
UNITS
OUTPUT PORT (FIGURE 5)
Clock to Data Out
tCLO
-
50
100
ns
Clear to Output
tCRO
-
80
160
ns
Data In to Data Out
tDIO
-
50
85
ns
Minimum Data Setup Time
tDS
-
10
30
ns
Data Hold Time
tDH
-
10
30
ns
Minimum Clear Pulse Width
tCR
-
30
60
ns
NOTES:
1. Typical values are for TA = +25oC and VDD ±5%.
2. Maximum values are for TA = +85oC and VDD ±5%
CSI • CS2 • CS3 = CLOCK
tDS
tDH
DATA IN
tDIO
DATA OUT
tCLO
tCRO
CLR
tCR
FIGURE 5. TIMING WAVEFORMS FOR CDP1875C (OUTPUT PORT)
4-79
CDP1872C, CDP1874C, CDP1875C
CLOCK
CSI
DO
MRD
DI
DATA IN
CDP1874C
TPA
MA8
•
•
•
MA15
CLOCK
ADDRESS BUS
CDP1802
D0
D1
D2
CDP1874C D3
D4
D5
D6
D7
CS2
CSI
CS3
CS2
CS2
CDP1875C
VDD
DO
DI
TPB
DATA OUT
CS1
DATA BUS
0-7
DATA BUS
FIGURE 6. CDP1874C USED AS AN INPUT PORT AND ADDRESS LATCH WITH CDP1875C USED AS AN OUTPUT PORT
CS2
CLOCK
DATA IN
DATA BUS
CDP1872C
D0 - D7
MRD
N0
A0
N1
A1
N2
A2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
CS1
CS2
CLOCK
CD74HC138
CS1
CDP1802A
CDP1872C
DATA BUS
FIGURE 7. CDP1872C USED AS AN INPUT PORT AND SELECTED BY CD74HC138
4-80
DATA OUT
CDP1872C, CDP1874C, CDP1875C
MRD
CDP1802
N0
CS1
N1
N2
DO - D7
CS2
CS2
TPB
DATA IN
DO
DI
CS3
DI
CDP1874C
CS1
DATA IN
DO
DATA OUT
DO
DATA OUT
CDP1875C
CS2
CS2
DO
DI
CS1
CS1
DI
CDP1874C
CDP1875C
TPB
CS3
MEMORY
FIGURE 8. CDP1874C AND CDP1875C USED AS INPUT/OUTPUT BUFFERS
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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