PI2003 Series Universal Active ORing Controller IC Description Features The PI2003 solution is a universal highspeed Active ORing controller IC designed for use with N-channel MOSFETs and is optimized for -48V redundant power system architectures. The PI2003 Cool-ORing controller enables an extremely low power loss solution with fast dynamic response to input power fault conditions, critical for high availability systems. The PI2003 controls single or parallel MOSFETs to address Active ORing applications protecting against power source failures. The PI2003 is optimized for -48V low-side Active ORing applications. An internal VC shunt regulator enables biasing of the controller directly from -48V (GND). • • The gate drive output turns the MOSFET on during normal steady state operation, while achieving highspeed turn-off during input power source fault conditions, that cause reverse current flow, with auto-reset once the fault clears. The MOSFET drain-to-source voltage is monitored to detect normal forward, excessive forward, light load and reverse current flow. The PI2003 provides an active low fault flag output to the system during excessive forward current, reverse current and light load. • • • • • Typical Applications: • • • • • Optimized for -48V ORing applications Fast Dynamic Response to Power Source failures, with 160ns reverse current turn-off delay time 4A gate discharge current Accurate MOSFET drain-to-source voltage sensing to indicate system level fault conditions Low quiescent current enables biasing directly from -48V (GND). 100V for 100ms operation in low side applications Active low fault flag output Applications Low-side -48Vbus Active ORing N+1 Redundant Power Systems Servers & High End Computing Telecom Systems High current Active ORing Package Information The PI2003 is offered in the following packages: • 10 Lead 3mm x 3mm DFN package • 8 Lead SOIC package Figure 1: PI2003 Low-Side Active ORing Picor Corporation • picorpower.com PI2003 Rev 1.1 Page 1 of 16 Pin Description Pin Name GND GATE Pin Number Description 10 Lead DFN 8 Lead SOIC 1 1 Ground: This pin is ground for the gate driver and control circuitry. 2 Gate Drive Output: This pin drives the gate of the external N-channel MOSFET. Under normal operating conditions, the GATE pin pulls high to VC-0.5V. The controller turns the gate off during a reverse current fault that exceeds the reverse voltage threshold. 2 VC 3 3 Controller Input Supply: This pin is the supply pin for the control circuitry and gate driver. Connect a 1μF capacitor between VC pin and the GND pin. Voltage on this pin is limited to 11V by an internal shunt regulator. For high voltage auxiliary supply applications connect a shunt resistor between VC and the auxiliary supply. FC 5 4 Fault Clamp Input: Connect the FT pin to FC when it is pulled by a resistor to a voltage higher than the VC pin to clamp it to VC plus a diode. Leave this pin open if unused. FT 6 5 Fault State Output: This open collector pin pulls low when a fault occurs. Fault logic inputs are VC Under-Voltage, Reverse Current, Forward Over-Current, and light load. Leave this pin open if unused. SP 7 6 Positive Sense Input & Clamp: Connect SP pin to the Source pin of the external Nchannel MOSFET close to the GND pin. The polarity of the voltage difference between SP and SN provides an indication of current flow direction through the MOSFET. SN 8 7 Negative Sense Input & Clamp: Connect SN to the Drain pin of the external Nchannel MOSFET. The polarity of the voltage difference between SP and SN provides an indication of current flow direction through the MOSFET. Package Pin-Outs 10 Lead DFN (3mm x 3mm) Top view Picor Corporation • picorpower.com 8 Lead SOIC (5mm x 6mm) Top view PI2003 Rev 1.1 Page 2 of 16 Absolute Maximum Ratings VC -0.3V to 17.3V / 40mA SP -0.3V to 8.0V / 10mA -0.3V to 17.3V / 10mA FC, FT GATE -0.3V to 17.3V / 5A SN (Continuous) -0.3V to 80V / 10mA SN (100ms Pulse) 100V / 10mA GND -0.3V / 5A peak Storage Temperature -65oC to 150oC Operating Junction Temperature -40oC to 150°C 250oC Lead Temperature (Soldering, 20 sec) ESD Rating 2kV HBM Electrical Specifications Unless otherwise specified: -40°C < TJ < 125°C, VC =9.5V, CVc = 1uF, CGATE = 4nF Parameter Symbol Min VVC-GND 8.5 Typ Max Units Conditions 9.5 V 1.5 2.0 mA 11 12 V No VC limiting Resistors Normal Operating Condition, No Faults, IVC = 3mA 10 Ω Delta IVC=10mA 8.5 V VC Supply Operating Supply Range (3) Quiescent Current IVC VC Clamp Voltage VVC-CLM VC Clamp Shunt Resistance 10 RVC VC Under-Voltage Rising Threshold VVCUVR VC Under-Voltage Falling Threshold VVCUVF 7.15 7.00 V VVCUV-HS 150 mV Fault Output Low Voltage VFTL 0.2 Fault Output High Leakage Current IFT-LC Fault Delay Time tFT-DEL Fault Clamp (FC to VC) VFC-VC VC Under-Voltage Hysteresis 6.0 FAULT Picor Corporation • picorpower.com 20 0.5 V IFT = 4mA, VC > 4.5V 10 μA VFT=14V 40 60 μs 0.7 1.2 V PI2003 Rev 1.1 IDC ≤ 5mA Page 3 of 16 Electrical Specifications Unless otherwise specified: -40°C < TJ < 125°C, VC =9.5V, CVc = 1uF, CGATE = 4nF Parameter Symbol Min Typ Max Units Conditions DIFFERENTIAL AMPLIFIER AND COMPARATORS Common Mode Input Voltage VCM -0.1 1 V VSP-SN -50 200 mV SP-SN SP Input Bias Current ISP -8 -1 μA SP=SN=1V SN Input Bias Current ISN -8 -1 μA SP=SN=1V SN Leakage Current ISN Differential Operating Input Voltage 7 9 mA VSN = 80V,SP =0V -6 -3 mV SP=SN=1V mV SP=SN=1V VSP-SN = ± 50mV step to 90% of VG max, VBK=0 (minimum blanking) Reverse Comparator Off Threshold VRVS-TH Reverse Comparator Hysteresis VRVS-HS 3 Reverse Fault to Gate Turn-off Delay Time tRVS-MS 160 190 ns Forward Comparator On Threshold VFWD-TH 6 9 mV Forward Comparator Hysteresis Forward Over-Current Comparator Threshold Forward Over-Current Comparator Hysteresis GATE DRIVER VFWD-HS VOC-TH -9 3 -3 135 150 VOC-HS -15 Gate Source Current IG-SC -150 Pull Down Peak Current(1) IG-PD Pull-down Gate Resistance (1) RG-PD Voltage(1) VG-PD AC Gate Pull-down DC Gate Pull-down Voltage to GND Gate Voltage @ VC UVLO Gate Voltage High Gate Fault Condition Clear; % of VC(1) Gate Fall Time 1.5 SP to GND, SN to GND mV 165 mV mV -60 µA 4.0 A 0.3 Ω 0.2 V VG = 1V, Normal Operating Conditions, No Faults VG = 1.5V @ 25°C VG-PD 0.8 1.2 V IG=100mA, in reverse fault VG-UVLO 0.7 VC0.25V 1 V IG =10μA, 4.5V<VC<7.5V VG VC0.5V VVC-G 50 tG-F 10 V % 15 ns 90% to 10% of VG max. Note 1: These parameters are not production tested but are guaranteed by design, characterization and correlation with statistical process control. Note 2: Current sourced by a pin is reported with a negative sign. Note 3: Refer to the Auxiliary Power Supply section in the Application Information for details on the VC requirement to meet the MOSFET Vgs requirement. Picor Corporation • picorpower.com PI2003 Rev 1.1 Page 4 of 16 Functional Description: The PI2003 Cool-ORing controller IC is designed to drive single or paralleled N-channel MOSFETs in Active ORing applications, and optimized for -48V applications. The PI2003 used with an external MOSFET can function as an ideal ORing diode in low side of a redundant power system, significantly reducing power dissipation and eliminating the need for heatsinking. Forward Voltage Comparator: FWD The FWD comparator detects when a forward current condition exists and SP is 6mV(typical) positive with respect to SN. When SP-SN is less than 6mV, the FWD comparator will assert the Fault flag to report a fault condition indicative of a light load or “load not present” condition or possible shorted MOSFET. An N-channel MOSFET in the conduction path offers extremely low on-resistance resulting in a dramatic reduction of power dissipation versus the performance of a diode used in conventional ORing applications. This can allow for the elimination of complex heat sinking and other thermal management requirements. While the gate remains above the gate threshold voltage it will allow current to flow in the forward and reverse direction. Ideal ORing applications do not allow for reverse current flow, so the controller detect reverse current caused by input power source failures and turn off the the MOSFET as quickly as possible. Once the gate voltage falls below the gate threshold, the MOSFET is off and the body diode will be reverse biased preventing reverse current flow and subsequent excessive voltage droop on the redundant bus. During forward over-current conditions the controller maintains gate drive to keep the MOSFET forward drop and power dissipation as low as possible. While conventional ORing solutions using diodes offer no protection against forward over-current conditions. The PI2003 will provide an active-low fault flag to the system via the FT pin. The fault flag is also issued during the reverse current condition, and light load or shorted MOSFET conditions. Forward Over Current Comparator: FOC The FOC comparator indicates an excessive forward current condition when SP is 150mV(typical) higher than SN. When the GATE output voltage is greater than 50% of the VC voltage and SP-SN is higher than 150mV, the PI2003 will initiate a fault condition via the FT pin. Differential Amplifier: The PI2003 integrates a high-speed low offset voltage differential amplifier to sense the difference between the Sense Positive (SP) pin voltage and Sense Negative (SN) pin voltage with high accuracy. The amplifier output is connected to three comparators: Reverse comparator, Forward comparator, and Forward over-current comparator. Reverse Current Comparator: RVS The reverse current comparator provides the most critical function in the controller, detecting negative voltage caused by reverse current. When the SN pin is 6mV higher than the SP pin, the reverse comparator will enable the gate discharge circuit and turn off the MOSFETs in typically 160ns. The reverse comparator has typically 3mV of hysteresis referenced to SP-SN. Picor Corporation • picorpower.com VC and Internal Voltage Regulator: The PI2003 has a separate input (VC) that provides power to the control circuitry and the gate driver. An internal regulator clamps the VC voltage (VVC-CLM ) to 11V. VC may be tied to a voltage higher than VVC-CLM through a resistor to limit VC current. The internal regulator circuit has a comparator to monitor VC voltage and initiates a FAULT condition when VC is lower than the VC Under-Voltage Threshold, 7.15V Gate Driver: The gate driver (GATE) output is configured to drive an external N-channel MOSFET. In the high state, the gate driver applies a 150µA current source to the MOSFET gate limited to the VC voltage. When a reverse current fault is initiated, the gate driver pulls the GATE pin low and discharges the FET gate with 4 Apeak capability. When the input source voltage is applied before the MOSFET is fully enhanced, a voltage greater than the Forward Over Current (FOC) Threshold may be present across the MOSFET. To avoid an erroneous FOC detection, a VGS detector blanks the FOC and FWD comparators from initiating a fault, until the GATE pin reaches 50% of VC pin voltage. Fault: The fault circuit output is an open collector with 40μs delay to prevent any false triggering. The FT pin will be pulled low when any of the following faults occur: • Reverse current • Forward Over-Current and VG > ½ VC • Forward Low-Current and VG > ½ VC PI2003 Rev 1.1 Page 5 of 16 • VC pin Under-Voltage Reverse current is the only fault condition that initiates gate turn-off of the MOSFET (as well as a fault flag signal). Forward Over-Current and Forward Low-Current fault conditions issue a fault flag signal to the FT pin, but do not affect the gate of the MOSFET. The FT pin serves as an indicator that a fault condition may be present. This information can be reported to a Host to signal that some system level maintenance may be required. The FT pin can be connected to VC pin or system logic bias voltage via a current limiting resistor. When pulling up FT to an unregulated voltage connect FC to FT . FC will clamp FT voltage to one diode drop above VC. This current will return to ground through the internal shunt. Figure 2: PI2003 Controller Internal Block Diagram (10 Lead DFN package pin out shown) Figure 3: Comparator hysteresis, values are for reference only, please refer to the electrical specifications Picor Corporation • picorpower.com PI2003 Rev 1.1 Page 6 of 16 Figure 4: PI2003 State Diagram Picor Corporation • picorpower.com PI2003 Rev 1.1 Page 7 of 16 Figure 5: Timing diagram for two PI2003 controllers in a low side Active ORing application Picor Corporation • picorpower.com PI2003 Rev 1.1 Page 8 of 16 Typical Characteristics: Figure 6: Controller bias current vs. temperature Figure 8: Reverse condition gate turn-off delay time vs. temperature. Figure 10: VC clamp voltage vs. temperature. Picor Corporation • picorpower.com Figure 7: VC UVLO threshold vs. temperature Figure 9: Reverse comparator threshold vs. temperature. VCM: Common Mode Voltage. Figure 11: Gate output source current vs. temperature PI2003 Rev 1.1 Page 9 of 16 Application Information: enhance the MOSFET. The maximum gate to VC voltage loss (headroom), VHDVC-G is 0.5V. VHDVC-G specification is the Gate Voltage High (VG) in the Gate Driver section under the Electrical Specification. The PI2003 is designed to replace ORing diodes in high current redundant power architectures. Replacing a traditional diode with a PI2003 controller IC and a low on-state resistance Nchannel MOSFET will result in significant power dissipation reduction as well as board space reduction, efficiency improvement and additional protection features. This section describes in detail the procedure to follow when designing with the PI2003 Active ORing controller and N-Channel MOSFETs. The following is a low side Active ORing design example. If the bus voltage is higher than 11V then a bias resistor (Rbias) is required, and should be connected between the PI2003 VC pin and supply. The resistor is selected based on the input voltage range. Rbias = Fault Indication: FT output pin is an open collector output and should be pulled up to the logic voltage or to the controller VC via a resistor (10KΩ). Also the FT output can be pulled with a current limiting resistor directly to an unregulated voltage source, such as the return of a -48V bus. In this condition connect the FT pin to the FC pin for clamping. Vbus min − VC clamp IC max Rbias maximum power dissipation: Pd Rbias = (Vbus max − VC clamp ) 2 Rbias Rbias maximum power dissipation is at maximum input voltage and minimum clamp voltage (11V). Where: Vbusmin : V(bus) minimum voltage Vbus max : V(bus) maximum voltage Also the FT pin can be used to drive an LED or opto-coupler device. The circuit in figure 12a shows a PI2003 configuration for an LED/opto-coupler that will turn on during a fault condition. The FC connection protects the FT pin if the LED is open. VC Clamp : Controller clamp voltage, 11V IC max Use the circuit in figure 12b to turn on the LED/optocoupler when there is no fault and to turn off during a fault condition. : Controller maximum bias current (2.0mA) Note: If the FT pin is connected to the VC pin via a resistor (RFT), the FT sink current ( I FT ) during a fault condition should be added to the maximum bias current IC max in the above equations. The FT pin sink current during a fault can be calculated using the following approximate equation: I FT = Figure 12a: Fault circuit where the LED turns on during a fault. VC clampMax R FT N-Channel MOSFET Selection: There are several factors that affect the MOSFET selection including cost, on-state resistance (Rds(on)), current rating, power dissipation, thermal conductivity, drain-to-source breakdown voltage (BVdss), gate-to-source voltage rating (Vgs), and gate threshold voltage (Vgs(TH)). The first step is to select suitable MOSFETs based on the BVdss requirement for the application. The BVdss voltage rating should be higher than the applied Vin voltage plus expected transient voltages. Stray parasitic inductance in the circuit can also contribute to significant transient voltage conditions, particularly during MOSFET turn-off after a reverse Figure 12b: Fault circuit where the LED turns off during a fault. VC Power Source: The PI2003 VC input voltage should be higher than the required gate-to-source voltage (Vgs) to fully Picor Corporation • picorpower.com PI2003 Rev 1.1 Page 10 of 16 current fault has been detected. In Active ORing applications when one of the input power sources is shorted, a large reverse current is sourced from the circuit output through the MOSFET. Depending on the output impedance of the system, the reverse current may reach over 60A in some conditions before the MOSFET is turned off. Such high current conditions will store energy even in a small parasitic element. For example, a 1nH parasitic inductance with 60A reverse current will store 1.8µJ (½Li2). When the MOSFET is turned off, the stored energy will be released and will produce high negative voltage ringing at the MOSFET source. This event will create a high voltage difference across the drain and source of the MOSFET. The MOSFET current rating and maximum power dissipation are closely related. Generally the lower the MOSFET Rds(on), the higher the current capability and the lower the resultant power dissipation. This leads to reduced thermal management overhead, but will ultimately be higher cost compared to higher Rds(on) parts. It is important to understand the primary design goal objectives for the application in order to effectively trade off the performance of one MOSFET versus another. Rds(on) and PI2003 sensing: The PI2003 senses the MOSFET source-to-drain voltage drop via the SP and SN pins to determine the status of the current through the MOSFET. When the MOSFET is fully enhanced, its source-todrain voltage is equal to the MOSFET on-state resistance multiplied by the source current, VSD = Rds(on)*Is. The reverse current threshold is set for -6mV and when the differential voltage between the SP & SN pins is more negative than -6mV, i.e. SPSN≤-6mV, the PI2003 detects a reverse current fault condition and pulls the MOSFET gate pin low, thus turning off the MOSFET and preventing further reverse current. The reverse current fault protection disconnects the power source fault condition from the redundant bus, and allows the system to keep running. Under normal conditions the GATE pin output voltage will rail to the VC voltage minus 0.5V, where the VC output is regulated to 11V typically to support any MOSFET with a Vgs rating of ±12V or greater. A Vgs rating ≥ 12V is very common for industry standard N-Channel MOSFETs. Power dissipation in active ORing circuits is derived from the total source current and the on-state resistance of the selected MOSFET. MOSFET power dissipation: Pd MOSFET = Is 2 ∗ Rds(on) Where : Is : Source Current Rds(on) : MOSFET on-state resistance Note: In the calculation use Rds(on) at maximum MOSFET temperature because Rds(on) is temperature dependent. Refer to the normalized Rds(on) curves in the MOSFET manufacturers datasheet. Some MOSFET Rds(on) values may increase by 50% at 125°C compared to values at 25°C. The Junction Temperature rise is a function of power dissipation and thermal resistance. TriseMOSFET = RthJA ∗ PdMOSFET = RthJA ∗ Is 2 ∗ Rds(on) , Where: RthJA : Junction-to-Ambient thermal resistance Picor Corporation • picorpower.com PI2003 Rev 1.1 Page 11 of 16 Typical application Example 1: Requirement: Redundant Bus Voltage = -48V (-36V to -60V, 100V for 100ms transient) Load Current = 5A load (assume through each redundant path) Maximum Ambient Temperature = 60°C Solution: A single PI2003 with a suitable MOSFET for each redundant -48V power source should be used and configured as shown in figure 13. The VC is biased from the return line through a bias resistor. Select a suitable N-Channel MOSFET: Select the N-Channel MOSFET with voltage rating higher than the input voltage, Vin, plus any expected transient voltages, with a low Rds(on) that is capable of supporting the full load current with margin. For instance, a 100V rated MOSFET with 10A current capability is suitable. An exemplary MOSFET having these characteristic is Si4486EY from Vishay Siliconix. ⎛ 50°C ⎞ TJ max = 60°C + ⎜ ∗ (5.0 A)2 ∗ 43mΩ⎟ = 113°C W ⎝ ⎠ FT pin: Connect the FT pin to to the logic power supply or to the VC pin via a resistor (RFT). Make RFT large (120KΩ) to lower FT sink current. I FT − Sink = VC: Connect each controller to the return path with a separate bias resistor, Rbias. Rbias = Rbias = 1% Vbus min − VC clampMax IC max + I FT − Sink 36V − 12V = 11.47 KΩ , or 11.5KΩ, 2.0mA + 0.092mA Rbias maximum power dissipation is at maximum input voltage and minimum clamp voltage. Pd Rbias = From Si4486EY datasheet: • N-Channel MOSFET • VDS= 100V • ID = 23A continuous drain current at 125°C • • • VC 11.0V = = 92μA R FT 120 KΩ (Vbus max − VC clampMIN ) 2 Rbias = (60V − 12V ) 2 = 200mW 11.5 KΩ VGS(MAX) = ± 20V RθJA= 50°C/W RDS(on)=20mΩ typical at VGS=10V, TJ=25°C Reverse current threshold is: Is.reverse = Vth.reverse − 6mV = = −300mA Rds(on) 20mΩ Power dissipation: Rds(on) is 25mΩ maximum at 25°C and will increase as the temperature increases. Add 40°C to maximum ambient temperature to compensate for the temperature rise due to power dissipation. At 100°C (60°C + 40°C) Rds(on) will increase by 63%. Rds(on) = 25mΩ ∗1.63 = 41mΩ maximum at 100°C Maximum Junction temperature ⎛ 50°C ⎞ ∗ (5.0 A)2 ∗ 41mΩ⎟ = 111°C TJ max = 60°C + ⎜ ⎝ W ⎠ Figure 13: PI2003 in low side -48V application. Recalculate based on calculated Junction temperature, 115°C. At 115°C Rds(on) will increase by 72%. Rds(on) = 25mΩ ∗1.72 = 43mΩ maximum at 115°C Picor Corporation • picorpower.com PI2003 Rev 1.1 Page 12 of 16 Layout Recommendation: Use the following general guidelines when designing printed circuit boards. An example of the typical land pattern for a DFN PI2003 and SO-8/PowerPak MOSFET is shown in Figure 14: • It is best to connect the gate of the MOSFET to the GATE pin of the controller with a short and wide trace. • Connections from the SP and SN pins to the MOSFET source and drain pins respectively should be as short as possible • The VC bypass capacitor (C1 and C2) should be located as close as possible to the VC and GND pins. Place the PI2003 and VC bypass capacitor on the same layer of the board. • Connect all MOSFET source pins together with a wide trace to reduce trace parasitics and to accommodate the high current input. Similarly, connect all MOSFET Drain pins together with a wide trace to accommodate the high current output. Figure 24: PI2003 Mounted on PI2003-EVAL1 Figure 14: PI2003 and MOSFET layout example Figure 25: PI2003-EVAL1 performance under an input short Please visit www.picorpower.com for information on PI2003-EVAL1 Picor Corporation • picorpower.com PI2003 Rev 1.1 Page 13 of 16 Package Drawings 8 Lead SOIC Picor Corporation • picorpower.com PI2003 Rev 1.1 Page 14 of 16 Package Drawings 10 Lead DFN Ordering Information Part Number PI2003-00-QEIG PI2003-00-SOIG Package Transport Media 3mm x 3mm 10 Lead DFN 8 Lead SOIC T&R T&R Picor Corporation • picorpower.com PI2003 Rev 1.1 Page 15 of 16 Warranty Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to the original purchaser only. EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR LIMITED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies Vicor against all damages. Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems. Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are available upon request. Specifications are subject to change without notice. Vicor Corporation 25 Frontage Road Andover, MA 01810 USA Picor Corporation 51 Industrial Drive North Smithfield, RI 02896 USA Customer Service: [email protected] Technical Support: [email protected] Tel: 800-735-6200 Fax: 978-475-6715 Picor Corporation • picorpower.com PI2003 Rev 1.1 Page 16 of 16